1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Probe module for 8250/16550-type Exar chips PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. 8 */ 9#include <linux/acpi.h> 10#include <linux/dmi.h> 11#include <linux/io.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/pci.h> 15#include <linux/property.h> 16#include <linux/serial_core.h> 17#include <linux/serial_reg.h> 18#include <linux/slab.h> 19#include <linux/string.h> 20#include <linux/tty.h> 21#include <linux/8250_pci.h> 22#include <linux/delay.h> 23 24#include <asm/byteorder.h> 25 26#include "8250.h" 27 28#define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 29#define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d 30#define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c 31#define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 32#define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 33#define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db 34#define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea 35 36#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 37#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 38#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 39#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 40#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 41#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 42#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 43 44#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 45#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 46 47#define PCI_SUBDEVICE_ID_USR_2980 0x0128 48#define PCI_SUBDEVICE_ID_USR_2981 0x0129 49 50#define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 51#define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 52#define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004 53#define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008 54#define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010 55 56#define UART_EXAR_INT0 0x80 57#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 58#define UART_EXAR_SLEEP 0x8b /* Sleep mode */ 59#define UART_EXAR_DVID 0x8d /* Device identification */ 60 61#define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 62#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ 63#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ 64#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 65#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 66#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 67#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 68 69#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 70#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 71 72#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 73#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 74#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 75#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 76#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 77#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 78#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 79#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 80#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 81#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 82#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 83#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 84 85#define UART_EXAR_RS485_DLY(x) ((x) << 4) 86 87/* 88 * IOT2040 MPIO wiring semantics: 89 * 90 * MPIO Port Function 91 * ---- ---- -------- 92 * 0 2 Mode bit 0 93 * 1 2 Mode bit 1 94 * 2 2 Terminate bus 95 * 3 - <reserved> 96 * 4 3 Mode bit 0 97 * 5 3 Mode bit 1 98 * 6 3 Terminate bus 99 * 7 - <reserved> 100 * 8 2 Enable 101 * 9 3 Enable 102 * 10 - Red LED 103 * 11..15 - <unused> 104 */ 105 106/* IOT2040 MPIOs 0..7 */ 107#define IOT2040_UART_MODE_RS232 0x01 108#define IOT2040_UART_MODE_RS485 0x02 109#define IOT2040_UART_MODE_RS422 0x03 110#define IOT2040_UART_TERMINATE_BUS 0x04 111 112#define IOT2040_UART1_MASK 0x0f 113#define IOT2040_UART2_SHIFT 4 114 115#define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ 116#define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ 117 118/* IOT2040 MPIOs 8..15 */ 119#define IOT2040_UARTS_ENABLE 0x03 120#define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ 121 122struct exar8250; 123 124struct exar8250_platform { 125 int (*rs485_config)(struct uart_port *, struct serial_rs485 *); 126 const struct serial_rs485 *rs485_supported; 127 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); 128}; 129 130/** 131 * struct exar8250_board - board information 132 * @num_ports: number of serial ports 133 * @reg_shift: describes UART register mapping in PCI memory 134 * @setup: quirk run at ->probe() stage 135 * @exit: quirk run at ->remove() stage 136 */ 137struct exar8250_board { 138 unsigned int num_ports; 139 unsigned int reg_shift; 140 int (*setup)(struct exar8250 *, struct pci_dev *, 141 struct uart_8250_port *, int); 142 void (*exit)(struct pci_dev *pcidev); 143}; 144 145struct exar8250 { 146 unsigned int nr; 147 struct exar8250_board *board; 148 void __iomem *virt; 149 int line[]; 150}; 151 152static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) 153{ 154 /* 155 * Exar UARTs have a SLEEP register that enables or disables each UART 156 * to enter sleep mode separately. On the XR17V35x the register 157 * is accessible to each UART at the UART_EXAR_SLEEP offset, but 158 * the UART channel may only write to the corresponding bit. 159 */ 160 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0); 161} 162 163/* 164 * XR17V35x UARTs have an extra fractional divisor register (DLD) 165 * Calculate divisor with extra 4-bit fractional portion 166 */ 167static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, 168 unsigned int *frac) 169{ 170 unsigned int quot_16; 171 172 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); 173 *frac = quot_16 & 0x0f; 174 175 return quot_16 >> 4; 176} 177 178static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, 179 unsigned int quot, unsigned int quot_frac) 180{ 181 serial8250_do_set_divisor(p, baud, quot, quot_frac); 182 183 /* Preserve bits not related to baudrate; DLD[7:4]. */ 184 quot_frac |= serial_port_in(p, 0x2) & 0xf0; 185 serial_port_out(p, 0x2, quot_frac); 186} 187 188static int xr17v35x_startup(struct uart_port *port) 189{ 190 /* 191 * First enable access to IER [7:5], ISR [5:4], FCR [5:4], 192 * MCR [7:5] and MSR [7:0] 193 */ 194 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); 195 196 /* 197 * Make sure all interrups are masked until initialization is 198 * complete and the FIFOs are cleared 199 */ 200 serial_port_out(port, UART_IER, 0); 201 202 return serial8250_do_startup(port); 203} 204 205static void exar_shutdown(struct uart_port *port) 206{ 207 unsigned char lsr; 208 bool tx_complete = false; 209 struct uart_8250_port *up = up_to_u8250p(port); 210 struct circ_buf *xmit = &port->state->xmit; 211 int i = 0; 212 213 do { 214 lsr = serial_in(up, UART_LSR); 215 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE)) 216 tx_complete = true; 217 else 218 tx_complete = false; 219 usleep_range(1000, 1100); 220 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000); 221 222 serial8250_do_shutdown(port); 223} 224 225static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, 226 int idx, unsigned int offset, 227 struct uart_8250_port *port) 228{ 229 const struct exar8250_board *board = priv->board; 230 unsigned int bar = 0; 231 unsigned char status; 232 233 port->port.iotype = UPIO_MEM; 234 port->port.mapbase = pci_resource_start(pcidev, bar) + offset; 235 port->port.membase = priv->virt + offset; 236 port->port.regshift = board->reg_shift; 237 238 /* 239 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled 240 * with when DLAB is set which will cause the device to incorrectly match 241 * and assign port type to PORT_16650. The EFR for this UART is found 242 * at offset 0x09. Instead check the Deice ID (DVID) register 243 * for a 2, 4 or 8 port UART. 244 */ 245 status = readb(port->port.membase + UART_EXAR_DVID); 246 if (status == 0x82 || status == 0x84 || status == 0x88) { 247 port->port.type = PORT_XR17V35X; 248 249 port->port.get_divisor = xr17v35x_get_divisor; 250 port->port.set_divisor = xr17v35x_set_divisor; 251 252 port->port.startup = xr17v35x_startup; 253 } else { 254 port->port.type = PORT_XR17D15X; 255 } 256 257 port->port.pm = exar_pm; 258 port->port.shutdown = exar_shutdown; 259 260 return 0; 261} 262 263static int 264pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, 265 struct uart_8250_port *port, int idx) 266{ 267 unsigned int offset = idx * 0x200; 268 unsigned int baud = 1843200; 269 u8 __iomem *p; 270 int err; 271 272 port->port.uartclk = baud * 16; 273 274 err = default_setup(priv, pcidev, idx, offset, port); 275 if (err) 276 return err; 277 278 p = port->port.membase; 279 280 writeb(0x00, p + UART_EXAR_8XMODE); 281 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 282 writeb(32, p + UART_EXAR_TXTRG); 283 writeb(32, p + UART_EXAR_RXTRG); 284 285 /* 286 * Setup Multipurpose Input/Output pins. 287 */ 288 if (idx == 0) { 289 switch (pcidev->device) { 290 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 291 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 292 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 293 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 294 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 295 break; 296 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 297 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 298 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 299 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 300 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 301 break; 302 } 303 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 304 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 305 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 306 } 307 308 return 0; 309} 310 311static int 312pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, 313 struct uart_8250_port *port, int idx) 314{ 315 unsigned int offset = idx * 0x200; 316 unsigned int baud = 1843200; 317 318 port->port.uartclk = baud * 16; 319 return default_setup(priv, pcidev, idx, offset, port); 320} 321 322static int 323pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, 324 struct uart_8250_port *port, int idx) 325{ 326 unsigned int offset = idx * 0x200; 327 unsigned int baud = 921600; 328 329 port->port.uartclk = baud * 16; 330 return default_setup(priv, pcidev, idx, offset, port); 331} 332 333static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) 334{ 335 /* 336 * The Commtech adapters required the MPIOs to be driven low. The Exar 337 * devices will export them as GPIOs, so we pre-configure them safely 338 * as inputs. 339 */ 340 341 u8 dir = 0x00; 342 343 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && 344 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { 345 // Configure GPIO as inputs for Commtech adapters 346 dir = 0xff; 347 } else { 348 // Configure GPIO as outputs for SeaLevel adapters 349 dir = 0x00; 350 } 351 352 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 353 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 354 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 355 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 356 writeb(dir, p + UART_EXAR_MPIOSEL_7_0); 357 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 358 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 359 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 360 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 361 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 362 writeb(dir, p + UART_EXAR_MPIOSEL_15_8); 363 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 364} 365 366static void * 367__xr17v35x_register_gpio(struct pci_dev *pcidev, 368 const struct property_entry *properties) 369{ 370 struct platform_device *pdev; 371 372 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); 373 if (!pdev) 374 return NULL; 375 376 pdev->dev.parent = &pcidev->dev; 377 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); 378 379 if (platform_device_add_properties(pdev, properties) < 0 || 380 platform_device_add(pdev) < 0) { 381 platform_device_put(pdev); 382 return NULL; 383 } 384 385 return pdev; 386} 387 388static const struct property_entry exar_gpio_properties[] = { 389 PROPERTY_ENTRY_U32("exar,first-pin", 0), 390 PROPERTY_ENTRY_U32("ngpios", 16), 391 { } 392}; 393 394static int xr17v35x_register_gpio(struct pci_dev *pcidev, 395 struct uart_8250_port *port) 396{ 397 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) 398 port->port.private_data = 399 __xr17v35x_register_gpio(pcidev, exar_gpio_properties); 400 401 return 0; 402} 403 404static int generic_rs485_config(struct uart_port *port, 405 struct serial_rs485 *rs485) 406{ 407 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 408 u8 __iomem *p = port->membase; 409 u8 value; 410 411 value = readb(p + UART_EXAR_FCTR); 412 if (is_rs485) 413 value |= UART_FCTR_EXAR_485; 414 else 415 value &= ~UART_FCTR_EXAR_485; 416 417 writeb(value, p + UART_EXAR_FCTR); 418 419 if (is_rs485) 420 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); 421 422 port->rs485 = *rs485; 423 424 return 0; 425} 426 427static const struct serial_rs485 generic_rs485_supported = { 428 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 429}; 430 431static const struct exar8250_platform exar8250_default_platform = { 432 .register_gpio = xr17v35x_register_gpio, 433 .rs485_config = generic_rs485_config, 434 .rs485_supported = &generic_rs485_supported, 435}; 436 437static int iot2040_rs485_config(struct uart_port *port, 438 struct serial_rs485 *rs485) 439{ 440 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 441 u8 __iomem *p = port->membase; 442 u8 mask = IOT2040_UART1_MASK; 443 u8 mode, value; 444 445 if (is_rs485) { 446 if (rs485->flags & SER_RS485_RX_DURING_TX) 447 mode = IOT2040_UART_MODE_RS422; 448 else 449 mode = IOT2040_UART_MODE_RS485; 450 451 if (rs485->flags & SER_RS485_TERMINATE_BUS) 452 mode |= IOT2040_UART_TERMINATE_BUS; 453 } else { 454 mode = IOT2040_UART_MODE_RS232; 455 } 456 457 if (port->line == 3) { 458 mask <<= IOT2040_UART2_SHIFT; 459 mode <<= IOT2040_UART2_SHIFT; 460 } 461 462 value = readb(p + UART_EXAR_MPIOLVL_7_0); 463 value &= ~mask; 464 value |= mode; 465 writeb(value, p + UART_EXAR_MPIOLVL_7_0); 466 467 return generic_rs485_config(port, rs485); 468} 469 470static const struct serial_rs485 iot2040_rs485_supported = { 471 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 472 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS, 473}; 474 475static const struct property_entry iot2040_gpio_properties[] = { 476 PROPERTY_ENTRY_U32("exar,first-pin", 10), 477 PROPERTY_ENTRY_U32("ngpios", 1), 478 { } 479}; 480 481static int iot2040_register_gpio(struct pci_dev *pcidev, 482 struct uart_8250_port *port) 483{ 484 u8 __iomem *p = port->port.membase; 485 486 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); 487 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); 488 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); 489 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); 490 491 port->port.private_data = 492 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties); 493 494 return 0; 495} 496 497static const struct exar8250_platform iot2040_platform = { 498 .rs485_config = iot2040_rs485_config, 499 .rs485_supported = &iot2040_rs485_supported, 500 .register_gpio = iot2040_register_gpio, 501}; 502 503/* 504 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device, 505 * IOT2020 doesn't have. Therefore it is sufficient to match on the common 506 * board name after the device was found. 507 */ 508static const struct dmi_system_id exar_platforms[] = { 509 { 510 .matches = { 511 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 512 }, 513 .driver_data = (void *)&iot2040_platform, 514 }, 515 {} 516}; 517 518static int 519pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, 520 struct uart_8250_port *port, int idx) 521{ 522 const struct exar8250_platform *platform; 523 const struct dmi_system_id *dmi_match; 524 unsigned int offset = idx * 0x400; 525 unsigned int baud = 7812500; 526 u8 __iomem *p; 527 int ret; 528 529 dmi_match = dmi_first_match(exar_platforms); 530 if (dmi_match) 531 platform = dmi_match->driver_data; 532 else 533 platform = &exar8250_default_platform; 534 535 port->port.uartclk = baud * 16; 536 port->port.rs485_config = platform->rs485_config; 537 port->port.rs485_supported = platform->rs485_supported; 538 539 /* 540 * Setup the UART clock for the devices on expansion slot to 541 * half the clock speed of the main chip (which is 125MHz) 542 */ 543 if (idx >= 8) 544 port->port.uartclk /= 2; 545 546 ret = default_setup(priv, pcidev, idx, offset, port); 547 if (ret) 548 return ret; 549 550 p = port->port.membase; 551 552 writeb(0x00, p + UART_EXAR_8XMODE); 553 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 554 writeb(128, p + UART_EXAR_TXTRG); 555 writeb(128, p + UART_EXAR_RXTRG); 556 557 if (idx == 0) { 558 /* Setup Multipurpose Input/Output pins. */ 559 setup_gpio(pcidev, p); 560 561 ret = platform->register_gpio(pcidev, port); 562 } 563 564 return ret; 565} 566 567static void pci_xr17v35x_exit(struct pci_dev *pcidev) 568{ 569 struct exar8250 *priv = pci_get_drvdata(pcidev); 570 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); 571 struct platform_device *pdev = port->port.private_data; 572 573 platform_device_unregister(pdev); 574 port->port.private_data = NULL; 575} 576 577static inline void exar_misc_clear(struct exar8250 *priv) 578{ 579 /* Clear all PCI interrupts by reading INT0. No effect on IIR */ 580 readb(priv->virt + UART_EXAR_INT0); 581 582 /* Clear INT0 for Expansion Interface slave ports, too */ 583 if (priv->board->num_ports > 8) 584 readb(priv->virt + 0x2000 + UART_EXAR_INT0); 585} 586 587/* 588 * These Exar UARTs have an extra interrupt indicator that could fire for a 589 * few interrupts that are not presented/cleared through IIR. One of which is 590 * a wakeup interrupt when coming out of sleep. These interrupts are only 591 * cleared by reading global INT0 or INT1 registers as interrupts are 592 * associated with channel 0. The INT[3:0] registers _are_ accessible from each 593 * channel's address space, but for the sake of bus efficiency we register a 594 * dedicated handler at the PCI device level to handle them. 595 */ 596static irqreturn_t exar_misc_handler(int irq, void *data) 597{ 598 exar_misc_clear(data); 599 600 return IRQ_HANDLED; 601} 602 603static int 604exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 605{ 606 unsigned int nr_ports, i, bar = 0, maxnr; 607 struct exar8250_board *board; 608 struct uart_8250_port uart; 609 struct exar8250 *priv; 610 int rc; 611 612 board = (struct exar8250_board *)ent->driver_data; 613 if (!board) 614 return -EINVAL; 615 616 rc = pcim_enable_device(pcidev); 617 if (rc) 618 return rc; 619 620 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 621 622 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) 623 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); 624 else if (board->num_ports) 625 nr_ports = board->num_ports; 626 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL) 627 nr_ports = pcidev->device & 0xff; 628 else 629 nr_ports = pcidev->device & 0x0f; 630 631 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 632 if (!priv) 633 return -ENOMEM; 634 635 priv->board = board; 636 priv->virt = pcim_iomap(pcidev, bar, 0); 637 if (!priv->virt) 638 return -ENOMEM; 639 640 pci_set_master(pcidev); 641 642 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); 643 if (rc < 0) 644 return rc; 645 646 memset(&uart, 0, sizeof(uart)); 647 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT; 648 uart.port.irq = pci_irq_vector(pcidev, 0); 649 uart.port.dev = &pcidev->dev; 650 651 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, 652 IRQF_SHARED, "exar_uart", priv); 653 if (rc) 654 return rc; 655 656 /* Clear interrupts */ 657 exar_misc_clear(priv); 658 659 for (i = 0; i < nr_ports && i < maxnr; i++) { 660 rc = board->setup(priv, pcidev, &uart, i); 661 if (rc) { 662 dev_err(&pcidev->dev, "Failed to setup port %u\n", i); 663 break; 664 } 665 666 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 667 uart.port.iobase, uart.port.irq, uart.port.iotype); 668 669 priv->line[i] = serial8250_register_8250_port(&uart); 670 if (priv->line[i] < 0) { 671 dev_err(&pcidev->dev, 672 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 673 uart.port.iobase, uart.port.irq, 674 uart.port.iotype, priv->line[i]); 675 break; 676 } 677 } 678 priv->nr = i; 679 pci_set_drvdata(pcidev, priv); 680 return 0; 681} 682 683static void exar_pci_remove(struct pci_dev *pcidev) 684{ 685 struct exar8250 *priv = pci_get_drvdata(pcidev); 686 unsigned int i; 687 688 for (i = 0; i < priv->nr; i++) 689 serial8250_unregister_port(priv->line[i]); 690 691 if (priv->board->exit) 692 priv->board->exit(pcidev); 693} 694 695static int __maybe_unused exar_suspend(struct device *dev) 696{ 697 struct pci_dev *pcidev = to_pci_dev(dev); 698 struct exar8250 *priv = pci_get_drvdata(pcidev); 699 unsigned int i; 700 701 for (i = 0; i < priv->nr; i++) 702 if (priv->line[i] >= 0) 703 serial8250_suspend_port(priv->line[i]); 704 705 /* Ensure that every init quirk is properly torn down */ 706 if (priv->board->exit) 707 priv->board->exit(pcidev); 708 709 return 0; 710} 711 712static int __maybe_unused exar_resume(struct device *dev) 713{ 714 struct exar8250 *priv = dev_get_drvdata(dev); 715 unsigned int i; 716 717 exar_misc_clear(priv); 718 719 for (i = 0; i < priv->nr; i++) 720 if (priv->line[i] >= 0) 721 serial8250_resume_port(priv->line[i]); 722 723 return 0; 724} 725 726static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); 727 728static const struct exar8250_board pbn_fastcom335_2 = { 729 .num_ports = 2, 730 .setup = pci_fastcom335_setup, 731}; 732 733static const struct exar8250_board pbn_fastcom335_4 = { 734 .num_ports = 4, 735 .setup = pci_fastcom335_setup, 736}; 737 738static const struct exar8250_board pbn_fastcom335_8 = { 739 .num_ports = 8, 740 .setup = pci_fastcom335_setup, 741}; 742 743static const struct exar8250_board pbn_connect = { 744 .setup = pci_connect_tech_setup, 745}; 746 747static const struct exar8250_board pbn_exar_ibm_saturn = { 748 .num_ports = 1, 749 .setup = pci_xr17c154_setup, 750}; 751 752static const struct exar8250_board pbn_exar_XR17C15x = { 753 .setup = pci_xr17c154_setup, 754}; 755 756static const struct exar8250_board pbn_exar_XR17V35x = { 757 .setup = pci_xr17v35x_setup, 758 .exit = pci_xr17v35x_exit, 759}; 760 761static const struct exar8250_board pbn_fastcom35x_2 = { 762 .num_ports = 2, 763 .setup = pci_xr17v35x_setup, 764 .exit = pci_xr17v35x_exit, 765}; 766 767static const struct exar8250_board pbn_fastcom35x_4 = { 768 .num_ports = 4, 769 .setup = pci_xr17v35x_setup, 770 .exit = pci_xr17v35x_exit, 771}; 772 773static const struct exar8250_board pbn_fastcom35x_8 = { 774 .num_ports = 8, 775 .setup = pci_xr17v35x_setup, 776 .exit = pci_xr17v35x_exit, 777}; 778 779static const struct exar8250_board pbn_exar_XR17V4358 = { 780 .num_ports = 12, 781 .setup = pci_xr17v35x_setup, 782 .exit = pci_xr17v35x_exit, 783}; 784 785static const struct exar8250_board pbn_exar_XR17V8358 = { 786 .num_ports = 16, 787 .setup = pci_xr17v35x_setup, 788 .exit = pci_xr17v35x_exit, 789}; 790 791#define CONNECT_DEVICE(devid, sdevid, bd) { \ 792 PCI_DEVICE_SUB( \ 793 PCI_VENDOR_ID_EXAR, \ 794 PCI_DEVICE_ID_EXAR_##devid, \ 795 PCI_SUBVENDOR_ID_CONNECT_TECH, \ 796 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ 797 (kernel_ulong_t)&bd \ 798 } 799 800#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } 801 802#define IBM_DEVICE(devid, sdevid, bd) { \ 803 PCI_DEVICE_SUB( \ 804 PCI_VENDOR_ID_EXAR, \ 805 PCI_DEVICE_ID_EXAR_##devid, \ 806 PCI_VENDOR_ID_IBM, \ 807 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ 808 (kernel_ulong_t)&bd \ 809 } 810 811#define USR_DEVICE(devid, sdevid, bd) { \ 812 PCI_DEVICE_SUB( \ 813 PCI_VENDOR_ID_USR, \ 814 PCI_DEVICE_ID_EXAR_##devid, \ 815 PCI_VENDOR_ID_EXAR, \ 816 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \ 817 (kernel_ulong_t)&bd \ 818 } 819 820static const struct pci_device_id exar_pci_tbl[] = { 821 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x), 822 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x), 823 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x), 824 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x), 825 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x), 826 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), 827 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), 828 829 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), 830 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), 831 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), 832 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), 833 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), 834 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), 835 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), 836 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), 837 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), 838 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), 839 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), 840 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 841 842 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 843 844 /* USRobotics USR298x-OEM PCI Modems */ 845 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x), 846 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x), 847 848 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 849 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), 850 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), 851 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), 852 853 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ 854 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), 855 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), 856 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), 857 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), 858 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), 859 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2), 860 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4), 861 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8), 862 863 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), 864 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), 865 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), 866 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), 867 868 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x), 869 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x), 870 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x), 871 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x), 872 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x), 873 { 0, } 874}; 875MODULE_DEVICE_TABLE(pci, exar_pci_tbl); 876 877static struct pci_driver exar_pci_driver = { 878 .name = "exar_serial", 879 .probe = exar_pci_probe, 880 .remove = exar_pci_remove, 881 .driver = { 882 .pm = &exar_pci_pm, 883 }, 884 .id_table = exar_pci_tbl, 885}; 886module_pci_driver(exar_pci_driver); 887 888MODULE_LICENSE("GPL"); 889MODULE_DESCRIPTION("Exar Serial Driver"); 890MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 891