1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12#include <linux/delay.h> 13#include <linux/device.h> 14#include <linux/io.h> 15#include <linux/module.h> 16#include <linux/serial_8250.h> 17#include <linux/serial_reg.h> 18#include <linux/of.h> 19#include <linux/of_irq.h> 20#include <linux/of_platform.h> 21#include <linux/platform_device.h> 22#include <linux/workqueue.h> 23#include <linux/notifier.h> 24#include <linux/slab.h> 25#include <linux/acpi.h> 26#include <linux/clk.h> 27#include <linux/reset.h> 28#include <linux/pm_runtime.h> 29 30#include <asm/byteorder.h> 31 32#include "8250_dwlib.h" 33 34/* Offsets for the DesignWare specific registers */ 35#define DW_UART_USR 0x1f /* UART Status Register */ 36 37/* DesignWare specific register fields */ 38#define DW_UART_MCR_SIRE BIT(6) 39 40struct dw8250_data { 41 struct dw8250_port_data data; 42 43 u8 usr_reg; 44 int msr_mask_on; 45 int msr_mask_off; 46 struct clk *clk; 47 struct clk *pclk; 48 struct notifier_block clk_notifier; 49 struct work_struct clk_work; 50 struct reset_control *rst; 51 52 unsigned int skip_autocfg:1; 53 unsigned int uart_16550_compatible:1; 54}; 55 56static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 57{ 58 return container_of(data, struct dw8250_data, data); 59} 60 61static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb) 62{ 63 return container_of(nb, struct dw8250_data, clk_notifier); 64} 65 66static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work) 67{ 68 return container_of(work, struct dw8250_data, clk_work); 69} 70 71static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 72{ 73 struct dw8250_data *d = to_dw8250_data(p->private_data); 74 75 /* Override any modem control signals if needed */ 76 if (offset == UART_MSR) { 77 value |= d->msr_mask_on; 78 value &= ~d->msr_mask_off; 79 } 80 81 return value; 82} 83 84static void dw8250_force_idle(struct uart_port *p) 85{ 86 struct uart_8250_port *up = up_to_u8250p(p); 87 88 serial8250_clear_and_reinit_fifos(up); 89 (void)p->serial_in(p, UART_RX); 90} 91 92static void dw8250_check_lcr(struct uart_port *p, int value) 93{ 94 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 95 int tries = 1000; 96 97 /* Make sure LCR write wasn't ignored */ 98 while (tries--) { 99 unsigned int lcr = p->serial_in(p, UART_LCR); 100 101 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 102 return; 103 104 dw8250_force_idle(p); 105 106#ifdef CONFIG_64BIT 107 if (p->type == PORT_OCTEON) 108 __raw_writeq(value & 0xff, offset); 109 else 110#endif 111 if (p->iotype == UPIO_MEM32) 112 writel(value, offset); 113 else if (p->iotype == UPIO_MEM32BE) 114 iowrite32be(value, offset); 115 else 116 writeb(value, offset); 117 } 118 /* 119 * FIXME: this deadlocks if port->lock is already held 120 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 121 */ 122} 123 124/* Returns once the transmitter is empty or we run out of retries */ 125static void dw8250_tx_wait_empty(struct uart_port *p) 126{ 127 struct uart_8250_port *up = up_to_u8250p(p); 128 unsigned int tries = 20000; 129 unsigned int delay_threshold = tries - 1000; 130 unsigned int lsr; 131 132 while (tries--) { 133 lsr = readb (p->membase + (UART_LSR << p->regshift)); 134 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 135 136 if (lsr & UART_LSR_TEMT) 137 break; 138 139 /* The device is first given a chance to empty without delay, 140 * to avoid slowdowns at high bitrates. If after 1000 tries 141 * the buffer has still not emptied, allow more time for low- 142 * speed links. */ 143 if (tries < delay_threshold) 144 udelay (1); 145 } 146} 147 148static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 149{ 150 struct dw8250_data *d = to_dw8250_data(p->private_data); 151 152 /* Allow the TX to drain before we reconfigure */ 153 if (offset == UART_LCR) 154 dw8250_tx_wait_empty(p); 155 156 writeb(value, p->membase + (offset << p->regshift)); 157 158 if (offset == UART_LCR && !d->uart_16550_compatible) 159 dw8250_check_lcr(p, value); 160} 161 162 163static void dw8250_serial_out(struct uart_port *p, int offset, int value) 164{ 165 struct dw8250_data *d = to_dw8250_data(p->private_data); 166 167 writeb(value, p->membase + (offset << p->regshift)); 168 169 if (offset == UART_LCR && !d->uart_16550_compatible) 170 dw8250_check_lcr(p, value); 171} 172 173static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 174{ 175 unsigned int value = readb(p->membase + (offset << p->regshift)); 176 177 return dw8250_modify_msr(p, offset, value); 178} 179 180#ifdef CONFIG_64BIT 181static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 182{ 183 unsigned int value; 184 185 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 186 187 return dw8250_modify_msr(p, offset, value); 188} 189 190static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 191{ 192 struct dw8250_data *d = to_dw8250_data(p->private_data); 193 194 value &= 0xff; 195 __raw_writeq(value, p->membase + (offset << p->regshift)); 196 /* Read back to ensure register write ordering. */ 197 __raw_readq(p->membase + (UART_LCR << p->regshift)); 198 199 if (offset == UART_LCR && !d->uart_16550_compatible) 200 dw8250_check_lcr(p, value); 201} 202#endif /* CONFIG_64BIT */ 203 204static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 205{ 206 struct dw8250_data *d = to_dw8250_data(p->private_data); 207 208 writel(value, p->membase + (offset << p->regshift)); 209 210 if (offset == UART_LCR && !d->uart_16550_compatible) 211 dw8250_check_lcr(p, value); 212} 213 214static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 215{ 216 unsigned int value = readl(p->membase + (offset << p->regshift)); 217 218 return dw8250_modify_msr(p, offset, value); 219} 220 221static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 222{ 223 struct dw8250_data *d = to_dw8250_data(p->private_data); 224 225 iowrite32be(value, p->membase + (offset << p->regshift)); 226 227 if (offset == UART_LCR && !d->uart_16550_compatible) 228 dw8250_check_lcr(p, value); 229} 230 231static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 232{ 233 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 234 235 return dw8250_modify_msr(p, offset, value); 236} 237 238 239static int dw8250_handle_irq(struct uart_port *p) 240{ 241 struct uart_8250_port *up = up_to_u8250p(p); 242 struct dw8250_data *d = to_dw8250_data(p->private_data); 243 unsigned int iir = p->serial_in(p, UART_IIR); 244 unsigned int status; 245 unsigned long flags; 246 247 /* 248 * There are ways to get Designware-based UARTs into a state where 249 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 250 * data available. If we see such a case then we'll do a bogus 251 * read. If we don't do this then the "RX TIMEOUT" interrupt will 252 * fire forever. 253 * 254 * This problem has only been observed so far when not in DMA mode 255 * so we limit the workaround only to non-DMA mode. 256 */ 257 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 258 spin_lock_irqsave(&p->lock, flags); 259 status = p->serial_in(p, UART_LSR); 260 261 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 262 (void) p->serial_in(p, UART_RX); 263 264 spin_unlock_irqrestore(&p->lock, flags); 265 } 266 267 if (serial8250_handle_irq(p, iir)) 268 return 1; 269 270 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 271 /* Clear the USR */ 272 (void)p->serial_in(p, d->usr_reg); 273 274 return 1; 275 } 276 277 return 0; 278} 279 280static void dw8250_clk_work_cb(struct work_struct *work) 281{ 282 struct dw8250_data *d = work_to_dw8250_data(work); 283 struct uart_8250_port *up; 284 unsigned long rate; 285 286 rate = clk_get_rate(d->clk); 287 if (rate <= 0) 288 return; 289 290 up = serial8250_get_port(d->data.line); 291 292 serial8250_update_uartclk(&up->port, rate); 293} 294 295static int dw8250_clk_notifier_cb(struct notifier_block *nb, 296 unsigned long event, void *data) 297{ 298 struct dw8250_data *d = clk_to_dw8250_data(nb); 299 300 /* 301 * We have no choice but to defer the uartclk update due to two 302 * deadlocks. First one is caused by a recursive mutex lock which 303 * happens when clk_set_rate() is called from dw8250_set_termios(). 304 * Second deadlock is more tricky and is caused by an inverted order of 305 * the clk and tty-port mutexes lock. It happens if clock rate change 306 * is requested asynchronously while set_termios() is executed between 307 * tty-port mutex lock and clk_set_rate() function invocation and 308 * vise-versa. Anyway if we didn't have the reference clock alteration 309 * in the dw8250_set_termios() method we wouldn't have needed this 310 * deferred event handling complication. 311 */ 312 if (event == POST_RATE_CHANGE) { 313 queue_work(system_unbound_wq, &d->clk_work); 314 return NOTIFY_OK; 315 } 316 317 return NOTIFY_DONE; 318} 319 320static void 321dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 322{ 323 if (!state) 324 pm_runtime_get_sync(port->dev); 325 326 serial8250_do_pm(port, state, old); 327 328 if (state) 329 pm_runtime_put_sync_suspend(port->dev); 330} 331 332static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 333 struct ktermios *old) 334{ 335 unsigned long newrate = tty_termios_baud_rate(termios) * 16; 336 struct dw8250_data *d = to_dw8250_data(p->private_data); 337 long rate; 338 int ret; 339 340 clk_disable_unprepare(d->clk); 341 rate = clk_round_rate(d->clk, newrate); 342 if (rate > 0) { 343 /* 344 * Premilinary set the uartclk to the new clock rate so the 345 * clock update event handler caused by the clk_set_rate() 346 * calling wouldn't actually update the UART divisor since 347 * we about to do this anyway. 348 */ 349 swap(p->uartclk, rate); 350 ret = clk_set_rate(d->clk, newrate); 351 if (ret) 352 swap(p->uartclk, rate); 353 } 354 clk_prepare_enable(d->clk); 355 356 p->status &= ~UPSTAT_AUTOCTS; 357 if (termios->c_cflag & CRTSCTS) 358 p->status |= UPSTAT_AUTOCTS; 359 360 serial8250_do_set_termios(p, termios, old); 361} 362 363static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 364{ 365 struct uart_8250_port *up = up_to_u8250p(p); 366 unsigned int mcr = p->serial_in(p, UART_MCR); 367 368 if (up->capabilities & UART_CAP_IRDA) { 369 if (termios->c_line == N_IRDA) 370 mcr |= DW_UART_MCR_SIRE; 371 else 372 mcr &= ~DW_UART_MCR_SIRE; 373 374 p->serial_out(p, UART_MCR, mcr); 375 } 376 serial8250_do_set_ldisc(p, termios); 377} 378 379/* 380 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 381 * channel on platforms that have DMA engines, but don't have any channels 382 * assigned to the UART. 383 * 384 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 385 * core problem is fixed, this function is no longer needed. 386 */ 387static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 388{ 389 return false; 390} 391 392static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 393{ 394 return param == chan->device->dev; 395} 396 397static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 398{ 399 if (p->dev->of_node) { 400 struct device_node *np = p->dev->of_node; 401 int id; 402 403 /* get index of serial line, if found in DT aliases */ 404 id = of_alias_get_id(np, "serial"); 405 if (id >= 0) 406 p->line = id; 407#ifdef CONFIG_64BIT 408 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 409 p->serial_in = dw8250_serial_inq; 410 p->serial_out = dw8250_serial_outq; 411 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 412 p->type = PORT_OCTEON; 413 data->usr_reg = 0x27; 414 data->skip_autocfg = true; 415 } 416#endif 417 if (of_device_is_big_endian(p->dev->of_node)) { 418 p->iotype = UPIO_MEM32BE; 419 p->serial_in = dw8250_serial_in32be; 420 p->serial_out = dw8250_serial_out32be; 421 } 422 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 423 p->serial_out = dw8250_serial_out38x; 424 425 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 426 p->iotype = UPIO_MEM32; 427 p->regshift = 2; 428 p->serial_in = dw8250_serial_in32; 429 data->uart_16550_compatible = true; 430 } 431 432 /* Platforms with iDMA 64-bit */ 433 if (platform_get_resource_byname(to_platform_device(p->dev), 434 IORESOURCE_MEM, "lpss_priv")) { 435 data->data.dma.rx_param = p->dev->parent; 436 data->data.dma.tx_param = p->dev->parent; 437 data->data.dma.fn = dw8250_idma_filter; 438 } 439} 440 441static int dw8250_probe(struct platform_device *pdev) 442{ 443 struct uart_8250_port uart = {}, *up = &uart; 444 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 445 struct uart_port *p = &up->port; 446 struct device *dev = &pdev->dev; 447 struct dw8250_data *data; 448 int irq; 449 int err; 450 u32 val; 451 452 if (!regs) { 453 dev_err(dev, "no registers defined\n"); 454 return -EINVAL; 455 } 456 457 irq = platform_get_irq(pdev, 0); 458 if (irq < 0) 459 return irq; 460 461 spin_lock_init(&p->lock); 462 p->mapbase = regs->start; 463 p->irq = irq; 464 p->handle_irq = dw8250_handle_irq; 465 p->pm = dw8250_do_pm; 466 p->type = PORT_8250; 467 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 468 p->dev = dev; 469 p->iotype = UPIO_MEM; 470 p->serial_in = dw8250_serial_in; 471 p->serial_out = dw8250_serial_out; 472 p->set_ldisc = dw8250_set_ldisc; 473 p->set_termios = dw8250_set_termios; 474 475 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 476 if (!p->membase) 477 return -ENOMEM; 478 479 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 480 if (!data) 481 return -ENOMEM; 482 483 data->data.dma.fn = dw8250_fallback_dma_filter; 484 data->usr_reg = DW_UART_USR; 485 p->private_data = &data->data; 486 487 data->uart_16550_compatible = device_property_read_bool(dev, 488 "snps,uart-16550-compatible"); 489 490 err = device_property_read_u32(dev, "reg-shift", &val); 491 if (!err) 492 p->regshift = val; 493 494 err = device_property_read_u32(dev, "reg-io-width", &val); 495 if (!err && val == 4) { 496 p->iotype = UPIO_MEM32; 497 p->serial_in = dw8250_serial_in32; 498 p->serial_out = dw8250_serial_out32; 499 } 500 501 if (device_property_read_bool(dev, "dcd-override")) { 502 /* Always report DCD as active */ 503 data->msr_mask_on |= UART_MSR_DCD; 504 data->msr_mask_off |= UART_MSR_DDCD; 505 } 506 507 if (device_property_read_bool(dev, "dsr-override")) { 508 /* Always report DSR as active */ 509 data->msr_mask_on |= UART_MSR_DSR; 510 data->msr_mask_off |= UART_MSR_DDSR; 511 } 512 513 if (device_property_read_bool(dev, "cts-override")) { 514 /* Always report CTS as active */ 515 data->msr_mask_on |= UART_MSR_CTS; 516 data->msr_mask_off |= UART_MSR_DCTS; 517 } 518 519 if (device_property_read_bool(dev, "ri-override")) { 520 /* Always report Ring indicator as inactive */ 521 data->msr_mask_off |= UART_MSR_RI; 522 data->msr_mask_off |= UART_MSR_TERI; 523 } 524 525 /* Always ask for fixed clock rate from a property. */ 526 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 527 528 /* If there is separate baudclk, get the rate from it. */ 529 data->clk = devm_clk_get_optional(dev, "baudclk"); 530 if (data->clk == NULL) 531 data->clk = devm_clk_get_optional(dev, NULL); 532 if (IS_ERR(data->clk)) 533 return PTR_ERR(data->clk); 534 535 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); 536 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; 537 538 err = clk_prepare_enable(data->clk); 539 if (err) 540 dev_warn(dev, "could not enable optional baudclk: %d\n", err); 541 542 if (data->clk) 543 p->uartclk = clk_get_rate(data->clk); 544 545 /* If no clock rate is defined, fail. */ 546 if (!p->uartclk) { 547 dev_err(dev, "clock rate not defined\n"); 548 err = -EINVAL; 549 goto err_clk; 550 } 551 552 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); 553 if (IS_ERR(data->pclk)) { 554 err = PTR_ERR(data->pclk); 555 goto err_clk; 556 } 557 558 err = clk_prepare_enable(data->pclk); 559 if (err) { 560 dev_err(dev, "could not enable apb_pclk\n"); 561 goto err_clk; 562 } 563 564 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 565 if (IS_ERR(data->rst)) { 566 err = PTR_ERR(data->rst); 567 goto err_pclk; 568 } 569 reset_control_deassert(data->rst); 570 571 dw8250_quirks(p, data); 572 573 /* If the Busy Functionality is not implemented, don't handle it */ 574 if (data->uart_16550_compatible) 575 p->handle_irq = NULL; 576 577 if (!data->skip_autocfg) 578 dw8250_setup_port(p); 579 580 /* If we have a valid fifosize, try hooking up DMA */ 581 if (p->fifosize) { 582 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 583 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 584 up->dma = &data->data.dma; 585 } 586 587 data->data.line = serial8250_register_8250_port(up); 588 if (data->data.line < 0) { 589 err = data->data.line; 590 goto err_reset; 591 } 592 593 /* 594 * Some platforms may provide a reference clock shared between several 595 * devices. In this case any clock state change must be known to the 596 * UART port at least post factum. 597 */ 598 if (data->clk) { 599 err = clk_notifier_register(data->clk, &data->clk_notifier); 600 if (err) 601 dev_warn(p->dev, "Failed to set the clock notifier\n"); 602 else 603 queue_work(system_unbound_wq, &data->clk_work); 604 } 605 606 platform_set_drvdata(pdev, data); 607 608 pm_runtime_set_active(dev); 609 pm_runtime_enable(dev); 610 611 return 0; 612 613err_reset: 614 reset_control_assert(data->rst); 615 616err_pclk: 617 clk_disable_unprepare(data->pclk); 618 619err_clk: 620 clk_disable_unprepare(data->clk); 621 622 return err; 623} 624 625static int dw8250_remove(struct platform_device *pdev) 626{ 627 struct dw8250_data *data = platform_get_drvdata(pdev); 628 struct device *dev = &pdev->dev; 629 630 pm_runtime_get_sync(dev); 631 632 if (data->clk) { 633 clk_notifier_unregister(data->clk, &data->clk_notifier); 634 635 flush_work(&data->clk_work); 636 } 637 638 serial8250_unregister_port(data->data.line); 639 640 reset_control_assert(data->rst); 641 642 clk_disable_unprepare(data->pclk); 643 644 clk_disable_unprepare(data->clk); 645 646 pm_runtime_disable(dev); 647 pm_runtime_put_noidle(dev); 648 649 return 0; 650} 651 652#ifdef CONFIG_PM_SLEEP 653static int dw8250_suspend(struct device *dev) 654{ 655 struct dw8250_data *data = dev_get_drvdata(dev); 656 657 serial8250_suspend_port(data->data.line); 658 659 return 0; 660} 661 662static int dw8250_resume(struct device *dev) 663{ 664 struct dw8250_data *data = dev_get_drvdata(dev); 665 666 serial8250_resume_port(data->data.line); 667 668 return 0; 669} 670#endif /* CONFIG_PM_SLEEP */ 671 672#ifdef CONFIG_PM 673static int dw8250_runtime_suspend(struct device *dev) 674{ 675 struct dw8250_data *data = dev_get_drvdata(dev); 676 677 clk_disable_unprepare(data->clk); 678 679 clk_disable_unprepare(data->pclk); 680 681 return 0; 682} 683 684static int dw8250_runtime_resume(struct device *dev) 685{ 686 struct dw8250_data *data = dev_get_drvdata(dev); 687 688 clk_prepare_enable(data->pclk); 689 690 clk_prepare_enable(data->clk); 691 692 return 0; 693} 694#endif 695 696static const struct dev_pm_ops dw8250_pm_ops = { 697 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 698 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 699}; 700 701static const struct of_device_id dw8250_of_match[] = { 702 { .compatible = "snps,dw-apb-uart" }, 703 { .compatible = "cavium,octeon-3860-uart" }, 704 { .compatible = "marvell,armada-38x-uart" }, 705 { .compatible = "renesas,rzn1-uart" }, 706 { /* Sentinel */ } 707}; 708MODULE_DEVICE_TABLE(of, dw8250_of_match); 709 710static const struct acpi_device_id dw8250_acpi_match[] = { 711 { "INT33C4", 0 }, 712 { "INT33C5", 0 }, 713 { "INT3434", 0 }, 714 { "INT3435", 0 }, 715 { "80860F0A", 0 }, 716 { "8086228A", 0 }, 717 { "APMC0D08", 0}, 718 { "AMD0020", 0 }, 719 { "AMDI0020", 0 }, 720 { "AMDI0022", 0 }, 721 { "BRCM2032", 0 }, 722 { "HISI0031", 0 }, 723 { }, 724}; 725MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 726 727static struct platform_driver dw8250_platform_driver = { 728 .driver = { 729 .name = "dw-apb-uart", 730 .pm = &dw8250_pm_ops, 731 .of_match_table = dw8250_of_match, 732 .acpi_match_table = dw8250_acpi_match, 733 }, 734 .probe = dw8250_probe, 735 .remove = dw8250_remove, 736}; 737 738module_platform_driver(dw8250_platform_driver); 739 740MODULE_AUTHOR("Jamie Iles"); 741MODULE_LICENSE("GPL"); 742MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 743MODULE_ALIAS("platform:dw-apb-uart"); 744