1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * rocket_int.h --- internal header file for rocket.c 4 * 5 * Written by Theodore Ts'o, Copyright 1997. 6 * Copyright 1997 Comtrol Corporation. 7 * 8 */ 9 10/* 11 * Definition of the types in rcktpt_type 12 */ 13#define ROCKET_TYPE_NORMAL 0 14#define ROCKET_TYPE_MODEM 1 15#define ROCKET_TYPE_MODEMII 2 16#define ROCKET_TYPE_MODEMIII 3 17#define ROCKET_TYPE_PC104 4 18 19#include <linux/mutex.h> 20 21#include <asm/io.h> 22#include <asm/byteorder.h> 23 24typedef unsigned char Byte_t; 25typedef unsigned int ByteIO_t; 26 27typedef unsigned int Word_t; 28typedef unsigned int WordIO_t; 29 30typedef unsigned int DWordIO_t; 31 32/* 33 * Note! Normally the Linux I/O macros already take care of 34 * byte-swapping the I/O instructions. However, all accesses using 35 * sOutDW aren't really 32-bit accesses, but should be handled in byte 36 * order. Hence the use of the cpu_to_le32() macro to byte-swap 37 * things to no-op the byte swapping done by the big-endian outl() 38 * instruction. 39 */ 40 41static inline void sOutB(unsigned short port, unsigned char value) 42{ 43#ifdef ROCKET_DEBUG_IO 44 printk(KERN_DEBUG "sOutB(%x, %x)...\n", port, value); 45#endif 46 outb_p(value, port); 47} 48 49static inline void sOutW(unsigned short port, unsigned short value) 50{ 51#ifdef ROCKET_DEBUG_IO 52 printk(KERN_DEBUG "sOutW(%x, %x)...\n", port, value); 53#endif 54 outw_p(value, port); 55} 56 57static inline void out32(unsigned short port, Byte_t *p) 58{ 59 u32 value = get_unaligned_le32(p); 60#ifdef ROCKET_DEBUG_IO 61 printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value); 62#endif 63 outl_p(value, port); 64} 65 66static inline unsigned char sInB(unsigned short port) 67{ 68 return inb_p(port); 69} 70 71static inline unsigned short sInW(unsigned short port) 72{ 73 return inw_p(port); 74} 75 76/* This is used to move arrays of bytes so byte swapping isn't appropriate. */ 77#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) 78#define sInStrW(port, addr, count) if (count) insw(port, addr, count) 79 80#define CTL_SIZE 8 81#define AIOP_CTL_SIZE 4 82#define CHAN_AIOP_SIZE 8 83#define MAX_PORTS_PER_AIOP 8 84#define MAX_AIOPS_PER_BOARD 4 85#define MAX_PORTS_PER_BOARD 32 86 87/* Bus type ID */ 88#define isISA 0 89#define isPCI 1 90#define isMC 2 91 92/* Controller ID numbers */ 93#define CTLID_NULL -1 /* no controller exists */ 94#define CTLID_0001 0x0001 /* controller release 1 */ 95 96/* AIOP ID numbers, identifies AIOP type implementing channel */ 97#define AIOPID_NULL -1 /* no AIOP or channel exists */ 98#define AIOPID_0001 0x0001 /* AIOP release 1 */ 99 100/************************************************************************ 101 Global Register Offsets - Direct Access - Fixed values 102************************************************************************/ 103 104#define _CMD_REG 0x38 /* Command Register 8 Write */ 105#define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 106#define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 107#define _UNUSED 0x3B /* Unused 8 */ 108#define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 109#define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 110 111/************************************************************************ 112 Channel Register Offsets for 1st channel in AIOP - Direct Access 113************************************************************************/ 114#define _TD0 0x00 /* Transmit Data 16 Write */ 115#define _RD0 0x00 /* Receive Data 16 Read */ 116#define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 117#define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 118#define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 119 120/************************************************************************ 121 Tx Control Register Offsets - Indexed - External - Fixed 122************************************************************************/ 123#define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 124#define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 125#define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 126#define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 127#define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 128#define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 129 130/************************************************************************ 131Memory Controller Register Offsets - Indexed - External - Fixed 132************************************************************************/ 133#define _RX_FIFO 0x000 /* Rx FIFO */ 134#define _TX_FIFO 0x800 /* Tx FIFO */ 135#define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 136#define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 137#define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 138#define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 139#define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 140#define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 141 142#define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 143#define TXFIFO_SIZE 255 /* size of Tx FIFO */ 144#define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 145 146/************************************************************************ 147Tx Priority Buffer - Indexed - External - Fixed 148************************************************************************/ 149#define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 150#define TXP_SIZE 0x20 /* 32 bytes */ 151 152/************************************************************************ 153Channel Register Offsets - Indexed - Internal - Fixed 154************************************************************************/ 155 156#define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 157#define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 158#define _BAUD 0xFF4 /* Baud Rate 16 Write */ 159#define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 160 161#define STMBREAK 0x08 /* BREAK */ 162#define STMFRAME 0x04 /* framing error */ 163#define STMRCVROVR 0x02 /* receiver over run error */ 164#define STMPARITY 0x01 /* parity error */ 165#define STMERROR (STMBREAK | STMFRAME | STMPARITY) 166#define STMBREAKH 0x800 /* BREAK */ 167#define STMFRAMEH 0x400 /* framing error */ 168#define STMRCVROVRH 0x200 /* receiver over run error */ 169#define STMPARITYH 0x100 /* parity error */ 170#define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 171 172#define CTS_ACT 0x20 /* CTS input asserted */ 173#define DSR_ACT 0x10 /* DSR input asserted */ 174#define CD_ACT 0x08 /* CD input asserted */ 175#define TXFIFOMT 0x04 /* Tx FIFO is empty */ 176#define TXSHRMT 0x02 /* Tx shift register is empty */ 177#define RDA 0x01 /* Rx data available */ 178#define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 179 180#define STATMODE 0x8000 /* status mode enable bit */ 181#define RXFOVERFL 0x2000 /* receive FIFO overflow */ 182#define RX2MATCH 0x1000 /* receive compare byte 2 match */ 183#define RX1MATCH 0x0800 /* receive compare byte 1 match */ 184#define RXBREAK 0x0400 /* received BREAK */ 185#define RXFRAME 0x0200 /* received framing error */ 186#define RXPARITY 0x0100 /* received parity error */ 187#define STATERROR (RXBREAK | RXFRAME | RXPARITY) 188 189#define CTSFC_EN 0x80 /* CTS flow control enable bit */ 190#define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 191#define TXINT_EN 0x10 /* transmit interrupt enable */ 192#define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 193#define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 194#define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 195#define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 196 197#define SETBREAK 0x10 /* send break condition (must clear) */ 198#define LOCALLOOP 0x08 /* local loopback set for test */ 199#define SET_DTR 0x04 /* assert DTR */ 200#define SET_RTS 0x02 /* assert RTS */ 201#define TX_ENABLE 0x01 /* enable transmitter */ 202 203#define RTSFC_EN 0x40 /* RTS flow control enable */ 204#define RXPROC_EN 0x20 /* receive processor enable */ 205#define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 206#define TRIG_1 0x08 /* trigger level 1 char */ 207#define TRIG_1_2 0x10 /* trigger level 1/2 */ 208#define TRIG_7_8 0x18 /* trigger level 7/8 */ 209#define TRIG_MASK 0x18 /* trigger level mask */ 210#define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 211#define RXINT_EN 0x02 /* Rx interrupt enable */ 212#define MCINT_EN 0x01 /* modem change interrupt enable */ 213 214#define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 215#define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 216#define SRC_INT 0x08 /* special receive condition interrupt */ 217#define DELTA_CD 0x04 /* CD change interrupt */ 218#define DELTA_CTS 0x02 /* CTS change interrupt */ 219#define DELTA_DSR 0x01 /* DSR change interrupt */ 220 221#define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 222#define IGN2_EN 0x08 /* ignore byte 2 enable */ 223#define IGN1_EN 0x04 /* ignore byte 1 enable */ 224#define COMP2_EN 0x02 /* compare byte 2 enable */ 225#define COMP1_EN 0x01 /* compare byte 1 enable */ 226 227#define RESET_ALL 0x80 /* reset AIOP (all channels) */ 228#define TXOVERIDE 0x40 /* Transmit software off override */ 229#define RESETUART 0x20 /* reset channel's UART */ 230#define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 231#define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 232 233#define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 234#define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 235#define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 236#define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 237 238#define INTR_EN 0x08 /* allow interrupts to host */ 239#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 240 241/************************************************************************** 242 MUDBAC remapped for PCI 243**************************************************************************/ 244 245#define _CFG_INT_PCI 0x40 246#define _PCI_INT_FUNC 0x3A 247 248#define PCI_STROB 0x2000 /* bit 13 of int aiop register */ 249#define INTR_EN_PCI 0x0010 /* allow interrupts to host */ 250 251/* 252 * Definitions for Universal PCI board registers 253 */ 254#define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */ 255#define _PCI_9030_GPIO_CTRL 0x54 256#define PCI_INT_CTRL_AIOP 0x0001 257#define PCI_GPIO_CTRL_8PORT 0x4000 258#define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */ 259 260#define CHAN3_EN 0x08 /* enable AIOP 3 */ 261#define CHAN2_EN 0x04 /* enable AIOP 2 */ 262#define CHAN1_EN 0x02 /* enable AIOP 1 */ 263#define CHAN0_EN 0x01 /* enable AIOP 0 */ 264#define FREQ_DIS 0x00 265#define FREQ_274HZ 0x60 266#define FREQ_137HZ 0x50 267#define FREQ_69HZ 0x40 268#define FREQ_34HZ 0x30 269#define FREQ_17HZ 0x20 270#define FREQ_9HZ 0x10 271#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 272 273#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 274 275#define RDATASIZE 72 276#define RREGDATASIZE 52 277 278/* 279 * AIOP interrupt bits for ISA/PCI boards and UPCI boards. 280 */ 281#define AIOP_INTR_BIT_0 0x0001 282#define AIOP_INTR_BIT_1 0x0002 283#define AIOP_INTR_BIT_2 0x0004 284#define AIOP_INTR_BIT_3 0x0008 285 286#define AIOP_INTR_BITS ( \ 287 AIOP_INTR_BIT_0 \ 288 | AIOP_INTR_BIT_1 \ 289 | AIOP_INTR_BIT_2 \ 290 | AIOP_INTR_BIT_3) 291 292#define UPCI_AIOP_INTR_BIT_0 0x0004 293#define UPCI_AIOP_INTR_BIT_1 0x0020 294#define UPCI_AIOP_INTR_BIT_2 0x0100 295#define UPCI_AIOP_INTR_BIT_3 0x0800 296 297#define UPCI_AIOP_INTR_BITS ( \ 298 UPCI_AIOP_INTR_BIT_0 \ 299 | UPCI_AIOP_INTR_BIT_1 \ 300 | UPCI_AIOP_INTR_BIT_2 \ 301 | UPCI_AIOP_INTR_BIT_3) 302 303/* Controller level information structure */ 304typedef struct { 305 int CtlID; 306 int CtlNum; 307 int BusType; 308 int boardType; 309 int isUPCI; 310 WordIO_t PCIIO; 311 WordIO_t PCIIO2; 312 ByteIO_t MBaseIO; 313 ByteIO_t MReg1IO; 314 ByteIO_t MReg2IO; 315 ByteIO_t MReg3IO; 316 Byte_t MReg2; 317 Byte_t MReg3; 318 int NumAiop; 319 int AltChanRingIndicator; 320 ByteIO_t UPCIRingInd; 321 WordIO_t AiopIO[AIOP_CTL_SIZE]; 322 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; 323 int AiopID[AIOP_CTL_SIZE]; 324 int AiopNumChan[AIOP_CTL_SIZE]; 325 Word_t *AiopIntrBits; 326} CONTROLLER_T; 327 328typedef CONTROLLER_T CONTROLLER_t; 329 330/* Channel level information structure */ 331typedef struct { 332 CONTROLLER_T *CtlP; 333 int AiopNum; 334 int ChanID; 335 int ChanNum; 336 int rtsToggle; 337 338 ByteIO_t Cmd; 339 ByteIO_t IntChan; 340 ByteIO_t IntMask; 341 DWordIO_t IndexAddr; 342 WordIO_t IndexData; 343 344 WordIO_t TxRxData; 345 WordIO_t ChanStat; 346 WordIO_t TxRxCount; 347 ByteIO_t IntID; 348 349 Word_t TxFIFO; 350 Word_t TxFIFOPtrs; 351 Word_t RxFIFO; 352 Word_t RxFIFOPtrs; 353 Word_t TxPrioCnt; 354 Word_t TxPrioPtr; 355 Word_t TxPrioBuf; 356 357 Byte_t R[RREGDATASIZE]; 358 359 Byte_t BaudDiv[4]; 360 Byte_t TxControl[4]; 361 Byte_t RxControl[4]; 362 Byte_t TxEnables[4]; 363 Byte_t TxCompare[4]; 364 Byte_t TxReplace1[4]; 365 Byte_t TxReplace2[4]; 366} CHANNEL_T; 367 368typedef CHANNEL_T CHANNEL_t; 369typedef CHANNEL_T *CHANPTR_T; 370 371#define InterfaceModeRS232 0x00 372#define InterfaceModeRS422 0x08 373#define InterfaceModeRS485 0x10 374#define InterfaceModeRS232T 0x18 375 376/*************************************************************************** 377Function: sClrBreak 378Purpose: Stop sending a transmit BREAK signal 379Call: sClrBreak(ChP) 380 CHANNEL_T *ChP; Ptr to channel structure 381*/ 382#define sClrBreak(ChP) \ 383do { \ 384 (ChP)->TxControl[3] &= ~SETBREAK; \ 385 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 386} while (0) 387 388/*************************************************************************** 389Function: sClrDTR 390Purpose: Clr the DTR output 391Call: sClrDTR(ChP) 392 CHANNEL_T *ChP; Ptr to channel structure 393*/ 394#define sClrDTR(ChP) \ 395do { \ 396 (ChP)->TxControl[3] &= ~SET_DTR; \ 397 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 398} while (0) 399 400/*************************************************************************** 401Function: sClrRTS 402Purpose: Clr the RTS output 403Call: sClrRTS(ChP) 404 CHANNEL_T *ChP; Ptr to channel structure 405*/ 406#define sClrRTS(ChP) \ 407do { \ 408 if ((ChP)->rtsToggle) break; \ 409 (ChP)->TxControl[3] &= ~SET_RTS; \ 410 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 411} while (0) 412 413/*************************************************************************** 414Function: sClrTxXOFF 415Purpose: Clear any existing transmit software flow control off condition 416Call: sClrTxXOFF(ChP) 417 CHANNEL_T *ChP; Ptr to channel structure 418*/ 419#define sClrTxXOFF(ChP) \ 420do { \ 421 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 422 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ 423} while (0) 424 425/*************************************************************************** 426Function: sCtlNumToCtlPtr 427Purpose: Convert a controller number to controller structure pointer 428Call: sCtlNumToCtlPtr(CtlNum) 429 int CtlNum; Controller number 430Return: CONTROLLER_T *: Ptr to controller structure 431*/ 432#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] 433 434/*************************************************************************** 435Function: sControllerEOI 436Purpose: Strobe the MUDBAC's End Of Interrupt bit. 437Call: sControllerEOI(CtlP) 438 CONTROLLER_T *CtlP; Ptr to controller structure 439*/ 440#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) 441 442/*************************************************************************** 443Function: sPCIControllerEOI 444Purpose: Strobe the PCI End Of Interrupt bit. 445 For the UPCI boards, toggle the AIOP interrupt enable bit 446 (this was taken from the Windows driver). 447Call: sPCIControllerEOI(CtlP) 448 CONTROLLER_T *CtlP; Ptr to controller structure 449*/ 450#define sPCIControllerEOI(CTLP) \ 451do { \ 452 if ((CTLP)->isUPCI) { \ 453 Word_t w = sInW((CTLP)->PCIIO); \ 454 sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \ 455 sOutW((CTLP)->PCIIO, w); \ 456 } \ 457 else { \ 458 sOutW((CTLP)->PCIIO, PCI_STROB); \ 459 } \ 460} while (0) 461 462/*************************************************************************** 463Function: sDisAiop 464Purpose: Disable I/O access to an AIOP 465Call: sDisAiop(CltP) 466 CONTROLLER_T *CtlP; Ptr to controller structure 467 int AiopNum; Number of AIOP on controller 468*/ 469#define sDisAiop(CTLP,AIOPNUM) \ 470do { \ 471 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ 472 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 473} while (0) 474 475/*************************************************************************** 476Function: sDisCTSFlowCtl 477Purpose: Disable output flow control using CTS 478Call: sDisCTSFlowCtl(ChP) 479 CHANNEL_T *ChP; Ptr to channel structure 480*/ 481#define sDisCTSFlowCtl(ChP) \ 482do { \ 483 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 484 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 485} while (0) 486 487/*************************************************************************** 488Function: sDisIXANY 489Purpose: Disable IXANY Software Flow Control 490Call: sDisIXANY(ChP) 491 CHANNEL_T *ChP; Ptr to channel structure 492*/ 493#define sDisIXANY(ChP) \ 494do { \ 495 (ChP)->R[0x0e] = 0x86; \ 496 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \ 497} while (0) 498 499/*************************************************************************** 500Function: DisParity 501Purpose: Disable parity 502Call: sDisParity(ChP) 503 CHANNEL_T *ChP; Ptr to channel structure 504Comments: Function sSetParity() can be used in place of functions sEnParity(), 505 sDisParity(), sSetOddParity(), and sSetEvenParity(). 506*/ 507#define sDisParity(ChP) \ 508do { \ 509 (ChP)->TxControl[2] &= ~PARITY_EN; \ 510 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 511} while (0) 512 513/*************************************************************************** 514Function: sDisRTSToggle 515Purpose: Disable RTS toggle 516Call: sDisRTSToggle(ChP) 517 CHANNEL_T *ChP; Ptr to channel structure 518*/ 519#define sDisRTSToggle(ChP) \ 520do { \ 521 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 522 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 523 (ChP)->rtsToggle = 0; \ 524} while (0) 525 526/*************************************************************************** 527Function: sDisRxFIFO 528Purpose: Disable Rx FIFO 529Call: sDisRxFIFO(ChP) 530 CHANNEL_T *ChP; Ptr to channel structure 531*/ 532#define sDisRxFIFO(ChP) \ 533do { \ 534 (ChP)->R[0x32] = 0x0a; \ 535 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \ 536} while (0) 537 538/*************************************************************************** 539Function: sDisRxStatusMode 540Purpose: Disable the Rx status mode 541Call: sDisRxStatusMode(ChP) 542 CHANNEL_T *ChP; Ptr to channel structure 543Comments: This takes the channel out of the receive status mode. All 544 subsequent reads of receive data using sReadRxWord() will return 545 two data bytes. 546*/ 547#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) 548 549/*************************************************************************** 550Function: sDisTransmit 551Purpose: Disable transmit 552Call: sDisTransmit(ChP) 553 CHANNEL_T *ChP; Ptr to channel structure 554 This disables movement of Tx data from the Tx FIFO into the 1 byte 555 Tx buffer. Therefore there could be up to a 2 byte latency 556 between the time sDisTransmit() is called and the transmit buffer 557 and transmit shift register going completely empty. 558*/ 559#define sDisTransmit(ChP) \ 560do { \ 561 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 562 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 563} while (0) 564 565/*************************************************************************** 566Function: sDisTxSoftFlowCtl 567Purpose: Disable Tx Software Flow Control 568Call: sDisTxSoftFlowCtl(ChP) 569 CHANNEL_T *ChP; Ptr to channel structure 570*/ 571#define sDisTxSoftFlowCtl(ChP) \ 572do { \ 573 (ChP)->R[0x06] = 0x8a; \ 574 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ 575} while (0) 576 577/*************************************************************************** 578Function: sEnAiop 579Purpose: Enable I/O access to an AIOP 580Call: sEnAiop(CltP) 581 CONTROLLER_T *CtlP; Ptr to controller structure 582 int AiopNum; Number of AIOP on controller 583*/ 584#define sEnAiop(CTLP,AIOPNUM) \ 585do { \ 586 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ 587 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 588} while (0) 589 590/*************************************************************************** 591Function: sEnCTSFlowCtl 592Purpose: Enable output flow control using CTS 593Call: sEnCTSFlowCtl(ChP) 594 CHANNEL_T *ChP; Ptr to channel structure 595*/ 596#define sEnCTSFlowCtl(ChP) \ 597do { \ 598 (ChP)->TxControl[2] |= CTSFC_EN; \ 599 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 600} while (0) 601 602/*************************************************************************** 603Function: sEnIXANY 604Purpose: Enable IXANY Software Flow Control 605Call: sEnIXANY(ChP) 606 CHANNEL_T *ChP; Ptr to channel structure 607*/ 608#define sEnIXANY(ChP) \ 609do { \ 610 (ChP)->R[0x0e] = 0x21; \ 611 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \ 612} while (0) 613 614/*************************************************************************** 615Function: EnParity 616Purpose: Enable parity 617Call: sEnParity(ChP) 618 CHANNEL_T *ChP; Ptr to channel structure 619Comments: Function sSetParity() can be used in place of functions sEnParity(), 620 sDisParity(), sSetOddParity(), and sSetEvenParity(). 621 622Warnings: Before enabling parity odd or even parity should be chosen using 623 functions sSetOddParity() or sSetEvenParity(). 624*/ 625#define sEnParity(ChP) \ 626do { \ 627 (ChP)->TxControl[2] |= PARITY_EN; \ 628 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 629} while (0) 630 631/*************************************************************************** 632Function: sEnRTSToggle 633Purpose: Enable RTS toggle 634Call: sEnRTSToggle(ChP) 635 CHANNEL_T *ChP; Ptr to channel structure 636Comments: This function will disable RTS flow control and clear the RTS 637 line to allow operation of RTS toggle. 638*/ 639#define sEnRTSToggle(ChP) \ 640do { \ 641 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 642 out32((ChP)->IndexAddr,(ChP)->RxControl); \ 643 (ChP)->TxControl[2] |= RTSTOG_EN; \ 644 (ChP)->TxControl[3] &= ~SET_RTS; \ 645 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 646 (ChP)->rtsToggle = 1; \ 647} while (0) 648 649/*************************************************************************** 650Function: sEnRxFIFO 651Purpose: Enable Rx FIFO 652Call: sEnRxFIFO(ChP) 653 CHANNEL_T *ChP; Ptr to channel structure 654*/ 655#define sEnRxFIFO(ChP) \ 656do { \ 657 (ChP)->R[0x32] = 0x08; \ 658 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \ 659} while (0) 660 661/*************************************************************************** 662Function: sEnRxProcessor 663Purpose: Enable the receive processor 664Call: sEnRxProcessor(ChP) 665 CHANNEL_T *ChP; Ptr to channel structure 666Comments: This function is used to start the receive processor. When 667 the channel is in the reset state the receive processor is not 668 running. This is done to prevent the receive processor from 669 executing invalid microcode instructions prior to the 670 downloading of the microcode. 671 672Warnings: This function must be called after valid microcode has been 673 downloaded to the AIOP, and it must not be called before the 674 microcode has been downloaded. 675*/ 676#define sEnRxProcessor(ChP) \ 677do { \ 678 (ChP)->RxControl[2] |= RXPROC_EN; \ 679 out32((ChP)->IndexAddr,(ChP)->RxControl); \ 680} while (0) 681 682/*************************************************************************** 683Function: sEnRxStatusMode 684Purpose: Enable the Rx status mode 685Call: sEnRxStatusMode(ChP) 686 CHANNEL_T *ChP; Ptr to channel structure 687Comments: This places the channel in the receive status mode. All subsequent 688 reads of receive data using sReadRxWord() will return a data byte 689 in the low word and a status byte in the high word. 690 691*/ 692#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) 693 694/*************************************************************************** 695Function: sEnTransmit 696Purpose: Enable transmit 697Call: sEnTransmit(ChP) 698 CHANNEL_T *ChP; Ptr to channel structure 699*/ 700#define sEnTransmit(ChP) \ 701do { \ 702 (ChP)->TxControl[3] |= TX_ENABLE; \ 703 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 704} while (0) 705 706/*************************************************************************** 707Function: sEnTxSoftFlowCtl 708Purpose: Enable Tx Software Flow Control 709Call: sEnTxSoftFlowCtl(ChP) 710 CHANNEL_T *ChP; Ptr to channel structure 711*/ 712#define sEnTxSoftFlowCtl(ChP) \ 713do { \ 714 (ChP)->R[0x06] = 0xc5; \ 715 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ 716} while (0) 717 718/*************************************************************************** 719Function: sGetAiopIntStatus 720Purpose: Get the AIOP interrupt status 721Call: sGetAiopIntStatus(CtlP,AiopNum) 722 CONTROLLER_T *CtlP; Ptr to controller structure 723 int AiopNum; AIOP number 724Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 725 represent channels 0 through 7 respectively. If a 726 bit is set that channel is interrupting. 727*/ 728#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) 729 730/*************************************************************************** 731Function: sGetAiopNumChan 732Purpose: Get the number of channels supported by an AIOP 733Call: sGetAiopNumChan(CtlP,AiopNum) 734 CONTROLLER_T *CtlP; Ptr to controller structure 735 int AiopNum; AIOP number 736Return: int: The number of channels supported by the AIOP 737*/ 738#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] 739 740/*************************************************************************** 741Function: sGetChanIntID 742Purpose: Get a channel's interrupt identification byte 743Call: sGetChanIntID(ChP) 744 CHANNEL_T *ChP; Ptr to channel structure 745Return: Byte_t: The channel interrupt ID. Can be any 746 combination of the following flags: 747 RXF_TRIG: Rx FIFO trigger level interrupt 748 TXFIFO_MT: Tx FIFO empty interrupt 749 SRC_INT: Special receive condition interrupt 750 DELTA_CD: CD change interrupt 751 DELTA_CTS: CTS change interrupt 752 DELTA_DSR: DSR change interrupt 753*/ 754#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 755 756/*************************************************************************** 757Function: sGetChanNum 758Purpose: Get the number of a channel within an AIOP 759Call: sGetChanNum(ChP) 760 CHANNEL_T *ChP; Ptr to channel structure 761Return: int: Channel number within AIOP, or NULLCHAN if channel does 762 not exist. 763*/ 764#define sGetChanNum(ChP) (ChP)->ChanNum 765 766/*************************************************************************** 767Function: sGetChanStatus 768Purpose: Get the channel status 769Call: sGetChanStatus(ChP) 770 CHANNEL_T *ChP; Ptr to channel structure 771Return: Word_t: The channel status. Can be any combination of 772 the following flags: 773 LOW BYTE FLAGS 774 CTS_ACT: CTS input asserted 775 DSR_ACT: DSR input asserted 776 CD_ACT: CD input asserted 777 TXFIFOMT: Tx FIFO is empty 778 TXSHRMT: Tx shift register is empty 779 RDA: Rx data available 780 781 HIGH BYTE FLAGS 782 STATMODE: status mode enable bit 783 RXFOVERFL: receive FIFO overflow 784 RX2MATCH: receive compare byte 2 match 785 RX1MATCH: receive compare byte 1 match 786 RXBREAK: received BREAK 787 RXFRAME: received framing error 788 RXPARITY: received parity error 789Warnings: This function will clear the high byte flags in the Channel 790 Status Register. 791*/ 792#define sGetChanStatus(ChP) sInW((ChP)->ChanStat) 793 794/*************************************************************************** 795Function: sGetChanStatusLo 796Purpose: Get the low byte only of the channel status 797Call: sGetChanStatusLo(ChP) 798 CHANNEL_T *ChP; Ptr to channel structure 799Return: Byte_t: The channel status low byte. Can be any combination 800 of the following flags: 801 CTS_ACT: CTS input asserted 802 DSR_ACT: DSR input asserted 803 CD_ACT: CD input asserted 804 TXFIFOMT: Tx FIFO is empty 805 TXSHRMT: Tx shift register is empty 806 RDA: Rx data available 807*/ 808#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) 809 810/********************************************************************** 811 * Get RI status of channel 812 * Defined as a function in rocket.c -aes 813 */ 814#if 0 815#define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \ 816 (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \ 817 (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \ 818 (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \ 819 0)) 820#endif 821 822/*************************************************************************** 823Function: sGetControllerIntStatus 824Purpose: Get the controller interrupt status 825Call: sGetControllerIntStatus(CtlP) 826 CONTROLLER_T *CtlP; Ptr to controller structure 827Return: Byte_t: The controller interrupt status in the lower 4 828 bits. Bits 0 through 3 represent AIOP's 0 829 through 3 respectively. If a bit is set that 830 AIOP is interrupting. Bits 4 through 7 will 831 always be cleared. 832*/ 833#define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) 834 835/*************************************************************************** 836Function: sPCIGetControllerIntStatus 837Purpose: Get the controller interrupt status 838Call: sPCIGetControllerIntStatus(CtlP) 839 CONTROLLER_T *CtlP; Ptr to controller structure 840Return: unsigned char: The controller interrupt status in the lower 4 841 bits and bit 4. Bits 0 through 3 represent AIOP's 0 842 through 3 respectively. Bit 4 is set if the int 843 was generated from periodic. If a bit is set the 844 AIOP is interrupting. 845*/ 846#define sPCIGetControllerIntStatus(CTLP) \ 847 ((CTLP)->isUPCI ? \ 848 (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \ 849 ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS)) 850 851/*************************************************************************** 852 853Function: sGetRxCnt 854Purpose: Get the number of data bytes in the Rx FIFO 855Call: sGetRxCnt(ChP) 856 CHANNEL_T *ChP; Ptr to channel structure 857Return: int: The number of data bytes in the Rx FIFO. 858Comments: Byte read of count register is required to obtain Rx count. 859 860*/ 861#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) 862 863/*************************************************************************** 864Function: sGetTxCnt 865Purpose: Get the number of data bytes in the Tx FIFO 866Call: sGetTxCnt(ChP) 867 CHANNEL_T *ChP; Ptr to channel structure 868Return: Byte_t: The number of data bytes in the Tx FIFO. 869Comments: Byte read of count register is required to obtain Tx count. 870 871*/ 872#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) 873 874/***************************************************************************** 875Function: sGetTxRxDataIO 876Purpose: Get the I/O address of a channel's TxRx Data register 877Call: sGetTxRxDataIO(ChP) 878 CHANNEL_T *ChP; Ptr to channel structure 879Return: WordIO_t: I/O address of a channel's TxRx Data register 880*/ 881#define sGetTxRxDataIO(ChP) (ChP)->TxRxData 882 883/*************************************************************************** 884Function: sInitChanDefaults 885Purpose: Initialize a channel structure to it's default state. 886Call: sInitChanDefaults(ChP) 887 CHANNEL_T *ChP; Ptr to the channel structure 888Comments: This function must be called once for every channel structure 889 that exists before any other SSCI calls can be made. 890 891*/ 892#define sInitChanDefaults(ChP) \ 893do { \ 894 (ChP)->CtlP = NULLCTLPTR; \ 895 (ChP)->AiopNum = NULLAIOP; \ 896 (ChP)->ChanID = AIOPID_NULL; \ 897 (ChP)->ChanNum = NULLCHAN; \ 898} while (0) 899 900/*************************************************************************** 901Function: sResetAiopByNum 902Purpose: Reset the AIOP by number 903Call: sResetAiopByNum(CTLP,AIOPNUM) 904 CONTROLLER_T CTLP; Ptr to controller structure 905 AIOPNUM; AIOP index 906*/ 907#define sResetAiopByNum(CTLP,AIOPNUM) \ 908do { \ 909 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ 910 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ 911} while (0) 912 913/*************************************************************************** 914Function: sSendBreak 915Purpose: Send a transmit BREAK signal 916Call: sSendBreak(ChP) 917 CHANNEL_T *ChP; Ptr to channel structure 918*/ 919#define sSendBreak(ChP) \ 920do { \ 921 (ChP)->TxControl[3] |= SETBREAK; \ 922 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 923} while (0) 924 925/*************************************************************************** 926Function: sSetBaud 927Purpose: Set baud rate 928Call: sSetBaud(ChP,Divisor) 929 CHANNEL_T *ChP; Ptr to channel structure 930 Word_t Divisor; 16 bit baud rate divisor for channel 931*/ 932#define sSetBaud(ChP,DIVISOR) \ 933do { \ 934 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 935 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 936 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \ 937} while (0) 938 939/*************************************************************************** 940Function: sSetData7 941Purpose: Set data bits to 7 942Call: sSetData7(ChP) 943 CHANNEL_T *ChP; Ptr to channel structure 944*/ 945#define sSetData7(ChP) \ 946do { \ 947 (ChP)->TxControl[2] &= ~DATA8BIT; \ 948 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 949} while (0) 950 951/*************************************************************************** 952Function: sSetData8 953Purpose: Set data bits to 8 954Call: sSetData8(ChP) 955 CHANNEL_T *ChP; Ptr to channel structure 956*/ 957#define sSetData8(ChP) \ 958do { \ 959 (ChP)->TxControl[2] |= DATA8BIT; \ 960 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 961} while (0) 962 963/*************************************************************************** 964Function: sSetDTR 965Purpose: Set the DTR output 966Call: sSetDTR(ChP) 967 CHANNEL_T *ChP; Ptr to channel structure 968*/ 969#define sSetDTR(ChP) \ 970do { \ 971 (ChP)->TxControl[3] |= SET_DTR; \ 972 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 973} while (0) 974 975/*************************************************************************** 976Function: sSetEvenParity 977Purpose: Set even parity 978Call: sSetEvenParity(ChP) 979 CHANNEL_T *ChP; Ptr to channel structure 980Comments: Function sSetParity() can be used in place of functions sEnParity(), 981 sDisParity(), sSetOddParity(), and sSetEvenParity(). 982 983Warnings: This function has no effect unless parity is enabled with function 984 sEnParity(). 985*/ 986#define sSetEvenParity(ChP) \ 987do { \ 988 (ChP)->TxControl[2] |= EVEN_PAR; \ 989 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 990} while (0) 991 992/*************************************************************************** 993Function: sSetOddParity 994Purpose: Set odd parity 995Call: sSetOddParity(ChP) 996 CHANNEL_T *ChP; Ptr to channel structure 997Comments: Function sSetParity() can be used in place of functions sEnParity(), 998 sDisParity(), sSetOddParity(), and sSetEvenParity(). 999 1000Warnings: This function has no effect unless parity is enabled with function 1001 sEnParity(). 1002*/ 1003#define sSetOddParity(ChP) \ 1004do { \ 1005 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 1006 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 1007} while (0) 1008 1009/*************************************************************************** 1010Function: sSetRTS 1011Purpose: Set the RTS output 1012Call: sSetRTS(ChP) 1013 CHANNEL_T *ChP; Ptr to channel structure 1014*/ 1015#define sSetRTS(ChP) \ 1016do { \ 1017 if ((ChP)->rtsToggle) break; \ 1018 (ChP)->TxControl[3] |= SET_RTS; \ 1019 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 1020} while (0) 1021 1022/*************************************************************************** 1023Function: sSetRxTrigger 1024Purpose: Set the Rx FIFO trigger level 1025Call: sSetRxProcessor(ChP,Level) 1026 CHANNEL_T *ChP; Ptr to channel structure 1027 Byte_t Level; Number of characters in Rx FIFO at which the 1028 interrupt will be generated. Can be any of the following flags: 1029 1030 TRIG_NO: no trigger 1031 TRIG_1: 1 character in FIFO 1032 TRIG_1_2: FIFO 1/2 full 1033 TRIG_7_8: FIFO 7/8 full 1034Comments: An interrupt will be generated when the trigger level is reached 1035 only if function sEnInterrupt() has been called with flag 1036 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 1037 register will be set whenever the trigger level is reached 1038 regardless of the setting of RXINT_EN. 1039 1040*/ 1041#define sSetRxTrigger(ChP,LEVEL) \ 1042do { \ 1043 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 1044 (ChP)->RxControl[2] |= LEVEL; \ 1045 out32((ChP)->IndexAddr,(ChP)->RxControl); \ 1046} while (0) 1047 1048/*************************************************************************** 1049Function: sSetStop1 1050Purpose: Set stop bits to 1 1051Call: sSetStop1(ChP) 1052 CHANNEL_T *ChP; Ptr to channel structure 1053*/ 1054#define sSetStop1(ChP) \ 1055do { \ 1056 (ChP)->TxControl[2] &= ~STOP2; \ 1057 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 1058} while (0) 1059 1060/*************************************************************************** 1061Function: sSetStop2 1062Purpose: Set stop bits to 2 1063Call: sSetStop2(ChP) 1064 CHANNEL_T *ChP; Ptr to channel structure 1065*/ 1066#define sSetStop2(ChP) \ 1067do { \ 1068 (ChP)->TxControl[2] |= STOP2; \ 1069 out32((ChP)->IndexAddr,(ChP)->TxControl); \ 1070} while (0) 1071 1072/*************************************************************************** 1073Function: sSetTxXOFFChar 1074Purpose: Set the Tx XOFF flow control character 1075Call: sSetTxXOFFChar(ChP,Ch) 1076 CHANNEL_T *ChP; Ptr to channel structure 1077 Byte_t Ch; The value to set the Tx XOFF character to 1078*/ 1079#define sSetTxXOFFChar(ChP,CH) \ 1080do { \ 1081 (ChP)->R[0x07] = (CH); \ 1082 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ 1083} while (0) 1084 1085/*************************************************************************** 1086Function: sSetTxXONChar 1087Purpose: Set the Tx XON flow control character 1088Call: sSetTxXONChar(ChP,Ch) 1089 CHANNEL_T *ChP; Ptr to channel structure 1090 Byte_t Ch; The value to set the Tx XON character to 1091*/ 1092#define sSetTxXONChar(ChP,CH) \ 1093do { \ 1094 (ChP)->R[0x0b] = (CH); \ 1095 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \ 1096} while (0) 1097 1098/*************************************************************************** 1099Function: sStartRxProcessor 1100Purpose: Start a channel's receive processor 1101Call: sStartRxProcessor(ChP) 1102 CHANNEL_T *ChP; Ptr to channel structure 1103Comments: This function is used to start a Rx processor after it was 1104 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 1105 will restart both the Rx processor and software input flow control. 1106 1107*/ 1108#define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0]) 1109 1110/*************************************************************************** 1111Function: sWriteTxByte 1112Purpose: Write a transmit data byte to a channel. 1113 ByteIO_t io: Channel transmit register I/O address. This can 1114 be obtained with sGetTxRxDataIO(). 1115 Byte_t Data; The transmit data byte. 1116Warnings: This function writes the data byte without checking to see if 1117 sMaxTxSize is exceeded in the Tx FIFO. 1118*/ 1119#define sWriteTxByte(IO,DATA) sOutB(IO,DATA) 1120 1121/* 1122 * Begin Linux specific definitions for the Rocketport driver 1123 * 1124 * This code is Copyright Theodore Ts'o, 1995-1997 1125 */ 1126 1127struct r_port { 1128 int magic; 1129 struct tty_port port; 1130 int line; 1131 int flags; /* Don't yet match the ASY_ flags!! */ 1132 unsigned int board:3; 1133 unsigned int aiop:2; 1134 unsigned int chan:3; 1135 CONTROLLER_t *ctlp; 1136 CHANNEL_t channel; 1137 int intmask; 1138 int xmit_fifo_room; /* room in xmit fifo */ 1139 unsigned char *xmit_buf; 1140 int xmit_head; 1141 int xmit_tail; 1142 int xmit_cnt; 1143 int cd_status; 1144 int ignore_status_mask; 1145 int read_status_mask; 1146 int cps; 1147 1148 spinlock_t slock; 1149 struct mutex write_mtx; 1150}; 1151 1152#define RPORT_MAGIC 0x525001 1153 1154#define NUM_BOARDS 8 1155#define MAX_RP_PORTS (32*NUM_BOARDS) 1156 1157/* 1158 * The size of the xmit buffer is 1 page, or 4096 bytes 1159 */ 1160#define XMIT_BUF_SIZE 4096 1161 1162/* number of characters left in xmit buffer before we ask for more */ 1163#define WAKEUP_CHARS 256 1164 1165/* 1166 * Assigned major numbers for the Comtrol Rocketport 1167 */ 1168#define TTY_ROCKET_MAJOR 46 1169#define CUA_ROCKET_MAJOR 47 1170 1171#ifdef PCI_VENDOR_ID_RP 1172#undef PCI_VENDOR_ID_RP 1173#undef PCI_DEVICE_ID_RP8OCTA 1174#undef PCI_DEVICE_ID_RP8INTF 1175#undef PCI_DEVICE_ID_RP16INTF 1176#undef PCI_DEVICE_ID_RP32INTF 1177#undef PCI_DEVICE_ID_URP8OCTA 1178#undef PCI_DEVICE_ID_URP8INTF 1179#undef PCI_DEVICE_ID_URP16INTF 1180#undef PCI_DEVICE_ID_CRP16INTF 1181#undef PCI_DEVICE_ID_URP32INTF 1182#endif 1183 1184/* Comtrol PCI Vendor ID */ 1185#define PCI_VENDOR_ID_RP 0x11fe 1186 1187/* Comtrol Device ID's */ 1188#define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */ 1189#define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */ 1190#define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */ 1191#define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */ 1192#define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */ 1193#define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */ 1194#define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */ 1195#define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */ 1196#define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */ 1197#define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */ 1198#define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */ 1199#define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */ 1200#define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */ 1201#define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */ 1202#define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */ 1203 1204/* Universal PCI boards */ 1205#define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */ 1206#define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */ 1207#define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */ 1208#define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */ 1209#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */ 1210#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */ 1211 1212/* Compact PCI device */ 1213#define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */ 1214 1215