1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _MXSER_H 3#define _MXSER_H 4 5/* 6 * Semi-public control interfaces 7 */ 8 9/* 10 * MOXA ioctls 11 */ 12 13#define MOXA 0x400 14#define MOXA_GETDATACOUNT (MOXA + 23) 15#define MOXA_DIAGNOSE (MOXA + 50) 16#define MOXA_CHKPORTENABLE (MOXA + 60) 17#define MOXA_HighSpeedOn (MOXA + 61) 18#define MOXA_GET_MAJOR (MOXA + 63) 19#define MOXA_GETMSTATUS (MOXA + 65) 20#define MOXA_SET_OP_MODE (MOXA + 66) 21#define MOXA_GET_OP_MODE (MOXA + 67) 22 23#define RS232_MODE 0 24#define RS485_2WIRE_MODE 1 25#define RS422_MODE 2 26#define RS485_4WIRE_MODE 3 27#define OP_MODE_MASK 3 28 29#define MOXA_SDS_RSTICOUNTER (MOXA + 69) 30#define MOXA_ASPP_OQUEUE (MOXA + 70) 31#define MOXA_ASPP_MON (MOXA + 73) 32#define MOXA_ASPP_LSTATUS (MOXA + 74) 33#define MOXA_ASPP_MON_EXT (MOXA + 75) 34#define MOXA_SET_BAUD_METHOD (MOXA + 76) 35 36/* --------------------------------------------------- */ 37 38#define NPPI_NOTIFY_PARITY 0x01 39#define NPPI_NOTIFY_FRAMING 0x02 40#define NPPI_NOTIFY_HW_OVERRUN 0x04 41#define NPPI_NOTIFY_SW_OVERRUN 0x08 42#define NPPI_NOTIFY_BREAK 0x10 43 44#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */ 45#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */ 46#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */ 47#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */ 48 49/* follow just for Moxa Must chip define. */ 50/* */ 51/* when LCR register (offset 0x03) write following value, */ 52/* the Must chip will enter enchance mode. And write value */ 53/* on EFR (offset 0x02) bit 6,7 to change bank. */ 54#define MOXA_MUST_ENTER_ENCHANCE 0xBF 55 56/* when enhance mode enable, access on general bank register */ 57#define MOXA_MUST_GDL_REGISTER 0x07 58#define MOXA_MUST_GDL_MASK 0x7F 59#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 60 61#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 62/* enchance register bank select and enchance mode setting register */ 63/* when LCR register equal to 0xBF */ 64#define MOXA_MUST_EFR_REGISTER 0x02 65/* enchance mode enable */ 66#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 67/* enchance reister bank set 0, 1, 2 */ 68#define MOXA_MUST_EFR_BANK0 0x00 69#define MOXA_MUST_EFR_BANK1 0x40 70#define MOXA_MUST_EFR_BANK2 0x80 71#define MOXA_MUST_EFR_BANK3 0xC0 72#define MOXA_MUST_EFR_BANK_MASK 0xC0 73 74/* set XON1 value register, when LCR=0xBF and change to bank0 */ 75#define MOXA_MUST_XON1_REGISTER 0x04 76 77/* set XON2 value register, when LCR=0xBF and change to bank0 */ 78#define MOXA_MUST_XON2_REGISTER 0x05 79 80/* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 81#define MOXA_MUST_XOFF1_REGISTER 0x06 82 83/* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 84#define MOXA_MUST_XOFF2_REGISTER 0x07 85 86#define MOXA_MUST_RBRTL_REGISTER 0x04 87#define MOXA_MUST_RBRTH_REGISTER 0x05 88#define MOXA_MUST_RBRTI_REGISTER 0x06 89#define MOXA_MUST_THRTL_REGISTER 0x07 90#define MOXA_MUST_ENUM_REGISTER 0x04 91#define MOXA_MUST_HWID_REGISTER 0x05 92#define MOXA_MUST_ECR_REGISTER 0x06 93#define MOXA_MUST_CSR_REGISTER 0x07 94 95/* good data mode enable */ 96#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 97/* only good data put into RxFIFO */ 98#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 99 100/* enable CTS interrupt */ 101#define MOXA_MUST_IER_ECTSI 0x80 102/* enable RTS interrupt */ 103#define MOXA_MUST_IER_ERTSI 0x40 104/* enable Xon/Xoff interrupt */ 105#define MOXA_MUST_IER_XINT 0x20 106/* enable GDA interrupt */ 107#define MOXA_MUST_IER_EGDAI 0x10 108 109#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 110 111/* GDA interrupt pending */ 112#define MOXA_MUST_IIR_GDA 0x1C 113#define MOXA_MUST_IIR_RDA 0x04 114#define MOXA_MUST_IIR_RTO 0x0C 115#define MOXA_MUST_IIR_LSR 0x06 116 117/* received Xon/Xoff or specical interrupt pending */ 118#define MOXA_MUST_IIR_XSC 0x10 119 120/* RTS/CTS change state interrupt pending */ 121#define MOXA_MUST_IIR_RTSCTS 0x20 122#define MOXA_MUST_IIR_MASK 0x3E 123 124#define MOXA_MUST_MCR_XON_FLAG 0x40 125#define MOXA_MUST_MCR_XON_ANY 0x80 126#define MOXA_MUST_MCR_TX_XON 0x08 127 128/* software flow control on chip mask value */ 129#define MOXA_MUST_EFR_SF_MASK 0x0F 130/* send Xon1/Xoff1 */ 131#define MOXA_MUST_EFR_SF_TX1 0x08 132/* send Xon2/Xoff2 */ 133#define MOXA_MUST_EFR_SF_TX2 0x04 134/* send Xon1,Xon2/Xoff1,Xoff2 */ 135#define MOXA_MUST_EFR_SF_TX12 0x0C 136/* don't send Xon/Xoff */ 137#define MOXA_MUST_EFR_SF_TX_NO 0x00 138/* Tx software flow control mask */ 139#define MOXA_MUST_EFR_SF_TX_MASK 0x0C 140/* don't receive Xon/Xoff */ 141#define MOXA_MUST_EFR_SF_RX_NO 0x00 142/* receive Xon1/Xoff1 */ 143#define MOXA_MUST_EFR_SF_RX1 0x02 144/* receive Xon2/Xoff2 */ 145#define MOXA_MUST_EFR_SF_RX2 0x01 146/* receive Xon1,Xon2/Xoff1,Xoff2 */ 147#define MOXA_MUST_EFR_SF_RX12 0x03 148/* Rx software flow control mask */ 149#define MOXA_MUST_EFR_SF_RX_MASK 0x03 150 151#endif 152