1// SPDX-License-Identifier: GPL-2.0 2/* 3 * USB4 specific functionality 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rajmohan Mani <rajmohan.mani@intel.com> 8 */ 9 10#include <linux/delay.h> 11#include <linux/ktime.h> 12 13#include "sb_regs.h" 14#include "tb.h" 15 16#define USB4_DATA_DWORDS 16 17#define USB4_DATA_RETRIES 3 18 19enum usb4_switch_op { 20 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10, 21 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11, 22 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12, 23 USB4_SWITCH_OP_NVM_WRITE = 0x20, 24 USB4_SWITCH_OP_NVM_AUTH = 0x21, 25 USB4_SWITCH_OP_NVM_READ = 0x22, 26 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23, 27 USB4_SWITCH_OP_DROM_READ = 0x24, 28 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25, 29}; 30 31enum usb4_sb_target { 32 USB4_SB_TARGET_ROUTER, 33 USB4_SB_TARGET_PARTNER, 34 USB4_SB_TARGET_RETIMER, 35}; 36 37#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2) 38#define USB4_NVM_READ_OFFSET_SHIFT 2 39#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24) 40#define USB4_NVM_READ_LENGTH_SHIFT 24 41 42#define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK 43#define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT 44 45#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2) 46#define USB4_DROM_ADDRESS_SHIFT 2 47#define USB4_DROM_SIZE_MASK GENMASK(19, 15) 48#define USB4_DROM_SIZE_SHIFT 15 49 50#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0) 51 52typedef int (*read_block_fn)(void *, unsigned int, void *, size_t); 53typedef int (*write_block_fn)(void *, const void *, size_t); 54 55static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, 56 u32 value, int timeout_msec) 57{ 58 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); 59 60 do { 61 u32 val; 62 int ret; 63 64 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); 65 if (ret) 66 return ret; 67 68 if ((val & bit) == value) 69 return 0; 70 71 usleep_range(50, 100); 72 } while (ktime_before(ktime_get(), timeout)); 73 74 return -ETIMEDOUT; 75} 76 77static int usb4_switch_op_read_data(struct tb_switch *sw, void *data, 78 size_t dwords) 79{ 80 if (dwords > USB4_DATA_DWORDS) 81 return -EINVAL; 82 83 return tb_sw_read(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords); 84} 85 86static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data, 87 size_t dwords) 88{ 89 if (dwords > USB4_DATA_DWORDS) 90 return -EINVAL; 91 92 return tb_sw_write(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords); 93} 94 95static int usb4_switch_op_read_metadata(struct tb_switch *sw, u32 *metadata) 96{ 97 return tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 98} 99 100static int usb4_switch_op_write_metadata(struct tb_switch *sw, u32 metadata) 101{ 102 return tb_sw_write(sw, &metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 103} 104 105static int usb4_do_read_data(u16 address, void *buf, size_t size, 106 read_block_fn read_block, void *read_block_data) 107{ 108 unsigned int retries = USB4_DATA_RETRIES; 109 unsigned int offset; 110 111 do { 112 unsigned int dwaddress, dwords; 113 u8 data[USB4_DATA_DWORDS * 4]; 114 size_t nbytes; 115 int ret; 116 117 offset = address & 3; 118 nbytes = min_t(size_t, size + offset, USB4_DATA_DWORDS * 4); 119 120 dwaddress = address / 4; 121 dwords = ALIGN(nbytes, 4) / 4; 122 123 ret = read_block(read_block_data, dwaddress, data, dwords); 124 if (ret) { 125 if (ret != -ENODEV && retries--) 126 continue; 127 return ret; 128 } 129 130 nbytes -= offset; 131 memcpy(buf, data + offset, nbytes); 132 133 size -= nbytes; 134 address += nbytes; 135 buf += nbytes; 136 } while (size > 0); 137 138 return 0; 139} 140 141static int usb4_do_write_data(unsigned int address, const void *buf, size_t size, 142 write_block_fn write_next_block, void *write_block_data) 143{ 144 unsigned int retries = USB4_DATA_RETRIES; 145 unsigned int offset; 146 147 offset = address & 3; 148 address = address & ~3; 149 150 do { 151 u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4); 152 u8 data[USB4_DATA_DWORDS * 4]; 153 int ret; 154 155 memcpy(data + offset, buf, nbytes); 156 157 ret = write_next_block(write_block_data, data, nbytes / 4); 158 if (ret) { 159 if (ret == -ETIMEDOUT) { 160 if (retries--) 161 continue; 162 ret = -EIO; 163 } 164 return ret; 165 } 166 167 size -= nbytes; 168 address += nbytes; 169 buf += nbytes; 170 } while (size > 0); 171 172 return 0; 173} 174 175static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u8 *status) 176{ 177 u32 val; 178 int ret; 179 180 val = opcode | ROUTER_CS_26_OV; 181 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 182 if (ret) 183 return ret; 184 185 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); 186 if (ret) 187 return ret; 188 189 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 190 if (ret) 191 return ret; 192 193 if (val & ROUTER_CS_26_ONS) 194 return -EOPNOTSUPP; 195 196 *status = (val & ROUTER_CS_26_STATUS_MASK) >> ROUTER_CS_26_STATUS_SHIFT; 197 return 0; 198} 199 200static void usb4_switch_check_wakes(struct tb_switch *sw) 201{ 202 struct tb_port *port; 203 bool wakeup = false; 204 u32 val; 205 206 if (!device_may_wakeup(&sw->dev)) 207 return; 208 209 if (tb_route(sw)) { 210 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1)) 211 return; 212 213 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n", 214 (val & ROUTER_CS_6_WOPS) ? "yes" : "no", 215 (val & ROUTER_CS_6_WOUS) ? "yes" : "no"); 216 217 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS); 218 } 219 220 /* Check for any connected downstream ports for USB4 wake */ 221 tb_switch_for_each_port(sw, port) { 222 if (!tb_port_has_remote(port)) 223 continue; 224 225 if (tb_port_read(port, &val, TB_CFG_PORT, 226 port->cap_usb4 + PORT_CS_18, 1)) 227 break; 228 229 tb_port_dbg(port, "USB4 wake: %s\n", 230 (val & PORT_CS_18_WOU4S) ? "yes" : "no"); 231 232 if (val & PORT_CS_18_WOU4S) 233 wakeup = true; 234 } 235 236 if (wakeup) 237 pm_wakeup_event(&sw->dev, 0); 238} 239 240static bool link_is_usb4(struct tb_port *port) 241{ 242 u32 val; 243 244 if (!port->cap_usb4) 245 return false; 246 247 if (tb_port_read(port, &val, TB_CFG_PORT, 248 port->cap_usb4 + PORT_CS_18, 1)) 249 return false; 250 251 return !(val & PORT_CS_18_TCM); 252} 253 254/** 255 * usb4_switch_setup() - Additional setup for USB4 device 256 * @sw: USB4 router to setup 257 * 258 * USB4 routers need additional settings in order to enable all the 259 * tunneling. This function enables USB and PCIe tunneling if it can be 260 * enabled (e.g the parent switch also supports them). If USB tunneling 261 * is not available for some reason (like that there is Thunderbolt 3 262 * switch upstream) then the internal xHCI controller is enabled 263 * instead. 264 */ 265int usb4_switch_setup(struct tb_switch *sw) 266{ 267 struct tb_port *downstream_port; 268 struct tb_switch *parent; 269 bool tbt3, xhci; 270 u32 val = 0; 271 int ret; 272 273 usb4_switch_check_wakes(sw); 274 275 if (!tb_route(sw)) 276 return 0; 277 278 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1); 279 if (ret) 280 return ret; 281 282 parent = tb_switch_parent(sw); 283 downstream_port = tb_port_at(tb_route(sw), parent); 284 sw->link_usb4 = link_is_usb4(downstream_port); 285 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT3"); 286 287 xhci = val & ROUTER_CS_6_HCI; 288 tbt3 = !(val & ROUTER_CS_6_TNS); 289 290 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n", 291 tbt3 ? "yes" : "no", xhci ? "yes" : "no"); 292 293 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 294 if (ret) 295 return ret; 296 297 if (sw->link_usb4 && tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) { 298 val |= ROUTER_CS_5_UTO; 299 xhci = false; 300 } 301 302 /* Only enable PCIe tunneling if the parent router supports it */ 303 if (tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { 304 val |= ROUTER_CS_5_PTO; 305 /* 306 * xHCI can be enabled if PCIe tunneling is supported 307 * and the parent does not have any USB3 dowstream 308 * adapters (so we cannot do USB 3.x tunneling). 309 */ 310 if (xhci) 311 val |= ROUTER_CS_5_HCO; 312 } 313 314 /* TBT3 supported by the CM */ 315 val |= ROUTER_CS_5_C3S; 316 /* Tunneling configuration is ready now */ 317 val |= ROUTER_CS_5_CV; 318 319 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 320 if (ret) 321 return ret; 322 323 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR, 324 ROUTER_CS_6_CR, 50); 325} 326 327/** 328 * usb4_switch_read_uid() - Read UID from USB4 router 329 * @sw: USB4 router 330 * @uid: UID is stored here 331 * 332 * Reads 64-bit UID from USB4 router config space. 333 */ 334int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) 335{ 336 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2); 337} 338 339static int usb4_switch_drom_read_block(void *data, 340 unsigned int dwaddress, void *buf, 341 size_t dwords) 342{ 343 struct tb_switch *sw = data; 344 u8 status = 0; 345 u32 metadata; 346 int ret; 347 348 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK; 349 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) & 350 USB4_DROM_ADDRESS_MASK; 351 352 ret = usb4_switch_op_write_metadata(sw, metadata); 353 if (ret) 354 return ret; 355 356 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DROM_READ, &status); 357 if (ret) 358 return ret; 359 360 if (status) 361 return -EIO; 362 363 return usb4_switch_op_read_data(sw, buf, dwords); 364} 365 366/** 367 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM 368 * @sw: USB4 router 369 * @address: Byte address inside DROM to start reading 370 * @buf: Buffer where the DROM content is stored 371 * @size: Number of bytes to read from DROM 372 * 373 * Uses USB4 router operations to read router DROM. For devices this 374 * should always work but for hosts it may return %-EOPNOTSUPP in which 375 * case the host router does not have DROM. 376 */ 377int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, 378 size_t size) 379{ 380 return usb4_do_read_data(address, buf, size, 381 usb4_switch_drom_read_block, sw); 382} 383 384/** 385 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding 386 * @sw: USB4 router 387 * 388 * Checks whether conditions are met so that lane bonding can be 389 * established with the upstream router. Call only for device routers. 390 */ 391bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) 392{ 393 struct tb_port *up; 394 int ret; 395 u32 val; 396 397 up = tb_upstream_port(sw); 398 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); 399 if (ret) 400 return false; 401 402 return !!(val & PORT_CS_18_BE); 403} 404 405/** 406 * usb4_switch_set_wake() - Enabled/disable wake 407 * @sw: USB4 router 408 * @flags: Wakeup flags (%0 to disable) 409 * 410 * Enables/disables router to wake up from sleep. 411 */ 412int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags) 413{ 414 struct tb_port *port; 415 u64 route = tb_route(sw); 416 u32 val; 417 int ret; 418 419 /* 420 * Enable wakes coming from all USB4 downstream ports (from 421 * child routers). For device routers do this also for the 422 * upstream USB4 port. 423 */ 424 tb_switch_for_each_port(sw, port) { 425 if (!tb_port_is_null(port)) 426 continue; 427 if (!route && tb_is_upstream_port(port)) 428 continue; 429 if (!port->cap_usb4) 430 continue; 431 432 ret = tb_port_read(port, &val, TB_CFG_PORT, 433 port->cap_usb4 + PORT_CS_19, 1); 434 if (ret) 435 return ret; 436 437 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4); 438 439 if (flags & TB_WAKE_ON_CONNECT) 440 val |= PORT_CS_19_WOC; 441 if (flags & TB_WAKE_ON_DISCONNECT) 442 val |= PORT_CS_19_WOD; 443 if (flags & TB_WAKE_ON_USB4) 444 val |= PORT_CS_19_WOU4; 445 446 ret = tb_port_write(port, &val, TB_CFG_PORT, 447 port->cap_usb4 + PORT_CS_19, 1); 448 if (ret) 449 return ret; 450 } 451 452 /* 453 * Enable wakes from PCIe and USB 3.x on this router. Only 454 * needed for device routers. 455 */ 456 if (route) { 457 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 458 if (ret) 459 return ret; 460 461 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU); 462 if (flags & TB_WAKE_ON_USB3) 463 val |= ROUTER_CS_5_WOU; 464 if (flags & TB_WAKE_ON_PCIE) 465 val |= ROUTER_CS_5_WOP; 466 467 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 468 if (ret) 469 return ret; 470 } 471 472 return 0; 473} 474 475/** 476 * usb4_switch_set_sleep() - Prepare the router to enter sleep 477 * @sw: USB4 router 478 * 479 * Sets sleep bit for the router. Returns when the router sleep ready 480 * bit has been asserted. 481 */ 482int usb4_switch_set_sleep(struct tb_switch *sw) 483{ 484 int ret; 485 u32 val; 486 487 /* Set sleep bit and wait for sleep ready to be asserted */ 488 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 489 if (ret) 490 return ret; 491 492 val |= ROUTER_CS_5_SLP; 493 494 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 495 if (ret) 496 return ret; 497 498 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR, 499 ROUTER_CS_6_SLPR, 500); 500} 501 502/** 503 * usb4_switch_nvm_sector_size() - Return router NVM sector size 504 * @sw: USB4 router 505 * 506 * If the router supports NVM operations this function returns the NVM 507 * sector size in bytes. If NVM operations are not supported returns 508 * %-EOPNOTSUPP. 509 */ 510int usb4_switch_nvm_sector_size(struct tb_switch *sw) 511{ 512 u32 metadata; 513 u8 status; 514 int ret; 515 516 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &status); 517 if (ret) 518 return ret; 519 520 if (status) 521 return status == 0x2 ? -EOPNOTSUPP : -EIO; 522 523 ret = usb4_switch_op_read_metadata(sw, &metadata); 524 if (ret) 525 return ret; 526 527 return metadata & USB4_NVM_SECTOR_SIZE_MASK; 528} 529 530static int usb4_switch_nvm_read_block(void *data, 531 unsigned int dwaddress, void *buf, size_t dwords) 532{ 533 struct tb_switch *sw = data; 534 u8 status = 0; 535 u32 metadata; 536 int ret; 537 538 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) & 539 USB4_NVM_READ_LENGTH_MASK; 540 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) & 541 USB4_NVM_READ_OFFSET_MASK; 542 543 ret = usb4_switch_op_write_metadata(sw, metadata); 544 if (ret) 545 return ret; 546 547 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_READ, &status); 548 if (ret) 549 return ret; 550 551 if (status) 552 return -EIO; 553 554 return usb4_switch_op_read_data(sw, buf, dwords); 555} 556 557/** 558 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM 559 * @sw: USB4 router 560 * @address: Starting address in bytes 561 * @buf: Read data is placed here 562 * @size: How many bytes to read 563 * 564 * Reads NVM contents of the router. If NVM is not supported returns 565 * %-EOPNOTSUPP. 566 */ 567int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, 568 size_t size) 569{ 570 return usb4_do_read_data(address, buf, size, 571 usb4_switch_nvm_read_block, sw); 572} 573 574static int usb4_switch_nvm_set_offset(struct tb_switch *sw, 575 unsigned int address) 576{ 577 u32 metadata, dwaddress; 578 u8 status = 0; 579 int ret; 580 581 dwaddress = address / 4; 582 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 583 USB4_NVM_SET_OFFSET_MASK; 584 585 ret = usb4_switch_op_write_metadata(sw, metadata); 586 if (ret) 587 return ret; 588 589 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &status); 590 if (ret) 591 return ret; 592 593 return status ? -EIO : 0; 594} 595 596static int usb4_switch_nvm_write_next_block(void *data, const void *buf, 597 size_t dwords) 598{ 599 struct tb_switch *sw = data; 600 u8 status; 601 int ret; 602 603 ret = usb4_switch_op_write_data(sw, buf, dwords); 604 if (ret) 605 return ret; 606 607 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_WRITE, &status); 608 if (ret) 609 return ret; 610 611 return status ? -EIO : 0; 612} 613 614/** 615 * usb4_switch_nvm_write() - Write to the router NVM 616 * @sw: USB4 router 617 * @address: Start address where to write in bytes 618 * @buf: Pointer to the data to write 619 * @size: Size of @buf in bytes 620 * 621 * Writes @buf to the router NVM using USB4 router operations. If NVM 622 * write is not supported returns %-EOPNOTSUPP. 623 */ 624int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, 625 const void *buf, size_t size) 626{ 627 int ret; 628 629 ret = usb4_switch_nvm_set_offset(sw, address); 630 if (ret) 631 return ret; 632 633 return usb4_do_write_data(address, buf, size, 634 usb4_switch_nvm_write_next_block, sw); 635} 636 637/** 638 * usb4_switch_nvm_authenticate() - Authenticate new NVM 639 * @sw: USB4 router 640 * 641 * After the new NVM has been written via usb4_switch_nvm_write(), this 642 * function triggers NVM authentication process. If the authentication 643 * is successful the router is power cycled and the new NVM starts 644 * running. In case of failure returns negative errno. 645 */ 646int usb4_switch_nvm_authenticate(struct tb_switch *sw) 647{ 648 u8 status = 0; 649 int ret; 650 651 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, &status); 652 if (ret) 653 return ret; 654 655 switch (status) { 656 case 0x0: 657 tb_sw_dbg(sw, "NVM authentication successful\n"); 658 return 0; 659 case 0x1: 660 return -EINVAL; 661 case 0x2: 662 return -EAGAIN; 663 case 0x3: 664 return -EOPNOTSUPP; 665 default: 666 return -EIO; 667 } 668} 669 670/** 671 * usb4_switch_query_dp_resource() - Query availability of DP IN resource 672 * @sw: USB4 router 673 * @in: DP IN adapter 674 * 675 * For DP tunneling this function can be used to query availability of 676 * DP IN resource. Returns true if the resource is available for DP 677 * tunneling, false otherwise. 678 */ 679bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) 680{ 681 u8 status; 682 int ret; 683 684 ret = usb4_switch_op_write_metadata(sw, in->port); 685 if (ret) 686 return false; 687 688 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &status); 689 /* 690 * If DP resource allocation is not supported assume it is 691 * always available. 692 */ 693 if (ret == -EOPNOTSUPP) 694 return true; 695 else if (ret) 696 return false; 697 698 return !status; 699} 700 701/** 702 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource 703 * @sw: USB4 router 704 * @in: DP IN adapter 705 * 706 * Allocates DP IN resource for DP tunneling using USB4 router 707 * operations. If the resource was allocated returns %0. Otherwise 708 * returns negative errno, in particular %-EBUSY if the resource is 709 * already allocated. 710 */ 711int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 712{ 713 u8 status; 714 int ret; 715 716 ret = usb4_switch_op_write_metadata(sw, in->port); 717 if (ret) 718 return ret; 719 720 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &status); 721 if (ret == -EOPNOTSUPP) 722 return 0; 723 else if (ret) 724 return ret; 725 726 return status ? -EBUSY : 0; 727} 728 729/** 730 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource 731 * @sw: USB4 router 732 * @in: DP IN adapter 733 * 734 * Releases the previously allocated DP IN resource. 735 */ 736int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 737{ 738 u8 status; 739 int ret; 740 741 ret = usb4_switch_op_write_metadata(sw, in->port); 742 if (ret) 743 return ret; 744 745 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &status); 746 if (ret == -EOPNOTSUPP) 747 return 0; 748 else if (ret) 749 return ret; 750 751 return status ? -EIO : 0; 752} 753 754static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) 755{ 756 struct tb_port *p; 757 int usb4_idx = 0; 758 759 /* Assume port is primary */ 760 tb_switch_for_each_port(sw, p) { 761 if (!tb_port_is_null(p)) 762 continue; 763 if (tb_is_upstream_port(p)) 764 continue; 765 if (!p->link_nr) { 766 if (p == port) 767 break; 768 usb4_idx++; 769 } 770 } 771 772 return usb4_idx; 773} 774 775/** 776 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter 777 * @sw: USB4 router 778 * @port: USB4 port 779 * 780 * USB4 routers have direct mapping between USB4 ports and PCIe 781 * downstream adapters where the PCIe topology is extended. This 782 * function returns the corresponding downstream PCIe adapter or %NULL 783 * if no such mapping was possible. 784 */ 785struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, 786 const struct tb_port *port) 787{ 788 int usb4_idx = usb4_port_idx(sw, port); 789 struct tb_port *p; 790 int pcie_idx = 0; 791 792 /* Find PCIe down port matching usb4_port */ 793 tb_switch_for_each_port(sw, p) { 794 if (!tb_port_is_pcie_down(p)) 795 continue; 796 797 if (pcie_idx == usb4_idx) 798 return p; 799 800 pcie_idx++; 801 } 802 803 return NULL; 804} 805 806/** 807 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter 808 * @sw: USB4 router 809 * @port: USB4 port 810 * 811 * USB4 routers have direct mapping between USB4 ports and USB 3.x 812 * downstream adapters where the USB 3.x topology is extended. This 813 * function returns the corresponding downstream USB 3.x adapter or 814 * %NULL if no such mapping was possible. 815 */ 816struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, 817 const struct tb_port *port) 818{ 819 int usb4_idx = usb4_port_idx(sw, port); 820 struct tb_port *p; 821 int usb_idx = 0; 822 823 /* Find USB3 down port matching usb4_port */ 824 tb_switch_for_each_port(sw, p) { 825 if (!tb_port_is_usb3_down(p)) 826 continue; 827 828 if (usb_idx == usb4_idx) 829 return p; 830 831 usb_idx++; 832 } 833 834 return NULL; 835} 836 837/** 838 * usb4_port_unlock() - Unlock USB4 downstream port 839 * @port: USB4 port to unlock 840 * 841 * Unlocks USB4 downstream port so that the connection manager can 842 * access the router below this port. 843 */ 844int usb4_port_unlock(struct tb_port *port) 845{ 846 int ret; 847 u32 val; 848 849 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 850 if (ret) 851 return ret; 852 853 val &= ~ADP_CS_4_LCK; 854 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 855} 856 857/** 858 * usb4_port_hotplug_enable() - Enables hotplug for a port 859 * @port: USB4 port to operate on 860 * 861 * Enables hot plug events on a given port. This is only intended 862 * to be used on lane, DP-IN, and DP-OUT adapters. 863 */ 864int usb4_port_hotplug_enable(struct tb_port *port) 865{ 866 int ret; 867 u32 val; 868 869 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); 870 if (ret) 871 return ret; 872 873 val &= ~ADP_CS_5_DHP; 874 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); 875} 876 877static int usb4_port_set_configured(struct tb_port *port, bool configured) 878{ 879 int ret; 880 u32 val; 881 882 if (!port->cap_usb4) 883 return -EINVAL; 884 885 ret = tb_port_read(port, &val, TB_CFG_PORT, 886 port->cap_usb4 + PORT_CS_19, 1); 887 if (ret) 888 return ret; 889 890 if (configured) 891 val |= PORT_CS_19_PC; 892 else 893 val &= ~PORT_CS_19_PC; 894 895 return tb_port_write(port, &val, TB_CFG_PORT, 896 port->cap_usb4 + PORT_CS_19, 1); 897} 898 899/** 900 * usb4_port_configure() - Set USB4 port configured 901 * @port: USB4 router 902 * 903 * Sets the USB4 link to be configured for power management purposes. 904 */ 905int usb4_port_configure(struct tb_port *port) 906{ 907 return usb4_port_set_configured(port, true); 908} 909 910/** 911 * usb4_port_unconfigure() - Set USB4 port unconfigured 912 * @port: USB4 router 913 * 914 * Sets the USB4 link to be unconfigured for power management purposes. 915 */ 916void usb4_port_unconfigure(struct tb_port *port) 917{ 918 usb4_port_set_configured(port, false); 919} 920 921static int usb4_set_xdomain_configured(struct tb_port *port, bool configured) 922{ 923 int ret; 924 u32 val; 925 926 if (!port->cap_usb4) 927 return -EINVAL; 928 929 ret = tb_port_read(port, &val, TB_CFG_PORT, 930 port->cap_usb4 + PORT_CS_19, 1); 931 if (ret) 932 return ret; 933 934 if (configured) 935 val |= PORT_CS_19_PID; 936 else 937 val &= ~PORT_CS_19_PID; 938 939 return tb_port_write(port, &val, TB_CFG_PORT, 940 port->cap_usb4 + PORT_CS_19, 1); 941} 942 943/** 944 * usb4_port_configure_xdomain() - Configure port for XDomain 945 * @port: USB4 port connected to another host 946 * 947 * Marks the USB4 port as being connected to another host. Returns %0 in 948 * success and negative errno in failure. 949 */ 950int usb4_port_configure_xdomain(struct tb_port *port) 951{ 952 return usb4_set_xdomain_configured(port, true); 953} 954 955/** 956 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain 957 * @port: USB4 port that was connected to another host 958 * 959 * Clears USB4 port from being marked as XDomain. 960 */ 961void usb4_port_unconfigure_xdomain(struct tb_port *port) 962{ 963 usb4_set_xdomain_configured(port, false); 964} 965 966static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit, 967 u32 value, int timeout_msec) 968{ 969 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); 970 971 do { 972 u32 val; 973 int ret; 974 975 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1); 976 if (ret) 977 return ret; 978 979 if ((val & bit) == value) 980 return 0; 981 982 usleep_range(50, 100); 983 } while (ktime_before(ktime_get(), timeout)); 984 985 return -ETIMEDOUT; 986} 987 988static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords) 989{ 990 if (dwords > USB4_DATA_DWORDS) 991 return -EINVAL; 992 993 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 994 dwords); 995} 996 997static int usb4_port_write_data(struct tb_port *port, const void *data, 998 size_t dwords) 999{ 1000 if (dwords > USB4_DATA_DWORDS) 1001 return -EINVAL; 1002 1003 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 1004 dwords); 1005} 1006 1007static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, 1008 u8 index, u8 reg, void *buf, u8 size) 1009{ 1010 size_t dwords = DIV_ROUND_UP(size, 4); 1011 int ret; 1012 u32 val; 1013 1014 if (!port->cap_usb4) 1015 return -EINVAL; 1016 1017 val = reg; 1018 val |= size << PORT_CS_1_LENGTH_SHIFT; 1019 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1020 if (target == USB4_SB_TARGET_RETIMER) 1021 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1022 val |= PORT_CS_1_PND; 1023 1024 ret = tb_port_write(port, &val, TB_CFG_PORT, 1025 port->cap_usb4 + PORT_CS_1, 1); 1026 if (ret) 1027 return ret; 1028 1029 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1030 PORT_CS_1_PND, 0, 500); 1031 if (ret) 1032 return ret; 1033 1034 ret = tb_port_read(port, &val, TB_CFG_PORT, 1035 port->cap_usb4 + PORT_CS_1, 1); 1036 if (ret) 1037 return ret; 1038 1039 if (val & PORT_CS_1_NR) 1040 return -ENODEV; 1041 if (val & PORT_CS_1_RC) 1042 return -EIO; 1043 1044 return buf ? usb4_port_read_data(port, buf, dwords) : 0; 1045} 1046 1047static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target, 1048 u8 index, u8 reg, const void *buf, u8 size) 1049{ 1050 size_t dwords = DIV_ROUND_UP(size, 4); 1051 int ret; 1052 u32 val; 1053 1054 if (!port->cap_usb4) 1055 return -EINVAL; 1056 1057 if (buf) { 1058 ret = usb4_port_write_data(port, buf, dwords); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 val = reg; 1064 val |= size << PORT_CS_1_LENGTH_SHIFT; 1065 val |= PORT_CS_1_WNR_WRITE; 1066 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1067 if (target == USB4_SB_TARGET_RETIMER) 1068 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1069 val |= PORT_CS_1_PND; 1070 1071 ret = tb_port_write(port, &val, TB_CFG_PORT, 1072 port->cap_usb4 + PORT_CS_1, 1); 1073 if (ret) 1074 return ret; 1075 1076 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1077 PORT_CS_1_PND, 0, 500); 1078 if (ret) 1079 return ret; 1080 1081 ret = tb_port_read(port, &val, TB_CFG_PORT, 1082 port->cap_usb4 + PORT_CS_1, 1); 1083 if (ret) 1084 return ret; 1085 1086 if (val & PORT_CS_1_NR) 1087 return -ENODEV; 1088 if (val & PORT_CS_1_RC) 1089 return -EIO; 1090 1091 return 0; 1092} 1093 1094static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target, 1095 u8 index, enum usb4_sb_opcode opcode, int timeout_msec) 1096{ 1097 ktime_t timeout; 1098 u32 val; 1099 int ret; 1100 1101 val = opcode; 1102 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val, 1103 sizeof(val)); 1104 if (ret) 1105 return ret; 1106 1107 timeout = ktime_add_ms(ktime_get(), timeout_msec); 1108 1109 do { 1110 /* Check results */ 1111 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE, 1112 &val, sizeof(val)); 1113 if (ret) 1114 return ret; 1115 1116 switch (val) { 1117 case 0: 1118 return 0; 1119 1120 case USB4_SB_OPCODE_ERR: 1121 return -EAGAIN; 1122 1123 case USB4_SB_OPCODE_ONS: 1124 return -EOPNOTSUPP; 1125 1126 default: 1127 if (val != opcode) 1128 return -EIO; 1129 break; 1130 } 1131 } while (ktime_before(ktime_get(), timeout)); 1132 1133 return -ETIMEDOUT; 1134} 1135 1136/** 1137 * usb4_port_enumerate_retimers() - Send RT broadcast transaction 1138 * @port: USB4 port 1139 * 1140 * This forces the USB4 port to send broadcast RT transaction which 1141 * makes the retimers on the link to assign index to themselves. Returns 1142 * %0 in case of success and negative errno if there was an error. 1143 */ 1144int usb4_port_enumerate_retimers(struct tb_port *port) 1145{ 1146 u32 val; 1147 1148 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS; 1149 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, 1150 USB4_SB_OPCODE, &val, sizeof(val)); 1151} 1152 1153static inline int usb4_port_retimer_op(struct tb_port *port, u8 index, 1154 enum usb4_sb_opcode opcode, 1155 int timeout_msec) 1156{ 1157 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode, 1158 timeout_msec); 1159} 1160 1161/** 1162 * usb4_port_retimer_read() - Read from retimer sideband registers 1163 * @port: USB4 port 1164 * @index: Retimer index 1165 * @reg: Sideband register to read 1166 * @buf: Data from @reg is stored here 1167 * @size: Number of bytes to read 1168 * 1169 * Function reads retimer sideband registers starting from @reg. The 1170 * retimer is connected to @port at @index. Returns %0 in case of 1171 * success, and read data is copied to @buf. If there is no retimer 1172 * present at given @index returns %-ENODEV. In any other failure 1173 * returns negative errno. 1174 */ 1175int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, 1176 u8 size) 1177{ 1178 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1179 size); 1180} 1181 1182/** 1183 * usb4_port_retimer_write() - Write to retimer sideband registers 1184 * @port: USB4 port 1185 * @index: Retimer index 1186 * @reg: Sideband register to write 1187 * @buf: Data that is written starting from @reg 1188 * @size: Number of bytes to write 1189 * 1190 * Writes retimer sideband registers starting from @reg. The retimer is 1191 * connected to @port at @index. Returns %0 in case of success. If there 1192 * is no retimer present at given @index returns %-ENODEV. In any other 1193 * failure returns negative errno. 1194 */ 1195int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, 1196 const void *buf, u8 size) 1197{ 1198 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1199 size); 1200} 1201 1202/** 1203 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer 1204 * @port: USB4 port 1205 * @index: Retimer index 1206 * 1207 * If the retimer at @index is last one (connected directly to the 1208 * Type-C port) this function returns %1. If it is not returns %0. If 1209 * the retimer is not present returns %-ENODEV. Otherwise returns 1210 * negative errno. 1211 */ 1212int usb4_port_retimer_is_last(struct tb_port *port, u8 index) 1213{ 1214 u32 metadata; 1215 int ret; 1216 1217 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER, 1218 500); 1219 if (ret) 1220 return ret; 1221 1222 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1223 sizeof(metadata)); 1224 return ret ? ret : metadata & 1; 1225} 1226 1227/** 1228 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size 1229 * @port: USB4 port 1230 * @index: Retimer index 1231 * 1232 * Reads NVM sector size (in bytes) of a retimer at @index. This 1233 * operation can be used to determine whether the retimer supports NVM 1234 * upgrade for example. Returns sector size in bytes or negative errno 1235 * in case of error. Specifically returns %-ENODEV if there is no 1236 * retimer at @index. 1237 */ 1238int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index) 1239{ 1240 u32 metadata; 1241 int ret; 1242 1243 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE, 1244 500); 1245 if (ret) 1246 return ret; 1247 1248 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1249 sizeof(metadata)); 1250 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK; 1251} 1252 1253static int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, 1254 unsigned int address) 1255{ 1256 u32 metadata, dwaddress; 1257 int ret; 1258 1259 dwaddress = address / 4; 1260 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 1261 USB4_NVM_SET_OFFSET_MASK; 1262 1263 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1264 sizeof(metadata)); 1265 if (ret) 1266 return ret; 1267 1268 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET, 1269 500); 1270} 1271 1272struct retimer_info { 1273 struct tb_port *port; 1274 u8 index; 1275}; 1276 1277static int usb4_port_retimer_nvm_write_next_block(void *data, const void *buf, 1278 size_t dwords) 1279 1280{ 1281 const struct retimer_info *info = data; 1282 struct tb_port *port = info->port; 1283 u8 index = info->index; 1284 int ret; 1285 1286 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA, 1287 buf, dwords * 4); 1288 if (ret) 1289 return ret; 1290 1291 return usb4_port_retimer_op(port, index, 1292 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000); 1293} 1294 1295/** 1296 * usb4_port_retimer_nvm_write() - Write to retimer NVM 1297 * @port: USB4 port 1298 * @index: Retimer index 1299 * @address: Byte address where to start the write 1300 * @buf: Data to write 1301 * @size: Size in bytes how much to write 1302 * 1303 * Writes @size bytes from @buf to the retimer NVM. Used for NVM 1304 * upgrade. Returns %0 if the data was written successfully and negative 1305 * errno in case of failure. Specifically returns %-ENODEV if there is 1306 * no retimer at @index. 1307 */ 1308int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address, 1309 const void *buf, size_t size) 1310{ 1311 struct retimer_info info = { .port = port, .index = index }; 1312 int ret; 1313 1314 ret = usb4_port_retimer_nvm_set_offset(port, index, address); 1315 if (ret) 1316 return ret; 1317 1318 return usb4_do_write_data(address, buf, size, 1319 usb4_port_retimer_nvm_write_next_block, &info); 1320} 1321 1322/** 1323 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade 1324 * @port: USB4 port 1325 * @index: Retimer index 1326 * 1327 * After the new NVM image has been written via usb4_port_retimer_nvm_write() 1328 * this function can be used to trigger the NVM upgrade process. If 1329 * successful the retimer restarts with the new NVM and may not have the 1330 * index set so one needs to call usb4_port_enumerate_retimers() to 1331 * force index to be assigned. 1332 */ 1333int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index) 1334{ 1335 u32 val; 1336 1337 /* 1338 * We need to use the raw operation here because once the 1339 * authentication completes the retimer index is not set anymore 1340 * so we do not get back the status now. 1341 */ 1342 val = USB4_SB_OPCODE_NVM_AUTH_WRITE; 1343 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, 1344 USB4_SB_OPCODE, &val, sizeof(val)); 1345} 1346 1347/** 1348 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade 1349 * @port: USB4 port 1350 * @index: Retimer index 1351 * @status: Raw status code read from metadata 1352 * 1353 * This can be called after usb4_port_retimer_nvm_authenticate() and 1354 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade. 1355 * 1356 * Returns %0 if the authentication status was successfully read. The 1357 * completion metadata (the result) is then stored into @status. If 1358 * reading the status fails, returns negative errno. 1359 */ 1360int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, 1361 u32 *status) 1362{ 1363 u32 metadata, val; 1364 int ret; 1365 1366 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val, 1367 sizeof(val)); 1368 if (ret) 1369 return ret; 1370 1371 switch (val) { 1372 case 0: 1373 *status = 0; 1374 return 0; 1375 1376 case USB4_SB_OPCODE_ERR: 1377 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, 1378 &metadata, sizeof(metadata)); 1379 if (ret) 1380 return ret; 1381 1382 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK; 1383 return 0; 1384 1385 case USB4_SB_OPCODE_ONS: 1386 return -EOPNOTSUPP; 1387 1388 default: 1389 return -EIO; 1390 } 1391} 1392 1393static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress, 1394 void *buf, size_t dwords) 1395{ 1396 const struct retimer_info *info = data; 1397 struct tb_port *port = info->port; 1398 u8 index = info->index; 1399 u32 metadata; 1400 int ret; 1401 1402 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT; 1403 if (dwords < USB4_DATA_DWORDS) 1404 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT; 1405 1406 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1407 sizeof(metadata)); 1408 if (ret) 1409 return ret; 1410 1411 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500); 1412 if (ret) 1413 return ret; 1414 1415 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf, 1416 dwords * 4); 1417} 1418 1419/** 1420 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM 1421 * @port: USB4 port 1422 * @index: Retimer index 1423 * @address: NVM address (in bytes) to start reading 1424 * @buf: Data read from NVM is stored here 1425 * @size: Number of bytes to read 1426 * 1427 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the 1428 * read was successful and negative errno in case of failure. 1429 * Specifically returns %-ENODEV if there is no retimer at @index. 1430 */ 1431int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, 1432 unsigned int address, void *buf, size_t size) 1433{ 1434 struct retimer_info info = { .port = port, .index = index }; 1435 1436 return usb4_do_read_data(address, buf, size, 1437 usb4_port_retimer_nvm_read_block, &info); 1438} 1439 1440/** 1441 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate 1442 * @port: USB3 adapter port 1443 * 1444 * Return maximum supported link rate of a USB3 adapter in Mb/s. 1445 * Negative errno in case of error. 1446 */ 1447int usb4_usb3_port_max_link_rate(struct tb_port *port) 1448{ 1449 int ret, lr; 1450 u32 val; 1451 1452 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1453 return -EINVAL; 1454 1455 ret = tb_port_read(port, &val, TB_CFG_PORT, 1456 port->cap_adap + ADP_USB3_CS_4, 1); 1457 if (ret) 1458 return ret; 1459 1460 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT; 1461 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000; 1462} 1463 1464/** 1465 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate 1466 * @port: USB3 adapter port 1467 * 1468 * Return actual established link rate of a USB3 adapter in Mb/s. If the 1469 * link is not up returns %0 and negative errno in case of failure. 1470 */ 1471int usb4_usb3_port_actual_link_rate(struct tb_port *port) 1472{ 1473 int ret, lr; 1474 u32 val; 1475 1476 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1477 return -EINVAL; 1478 1479 ret = tb_port_read(port, &val, TB_CFG_PORT, 1480 port->cap_adap + ADP_USB3_CS_4, 1); 1481 if (ret) 1482 return ret; 1483 1484 if (!(val & ADP_USB3_CS_4_ULV)) 1485 return 0; 1486 1487 lr = val & ADP_USB3_CS_4_ALR_MASK; 1488 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000; 1489} 1490 1491static int usb4_usb3_port_cm_request(struct tb_port *port, bool request) 1492{ 1493 int ret; 1494 u32 val; 1495 1496 if (!tb_port_is_usb3_down(port)) 1497 return -EINVAL; 1498 if (tb_route(port->sw)) 1499 return -EINVAL; 1500 1501 ret = tb_port_read(port, &val, TB_CFG_PORT, 1502 port->cap_adap + ADP_USB3_CS_2, 1); 1503 if (ret) 1504 return ret; 1505 1506 if (request) 1507 val |= ADP_USB3_CS_2_CMR; 1508 else 1509 val &= ~ADP_USB3_CS_2_CMR; 1510 1511 ret = tb_port_write(port, &val, TB_CFG_PORT, 1512 port->cap_adap + ADP_USB3_CS_2, 1); 1513 if (ret) 1514 return ret; 1515 1516 /* 1517 * We can use val here directly as the CMR bit is in the same place 1518 * as HCA. Just mask out others. 1519 */ 1520 val &= ADP_USB3_CS_2_CMR; 1521 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1, 1522 ADP_USB3_CS_1_HCA, val, 1500); 1523} 1524 1525static inline int usb4_usb3_port_set_cm_request(struct tb_port *port) 1526{ 1527 return usb4_usb3_port_cm_request(port, true); 1528} 1529 1530static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port) 1531{ 1532 return usb4_usb3_port_cm_request(port, false); 1533} 1534 1535static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale) 1536{ 1537 unsigned long uframes; 1538 1539 uframes = bw * 512UL << scale; 1540 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000); 1541} 1542 1543static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale) 1544{ 1545 unsigned long uframes; 1546 1547 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */ 1548 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000; 1549 return DIV_ROUND_UP(uframes, 512UL << scale); 1550} 1551 1552static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port, 1553 int *upstream_bw, 1554 int *downstream_bw) 1555{ 1556 u32 val, bw, scale; 1557 int ret; 1558 1559 ret = tb_port_read(port, &val, TB_CFG_PORT, 1560 port->cap_adap + ADP_USB3_CS_2, 1); 1561 if (ret) 1562 return ret; 1563 1564 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1565 port->cap_adap + ADP_USB3_CS_3, 1); 1566 if (ret) 1567 return ret; 1568 1569 scale &= ADP_USB3_CS_3_SCALE_MASK; 1570 1571 bw = val & ADP_USB3_CS_2_AUBW_MASK; 1572 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1573 1574 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT; 1575 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1576 1577 return 0; 1578} 1579 1580/** 1581 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3 1582 * @port: USB3 adapter port 1583 * @upstream_bw: Allocated upstream bandwidth is stored here 1584 * @downstream_bw: Allocated downstream bandwidth is stored here 1585 * 1586 * Stores currently allocated USB3 bandwidth into @upstream_bw and 1587 * @downstream_bw in Mb/s. Returns %0 in case of success and negative 1588 * errno in failure. 1589 */ 1590int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, 1591 int *downstream_bw) 1592{ 1593 int ret; 1594 1595 ret = usb4_usb3_port_set_cm_request(port); 1596 if (ret) 1597 return ret; 1598 1599 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw, 1600 downstream_bw); 1601 usb4_usb3_port_clear_cm_request(port); 1602 1603 return ret; 1604} 1605 1606static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port, 1607 int *upstream_bw, 1608 int *downstream_bw) 1609{ 1610 u32 val, bw, scale; 1611 int ret; 1612 1613 ret = tb_port_read(port, &val, TB_CFG_PORT, 1614 port->cap_adap + ADP_USB3_CS_1, 1); 1615 if (ret) 1616 return ret; 1617 1618 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1619 port->cap_adap + ADP_USB3_CS_3, 1); 1620 if (ret) 1621 return ret; 1622 1623 scale &= ADP_USB3_CS_3_SCALE_MASK; 1624 1625 bw = val & ADP_USB3_CS_1_CUBW_MASK; 1626 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1627 1628 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT; 1629 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1630 1631 return 0; 1632} 1633 1634static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port, 1635 int upstream_bw, 1636 int downstream_bw) 1637{ 1638 u32 val, ubw, dbw, scale; 1639 int ret, max_bw; 1640 1641 /* Figure out suitable scale */ 1642 scale = 0; 1643 max_bw = max(upstream_bw, downstream_bw); 1644 while (scale < 64) { 1645 if (mbps_to_usb3_bw(max_bw, scale) < 4096) 1646 break; 1647 scale++; 1648 } 1649 1650 if (WARN_ON(scale >= 64)) 1651 return -EINVAL; 1652 1653 ret = tb_port_write(port, &scale, TB_CFG_PORT, 1654 port->cap_adap + ADP_USB3_CS_3, 1); 1655 if (ret) 1656 return ret; 1657 1658 ubw = mbps_to_usb3_bw(upstream_bw, scale); 1659 dbw = mbps_to_usb3_bw(downstream_bw, scale); 1660 1661 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale); 1662 1663 ret = tb_port_read(port, &val, TB_CFG_PORT, 1664 port->cap_adap + ADP_USB3_CS_2, 1); 1665 if (ret) 1666 return ret; 1667 1668 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK); 1669 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT; 1670 val |= ubw; 1671 1672 return tb_port_write(port, &val, TB_CFG_PORT, 1673 port->cap_adap + ADP_USB3_CS_2, 1); 1674} 1675 1676/** 1677 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3 1678 * @port: USB3 adapter port 1679 * @upstream_bw: New upstream bandwidth 1680 * @downstream_bw: New downstream bandwidth 1681 * 1682 * This can be used to set how much bandwidth is allocated for the USB3 1683 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the 1684 * new values programmed to the USB3 adapter allocation registers. If 1685 * the values are lower than what is currently consumed the allocation 1686 * is set to what is currently consumed instead (consumed bandwidth 1687 * cannot be taken away by CM). The actual new values are returned in 1688 * @upstream_bw and @downstream_bw. 1689 * 1690 * Returns %0 in case of success and negative errno if there was a 1691 * failure. 1692 */ 1693int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, 1694 int *downstream_bw) 1695{ 1696 int ret, consumed_up, consumed_down, allocate_up, allocate_down; 1697 1698 ret = usb4_usb3_port_set_cm_request(port); 1699 if (ret) 1700 return ret; 1701 1702 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 1703 &consumed_down); 1704 if (ret) 1705 goto err_request; 1706 1707 /* Don't allow it go lower than what is consumed */ 1708 allocate_up = max(*upstream_bw, consumed_up); 1709 allocate_down = max(*downstream_bw, consumed_down); 1710 1711 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up, 1712 allocate_down); 1713 if (ret) 1714 goto err_request; 1715 1716 *upstream_bw = allocate_up; 1717 *downstream_bw = allocate_down; 1718 1719err_request: 1720 usb4_usb3_port_clear_cm_request(port); 1721 return ret; 1722} 1723 1724/** 1725 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth 1726 * @port: USB3 adapter port 1727 * @upstream_bw: New allocated upstream bandwidth 1728 * @downstream_bw: New allocated downstream bandwidth 1729 * 1730 * Releases USB3 allocated bandwidth down to what is actually consumed. 1731 * The new bandwidth is returned in @upstream_bw and @downstream_bw. 1732 * 1733 * Returns 0% in success and negative errno in case of failure. 1734 */ 1735int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, 1736 int *downstream_bw) 1737{ 1738 int ret, consumed_up, consumed_down; 1739 1740 ret = usb4_usb3_port_set_cm_request(port); 1741 if (ret) 1742 return ret; 1743 1744 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 1745 &consumed_down); 1746 if (ret) 1747 goto err_request; 1748 1749 /* 1750 * Always keep 1000 Mb/s to make sure xHCI has at least some 1751 * bandwidth available for isochronous traffic. 1752 */ 1753 if (consumed_up < 1000) 1754 consumed_up = 1000; 1755 if (consumed_down < 1000) 1756 consumed_down = 1000; 1757 1758 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, 1759 consumed_down); 1760 if (ret) 1761 goto err_request; 1762 1763 *upstream_bw = consumed_up; 1764 *downstream_bw = consumed_down; 1765 1766err_request: 1767 usb4_usb3_port_clear_cm_request(port); 1768 return ret; 1769} 1770