1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019, Linaro Limited 4 */ 5 6#include <linux/bitops.h> 7#include <linux/regmap.h> 8#include <linux/delay.h> 9#include <linux/slab.h> 10#include "tsens.h" 11 12/* ----- SROT ------ */ 13#define SROT_HW_VER_OFF 0x0000 14#define SROT_CTRL_OFF 0x0004 15 16/* ----- TM ------ */ 17#define TM_INT_EN_OFF 0x0000 18#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 19#define TM_Sn_STATUS_OFF 0x0044 20#define TM_TRDY_OFF 0x0084 21#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 22#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 23 24/* eeprom layout data for msm8956/76 (v1) */ 25#define MSM8976_BASE0_MASK 0xff 26#define MSM8976_BASE1_MASK 0xff 27#define MSM8976_BASE1_SHIFT 8 28 29#define MSM8976_S0_P1_MASK 0x3f00 30#define MSM8976_S1_P1_MASK 0x3f00000 31#define MSM8976_S2_P1_MASK 0x3f 32#define MSM8976_S3_P1_MASK 0x3f000 33#define MSM8976_S4_P1_MASK 0x3f00 34#define MSM8976_S5_P1_MASK 0x3f00000 35#define MSM8976_S6_P1_MASK 0x3f 36#define MSM8976_S7_P1_MASK 0x3f000 37#define MSM8976_S8_P1_MASK 0x1f8 38#define MSM8976_S9_P1_MASK 0x1f8000 39#define MSM8976_S10_P1_MASK 0xf8000000 40#define MSM8976_S10_P1_MASK_1 0x1 41 42#define MSM8976_S0_P2_MASK 0xfc000 43#define MSM8976_S1_P2_MASK 0xfc000000 44#define MSM8976_S2_P2_MASK 0xfc0 45#define MSM8976_S3_P2_MASK 0xfc0000 46#define MSM8976_S4_P2_MASK 0xfc000 47#define MSM8976_S5_P2_MASK 0xfc000000 48#define MSM8976_S6_P2_MASK 0xfc0 49#define MSM8976_S7_P2_MASK 0xfc0000 50#define MSM8976_S8_P2_MASK 0x7e00 51#define MSM8976_S9_P2_MASK 0x7e00000 52#define MSM8976_S10_P2_MASK 0x7e 53 54#define MSM8976_S0_P1_SHIFT 8 55#define MSM8976_S1_P1_SHIFT 20 56#define MSM8976_S2_P1_SHIFT 0 57#define MSM8976_S3_P1_SHIFT 12 58#define MSM8976_S4_P1_SHIFT 8 59#define MSM8976_S5_P1_SHIFT 20 60#define MSM8976_S6_P1_SHIFT 0 61#define MSM8976_S7_P1_SHIFT 12 62#define MSM8976_S8_P1_SHIFT 3 63#define MSM8976_S9_P1_SHIFT 15 64#define MSM8976_S10_P1_SHIFT 27 65#define MSM8976_S10_P1_SHIFT_1 0 66 67#define MSM8976_S0_P2_SHIFT 14 68#define MSM8976_S1_P2_SHIFT 26 69#define MSM8976_S2_P2_SHIFT 6 70#define MSM8976_S3_P2_SHIFT 18 71#define MSM8976_S4_P2_SHIFT 14 72#define MSM8976_S5_P2_SHIFT 26 73#define MSM8976_S6_P2_SHIFT 6 74#define MSM8976_S7_P2_SHIFT 18 75#define MSM8976_S8_P2_SHIFT 9 76#define MSM8976_S9_P2_SHIFT 21 77#define MSM8976_S10_P2_SHIFT 1 78 79#define MSM8976_CAL_SEL_MASK 0x3 80 81/* eeprom layout data for qcs404/405 (v1) */ 82#define BASE0_MASK 0x000007f8 83#define BASE1_MASK 0x0007f800 84#define BASE0_SHIFT 3 85#define BASE1_SHIFT 11 86 87#define S0_P1_MASK 0x0000003f 88#define S1_P1_MASK 0x0003f000 89#define S2_P1_MASK 0x3f000000 90#define S3_P1_MASK 0x000003f0 91#define S4_P1_MASK 0x003f0000 92#define S5_P1_MASK 0x0000003f 93#define S6_P1_MASK 0x0003f000 94#define S7_P1_MASK 0x3f000000 95#define S8_P1_MASK 0x000003f0 96#define S9_P1_MASK 0x003f0000 97 98#define S0_P2_MASK 0x00000fc0 99#define S1_P2_MASK 0x00fc0000 100#define S2_P2_MASK_1_0 0xc0000000 101#define S2_P2_MASK_5_2 0x0000000f 102#define S3_P2_MASK 0x0000fc00 103#define S4_P2_MASK 0x0fc00000 104#define S5_P2_MASK 0x00000fc0 105#define S6_P2_MASK 0x00fc0000 106#define S7_P2_MASK_1_0 0xc0000000 107#define S7_P2_MASK_5_2 0x0000000f 108#define S8_P2_MASK 0x0000fc00 109#define S9_P2_MASK 0x0fc00000 110 111#define S0_P1_SHIFT 0 112#define S0_P2_SHIFT 6 113#define S1_P1_SHIFT 12 114#define S1_P2_SHIFT 18 115#define S2_P1_SHIFT 24 116#define S2_P2_SHIFT_1_0 30 117 118#define S2_P2_SHIFT_5_2 0 119#define S3_P1_SHIFT 4 120#define S3_P2_SHIFT 10 121#define S4_P1_SHIFT 16 122#define S4_P2_SHIFT 22 123 124#define S5_P1_SHIFT 0 125#define S5_P2_SHIFT 6 126#define S6_P1_SHIFT 12 127#define S6_P2_SHIFT 18 128#define S7_P1_SHIFT 24 129#define S7_P2_SHIFT_1_0 30 130 131#define S7_P2_SHIFT_5_2 0 132#define S8_P1_SHIFT 4 133#define S8_P2_SHIFT 10 134#define S9_P1_SHIFT 16 135#define S9_P2_SHIFT 22 136 137#define CAL_SEL_MASK 7 138#define CAL_SEL_SHIFT 0 139 140static int calibrate_v1(struct tsens_priv *priv) 141{ 142 u32 base0 = 0, base1 = 0; 143 u32 p1[10], p2[10]; 144 u32 mode = 0, lsb = 0, msb = 0; 145 u32 *qfprom_cdata; 146 int i; 147 148 qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); 149 if (IS_ERR(qfprom_cdata)) 150 return PTR_ERR(qfprom_cdata); 151 152 mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; 153 dev_dbg(priv->dev, "calibration mode is %d\n", mode); 154 155 switch (mode) { 156 case TWO_PT_CALIB: 157 base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; 158 p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; 159 p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; 160 /* This value is split over two registers, 2 bits and 4 bits */ 161 lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; 162 msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; 163 p2[2] = msb << 2 | lsb; 164 p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; 165 p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; 166 p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; 167 p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; 168 /* This value is split over two registers, 2 bits and 4 bits */ 169 lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; 170 msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; 171 p2[7] = msb << 2 | lsb; 172 p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; 173 p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; 174 for (i = 0; i < priv->num_sensors; i++) 175 p2[i] = ((base1 + p2[i]) << 2); 176 fallthrough; 177 case ONE_PT_CALIB2: 178 base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; 179 p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; 180 p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; 181 p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; 182 p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; 183 p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; 184 p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; 185 p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; 186 p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; 187 p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; 188 p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; 189 for (i = 0; i < priv->num_sensors; i++) 190 p1[i] = (((base0) + p1[i]) << 2); 191 break; 192 default: 193 for (i = 0; i < priv->num_sensors; i++) { 194 p1[i] = 500; 195 p2[i] = 780; 196 } 197 break; 198 } 199 200 compute_intercept_slope(priv, p1, p2, mode); 201 kfree(qfprom_cdata); 202 203 return 0; 204} 205 206static int calibrate_8976(struct tsens_priv *priv) 207{ 208 int base0 = 0, base1 = 0, i; 209 u32 p1[11], p2[11]; 210 int mode = 0, tmp = 0; 211 u32 *qfprom_cdata; 212 213 qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); 214 if (IS_ERR(qfprom_cdata)) 215 return PTR_ERR(qfprom_cdata); 216 217 mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); 218 dev_dbg(priv->dev, "calibration mode is %d\n", mode); 219 220 switch (mode) { 221 case TWO_PT_CALIB: 222 base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; 223 p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; 224 p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; 225 p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; 226 p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; 227 p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; 228 p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; 229 p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; 230 p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; 231 p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; 232 p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; 233 p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; 234 235 for (i = 0; i < priv->num_sensors; i++) 236 p2[i] = ((base1 + p2[i]) << 2); 237 fallthrough; 238 case ONE_PT_CALIB2: 239 base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; 240 p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; 241 p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; 242 p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; 243 p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; 244 p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; 245 p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; 246 p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; 247 p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; 248 p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; 249 p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; 250 p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; 251 tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; 252 p1[10] |= tmp; 253 254 for (i = 0; i < priv->num_sensors; i++) 255 p1[i] = (((base0) + p1[i]) << 2); 256 break; 257 default: 258 for (i = 0; i < priv->num_sensors; i++) { 259 p1[i] = 500; 260 p2[i] = 780; 261 } 262 break; 263 } 264 265 compute_intercept_slope(priv, p1, p2, mode); 266 kfree(qfprom_cdata); 267 268 return 0; 269} 270 271/* v1.x: msm8956,8976,qcs404,405 */ 272 273static struct tsens_features tsens_v1_feat = { 274 .ver_major = VER_1_X, 275 .crit_int = 0, 276 .adc = 1, 277 .srot_split = 1, 278 .max_sensors = 11, 279}; 280 281static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { 282 /* ----- SROT ------ */ 283 /* VERSION */ 284 [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31), 285 [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27), 286 [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15), 287 /* CTRL_OFFSET */ 288 [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), 289 [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), 290 [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13), 291 292 /* ----- TM ------ */ 293 /* INTERRUPT ENABLE */ 294 [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), 295 296 /* UPPER/LOWER TEMPERATURE THRESHOLDS */ 297 REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), 298 REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), 299 300 /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ 301 REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), 302 REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), 303 [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), 304 [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), 305 [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), 306 [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3), 307 [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4), 308 [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5), 309 [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6), 310 [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7), 311 [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8), 312 [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9), 313 [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10), 314 [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11), 315 [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12), 316 [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13), 317 [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14), 318 [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15), 319 320 /* NO CRITICAL INTERRUPT SUPPORT on v1 */ 321 322 /* Sn_STATUS */ 323 REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), 324 REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), 325 /* xxx_STATUS bits: 1 == threshold violated */ 326 REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), 327 REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), 328 REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), 329 /* No CRITICAL field on v1.x */ 330 REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13), 331 332 /* TRDY: 1=ready, 0=in progress */ 333 [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), 334}; 335 336static int __init init_8956(struct tsens_priv *priv) { 337 priv->sensor[0].slope = 3313; 338 priv->sensor[1].slope = 3275; 339 priv->sensor[2].slope = 3320; 340 priv->sensor[3].slope = 3246; 341 priv->sensor[4].slope = 3279; 342 priv->sensor[5].slope = 3257; 343 priv->sensor[6].slope = 3234; 344 priv->sensor[7].slope = 3269; 345 priv->sensor[8].slope = 3255; 346 priv->sensor[9].slope = 3239; 347 priv->sensor[10].slope = 3286; 348 349 return init_common(priv); 350} 351 352static const struct tsens_ops ops_generic_v1 = { 353 .init = init_common, 354 .calibrate = calibrate_v1, 355 .get_temp = get_temp_tsens_valid, 356}; 357 358struct tsens_plat_data data_tsens_v1 = { 359 .ops = &ops_generic_v1, 360 .feat = &tsens_v1_feat, 361 .fields = tsens_v1_regfields, 362}; 363 364static const struct tsens_ops ops_8956 = { 365 .init = init_8956, 366 .calibrate = calibrate_8976, 367 .get_temp = get_temp_tsens_valid, 368}; 369 370struct tsens_plat_data data_8956 = { 371 .num_sensors = 11, 372 .ops = &ops_8956, 373 .feat = &tsens_v1_feat, 374 .fields = tsens_v1_regfields, 375}; 376 377static const struct tsens_ops ops_8976 = { 378 .init = init_common, 379 .calibrate = calibrate_8976, 380 .get_temp = get_temp_tsens_valid, 381}; 382 383struct tsens_plat_data data_8976 = { 384 .num_sensors = 11, 385 .ops = &ops_8976, 386 .hw_ids = (unsigned int[]){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, 387 .feat = &tsens_v1_feat, 388 .fields = tsens_v1_regfields, 389}; 390