1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * SPI bus driver for the Topcliff PCH used by Intel SoCs 4 * 5 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 6 */ 7 8#include <linux/delay.h> 9#include <linux/pci.h> 10#include <linux/wait.h> 11#include <linux/spi/spi.h> 12#include <linux/interrupt.h> 13#include <linux/sched.h> 14#include <linux/spi/spidev.h> 15#include <linux/module.h> 16#include <linux/device.h> 17#include <linux/platform_device.h> 18 19#include <linux/dmaengine.h> 20#include <linux/pch_dma.h> 21 22/* Register offsets */ 23#define PCH_SPCR 0x00 /* SPI control register */ 24#define PCH_SPBRR 0x04 /* SPI baud rate register */ 25#define PCH_SPSR 0x08 /* SPI status register */ 26#define PCH_SPDWR 0x0C /* SPI write data register */ 27#define PCH_SPDRR 0x10 /* SPI read data register */ 28#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ 29#define PCH_SRST 0x1C /* SPI reset register */ 30#define PCH_ADDRESS_SIZE 0x20 31 32#define PCH_SPSR_TFD 0x000007C0 33#define PCH_SPSR_RFD 0x0000F800 34 35#define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) 36#define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) 37 38#define PCH_RX_THOLD 7 39#define PCH_RX_THOLD_MAX 15 40 41#define PCH_TX_THOLD 2 42 43#define PCH_MAX_BAUDRATE 5000000 44#define PCH_MAX_FIFO_DEPTH 16 45 46#define STATUS_RUNNING 1 47#define STATUS_EXITING 2 48#define PCH_SLEEP_TIME 10 49 50#define SSN_LOW 0x02U 51#define SSN_HIGH 0x03U 52#define SSN_NO_CONTROL 0x00U 53#define PCH_MAX_CS 0xFF 54#define PCI_DEVICE_ID_GE_SPI 0x8816 55 56#define SPCR_SPE_BIT (1 << 0) 57#define SPCR_MSTR_BIT (1 << 1) 58#define SPCR_LSBF_BIT (1 << 4) 59#define SPCR_CPHA_BIT (1 << 5) 60#define SPCR_CPOL_BIT (1 << 6) 61#define SPCR_TFIE_BIT (1 << 8) 62#define SPCR_RFIE_BIT (1 << 9) 63#define SPCR_FIE_BIT (1 << 10) 64#define SPCR_ORIE_BIT (1 << 11) 65#define SPCR_MDFIE_BIT (1 << 12) 66#define SPCR_FICLR_BIT (1 << 24) 67#define SPSR_TFI_BIT (1 << 0) 68#define SPSR_RFI_BIT (1 << 1) 69#define SPSR_FI_BIT (1 << 2) 70#define SPSR_ORF_BIT (1 << 3) 71#define SPBRR_SIZE_BIT (1 << 10) 72 73#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ 74 SPCR_ORIE_BIT|SPCR_MDFIE_BIT) 75 76#define SPCR_RFIC_FIELD 20 77#define SPCR_TFIC_FIELD 16 78 79#define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) 80#define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) 81#define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) 82 83#define PCH_CLOCK_HZ 50000000 84#define PCH_MAX_SPBR 1023 85 86/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ 87#define PCI_DEVICE_ID_ML7213_SPI 0x802c 88#define PCI_DEVICE_ID_ML7223_SPI 0x800F 89#define PCI_DEVICE_ID_ML7831_SPI 0x8816 90 91/* 92 * Set the number of SPI instance max 93 * Intel EG20T PCH : 1ch 94 * LAPIS Semiconductor ML7213 IOH : 2ch 95 * LAPIS Semiconductor ML7223 IOH : 1ch 96 * LAPIS Semiconductor ML7831 IOH : 1ch 97*/ 98#define PCH_SPI_MAX_DEV 2 99 100#define PCH_BUF_SIZE 4096 101#define PCH_DMA_TRANS_SIZE 12 102 103static int use_dma = 1; 104 105struct pch_spi_dma_ctrl { 106 struct dma_async_tx_descriptor *desc_tx; 107 struct dma_async_tx_descriptor *desc_rx; 108 struct pch_dma_slave param_tx; 109 struct pch_dma_slave param_rx; 110 struct dma_chan *chan_tx; 111 struct dma_chan *chan_rx; 112 struct scatterlist *sg_tx_p; 113 struct scatterlist *sg_rx_p; 114 struct scatterlist sg_tx; 115 struct scatterlist sg_rx; 116 int nent; 117 void *tx_buf_virt; 118 void *rx_buf_virt; 119 dma_addr_t tx_buf_dma; 120 dma_addr_t rx_buf_dma; 121}; 122/** 123 * struct pch_spi_data - Holds the SPI channel specific details 124 * @io_remap_addr: The remapped PCI base address 125 * @io_base_addr: Base address 126 * @master: Pointer to the SPI master structure 127 * @work: Reference to work queue handler 128 * @wait: Wait queue for waking up upon receiving an 129 * interrupt. 130 * @transfer_complete: Status of SPI Transfer 131 * @bcurrent_msg_processing: Status flag for message processing 132 * @lock: Lock for protecting this structure 133 * @queue: SPI Message queue 134 * @status: Status of the SPI driver 135 * @bpw_len: Length of data to be transferred in bits per 136 * word 137 * @transfer_active: Flag showing active transfer 138 * @tx_index: Transmit data count; for bookkeeping during 139 * transfer 140 * @rx_index: Receive data count; for bookkeeping during 141 * transfer 142 * @pkt_tx_buff: Buffer for data to be transmitted 143 * @pkt_rx_buff: Buffer for received data 144 * @n_curnt_chip: The chip number that this SPI driver currently 145 * operates on 146 * @current_chip: Reference to the current chip that this SPI 147 * driver currently operates on 148 * @current_msg: The current message that this SPI driver is 149 * handling 150 * @cur_trans: The current transfer that this SPI driver is 151 * handling 152 * @board_dat: Reference to the SPI device data structure 153 * @plat_dev: platform_device structure 154 * @ch: SPI channel number 155 * @dma: Local DMA information 156 * @use_dma: True if DMA is to be used 157 * @irq_reg_sts: Status of IRQ registration 158 * @save_total_len: Save length while data is being transferred 159 */ 160struct pch_spi_data { 161 void __iomem *io_remap_addr; 162 unsigned long io_base_addr; 163 struct spi_master *master; 164 struct work_struct work; 165 wait_queue_head_t wait; 166 u8 transfer_complete; 167 u8 bcurrent_msg_processing; 168 spinlock_t lock; 169 struct list_head queue; 170 u8 status; 171 u32 bpw_len; 172 u8 transfer_active; 173 u32 tx_index; 174 u32 rx_index; 175 u16 *pkt_tx_buff; 176 u16 *pkt_rx_buff; 177 u8 n_curnt_chip; 178 struct spi_device *current_chip; 179 struct spi_message *current_msg; 180 struct spi_transfer *cur_trans; 181 struct pch_spi_board_data *board_dat; 182 struct platform_device *plat_dev; 183 int ch; 184 struct pch_spi_dma_ctrl dma; 185 int use_dma; 186 u8 irq_reg_sts; 187 int save_total_len; 188}; 189 190/** 191 * struct pch_spi_board_data - Holds the SPI device specific details 192 * @pdev: Pointer to the PCI device 193 * @suspend_sts: Status of suspend 194 * @num: The number of SPI device instance 195 */ 196struct pch_spi_board_data { 197 struct pci_dev *pdev; 198 u8 suspend_sts; 199 int num; 200}; 201 202struct pch_pd_dev_save { 203 int num; 204 struct platform_device *pd_save[PCH_SPI_MAX_DEV]; 205 struct pch_spi_board_data *board_dat; 206}; 207 208static const struct pci_device_id pch_spi_pcidev_id[] = { 209 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, 210 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, 211 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, 212 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, 213 { } 214}; 215 216/** 217 * pch_spi_writereg() - Performs register writes 218 * @master: Pointer to struct spi_master. 219 * @idx: Register offset. 220 * @val: Value to be written to register. 221 */ 222static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) 223{ 224 struct pch_spi_data *data = spi_master_get_devdata(master); 225 iowrite32(val, (data->io_remap_addr + idx)); 226} 227 228/** 229 * pch_spi_readreg() - Performs register reads 230 * @master: Pointer to struct spi_master. 231 * @idx: Register offset. 232 */ 233static inline u32 pch_spi_readreg(struct spi_master *master, int idx) 234{ 235 struct pch_spi_data *data = spi_master_get_devdata(master); 236 return ioread32(data->io_remap_addr + idx); 237} 238 239static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, 240 u32 set, u32 clr) 241{ 242 u32 tmp = pch_spi_readreg(master, idx); 243 tmp = (tmp & ~clr) | set; 244 pch_spi_writereg(master, idx, tmp); 245} 246 247static void pch_spi_set_master_mode(struct spi_master *master) 248{ 249 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); 250} 251 252/** 253 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs 254 * @master: Pointer to struct spi_master. 255 */ 256static void pch_spi_clear_fifo(struct spi_master *master) 257{ 258 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); 259 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); 260} 261 262static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, 263 void __iomem *io_remap_addr) 264{ 265 u32 n_read, tx_index, rx_index, bpw_len; 266 u16 *pkt_rx_buffer, *pkt_tx_buff; 267 int read_cnt; 268 u32 reg_spcr_val; 269 void __iomem *spsr; 270 void __iomem *spdrr; 271 void __iomem *spdwr; 272 273 spsr = io_remap_addr + PCH_SPSR; 274 iowrite32(reg_spsr_val, spsr); 275 276 if (data->transfer_active) { 277 rx_index = data->rx_index; 278 tx_index = data->tx_index; 279 bpw_len = data->bpw_len; 280 pkt_rx_buffer = data->pkt_rx_buff; 281 pkt_tx_buff = data->pkt_tx_buff; 282 283 spdrr = io_remap_addr + PCH_SPDRR; 284 spdwr = io_remap_addr + PCH_SPDWR; 285 286 n_read = PCH_READABLE(reg_spsr_val); 287 288 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { 289 pkt_rx_buffer[rx_index++] = ioread32(spdrr); 290 if (tx_index < bpw_len) 291 iowrite32(pkt_tx_buff[tx_index++], spdwr); 292 } 293 294 /* disable RFI if not needed */ 295 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { 296 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); 297 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ 298 299 /* reset rx threshold */ 300 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; 301 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); 302 303 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); 304 } 305 306 /* update counts */ 307 data->tx_index = tx_index; 308 data->rx_index = rx_index; 309 310 /* if transfer complete interrupt */ 311 if (reg_spsr_val & SPSR_FI_BIT) { 312 if ((tx_index == bpw_len) && (rx_index == tx_index)) { 313 /* disable interrupts */ 314 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 315 PCH_ALL); 316 317 /* transfer is completed; 318 inform pch_spi_process_messages */ 319 data->transfer_complete = true; 320 data->transfer_active = false; 321 wake_up(&data->wait); 322 } else { 323 dev_vdbg(&data->master->dev, 324 "%s : Transfer is not completed", 325 __func__); 326 } 327 } 328 } 329} 330 331/** 332 * pch_spi_handler() - Interrupt handler 333 * @irq: The interrupt number. 334 * @dev_id: Pointer to struct pch_spi_board_data. 335 */ 336static irqreturn_t pch_spi_handler(int irq, void *dev_id) 337{ 338 u32 reg_spsr_val; 339 void __iomem *spsr; 340 void __iomem *io_remap_addr; 341 irqreturn_t ret = IRQ_NONE; 342 struct pch_spi_data *data = dev_id; 343 struct pch_spi_board_data *board_dat = data->board_dat; 344 345 if (board_dat->suspend_sts) { 346 dev_dbg(&board_dat->pdev->dev, 347 "%s returning due to suspend\n", __func__); 348 return IRQ_NONE; 349 } 350 351 io_remap_addr = data->io_remap_addr; 352 spsr = io_remap_addr + PCH_SPSR; 353 354 reg_spsr_val = ioread32(spsr); 355 356 if (reg_spsr_val & SPSR_ORF_BIT) { 357 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__); 358 if (data->current_msg->complete) { 359 data->transfer_complete = true; 360 data->current_msg->status = -EIO; 361 data->current_msg->complete(data->current_msg->context); 362 data->bcurrent_msg_processing = false; 363 data->current_msg = NULL; 364 data->cur_trans = NULL; 365 } 366 } 367 368 if (data->use_dma) 369 return IRQ_NONE; 370 371 /* Check if the interrupt is for SPI device */ 372 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { 373 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); 374 ret = IRQ_HANDLED; 375 } 376 377 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", 378 __func__, ret); 379 380 return ret; 381} 382 383/** 384 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR 385 * @master: Pointer to struct spi_master. 386 * @speed_hz: Baud rate. 387 */ 388static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) 389{ 390 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); 391 392 /* if baud rate is less than we can support limit it */ 393 if (n_spbr > PCH_MAX_SPBR) 394 n_spbr = PCH_MAX_SPBR; 395 396 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); 397} 398 399/** 400 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR 401 * @master: Pointer to struct spi_master. 402 * @bits_per_word: Bits per word for SPI transfer. 403 */ 404static void pch_spi_set_bits_per_word(struct spi_master *master, 405 u8 bits_per_word) 406{ 407 if (bits_per_word == 8) 408 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); 409 else 410 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); 411} 412 413/** 414 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer 415 * @spi: Pointer to struct spi_device. 416 */ 417static void pch_spi_setup_transfer(struct spi_device *spi) 418{ 419 u32 flags = 0; 420 421 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", 422 __func__, pch_spi_readreg(spi->master, PCH_SPBRR), 423 spi->max_speed_hz); 424 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); 425 426 /* set bits per word */ 427 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); 428 429 if (!(spi->mode & SPI_LSB_FIRST)) 430 flags |= SPCR_LSBF_BIT; 431 if (spi->mode & SPI_CPOL) 432 flags |= SPCR_CPOL_BIT; 433 if (spi->mode & SPI_CPHA) 434 flags |= SPCR_CPHA_BIT; 435 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, 436 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); 437 438 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ 439 pch_spi_clear_fifo(spi->master); 440} 441 442/** 443 * pch_spi_reset() - Clears SPI registers 444 * @master: Pointer to struct spi_master. 445 */ 446static void pch_spi_reset(struct spi_master *master) 447{ 448 /* write 1 to reset SPI */ 449 pch_spi_writereg(master, PCH_SRST, 0x1); 450 451 /* clear reset */ 452 pch_spi_writereg(master, PCH_SRST, 0x0); 453} 454 455static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) 456{ 457 458 struct spi_transfer *transfer; 459 struct pch_spi_data *data = spi_master_get_devdata(pspi->master); 460 int retval; 461 unsigned long flags; 462 463 spin_lock_irqsave(&data->lock, flags); 464 /* validate Tx/Rx buffers and Transfer length */ 465 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { 466 if (!transfer->tx_buf && !transfer->rx_buf) { 467 dev_err(&pspi->dev, 468 "%s Tx and Rx buffer NULL\n", __func__); 469 retval = -EINVAL; 470 goto err_return_spinlock; 471 } 472 473 if (!transfer->len) { 474 dev_err(&pspi->dev, "%s Transfer length invalid\n", 475 __func__); 476 retval = -EINVAL; 477 goto err_return_spinlock; 478 } 479 480 dev_dbg(&pspi->dev, 481 "%s Tx/Rx buffer valid. Transfer length valid\n", 482 __func__); 483 } 484 spin_unlock_irqrestore(&data->lock, flags); 485 486 /* We won't process any messages if we have been asked to terminate */ 487 if (data->status == STATUS_EXITING) { 488 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); 489 retval = -ESHUTDOWN; 490 goto err_out; 491 } 492 493 /* If suspended ,return -EINVAL */ 494 if (data->board_dat->suspend_sts) { 495 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); 496 retval = -EINVAL; 497 goto err_out; 498 } 499 500 /* set status of message */ 501 pmsg->actual_length = 0; 502 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); 503 504 pmsg->status = -EINPROGRESS; 505 spin_lock_irqsave(&data->lock, flags); 506 /* add message to queue */ 507 list_add_tail(&pmsg->queue, &data->queue); 508 spin_unlock_irqrestore(&data->lock, flags); 509 510 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); 511 512 schedule_work(&data->work); 513 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); 514 515 retval = 0; 516 517err_out: 518 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 519 return retval; 520err_return_spinlock: 521 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 522 spin_unlock_irqrestore(&data->lock, flags); 523 return retval; 524} 525 526static inline void pch_spi_select_chip(struct pch_spi_data *data, 527 struct spi_device *pspi) 528{ 529 if (data->current_chip != NULL) { 530 if (pspi->chip_select != data->n_curnt_chip) { 531 dev_dbg(&pspi->dev, "%s : different slave\n", __func__); 532 data->current_chip = NULL; 533 } 534 } 535 536 data->current_chip = pspi; 537 538 data->n_curnt_chip = data->current_chip->chip_select; 539 540 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); 541 pch_spi_setup_transfer(pspi); 542} 543 544static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) 545{ 546 int size; 547 u32 n_writes; 548 int j; 549 struct spi_message *pmsg, *tmp; 550 const u8 *tx_buf; 551 const u16 *tx_sbuf; 552 553 /* set baud rate if needed */ 554 if (data->cur_trans->speed_hz) { 555 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 556 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 557 } 558 559 /* set bits per word if needed */ 560 if (data->cur_trans->bits_per_word && 561 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { 562 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 563 pch_spi_set_bits_per_word(data->master, 564 data->cur_trans->bits_per_word); 565 *bpw = data->cur_trans->bits_per_word; 566 } else { 567 *bpw = data->current_msg->spi->bits_per_word; 568 } 569 570 /* reset Tx/Rx index */ 571 data->tx_index = 0; 572 data->rx_index = 0; 573 574 data->bpw_len = data->cur_trans->len / (*bpw / 8); 575 576 /* find alloc size */ 577 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); 578 579 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ 580 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); 581 if (data->pkt_tx_buff != NULL) { 582 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); 583 if (!data->pkt_rx_buff) { 584 kfree(data->pkt_tx_buff); 585 data->pkt_tx_buff = NULL; 586 } 587 } 588 589 if (!data->pkt_rx_buff) { 590 /* flush queue and set status of all transfers to -ENOMEM */ 591 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 592 pmsg->status = -ENOMEM; 593 594 if (pmsg->complete) 595 pmsg->complete(pmsg->context); 596 597 /* delete from queue */ 598 list_del_init(&pmsg->queue); 599 } 600 return; 601 } 602 603 /* copy Tx Data */ 604 if (data->cur_trans->tx_buf != NULL) { 605 if (*bpw == 8) { 606 tx_buf = data->cur_trans->tx_buf; 607 for (j = 0; j < data->bpw_len; j++) 608 data->pkt_tx_buff[j] = *tx_buf++; 609 } else { 610 tx_sbuf = data->cur_trans->tx_buf; 611 for (j = 0; j < data->bpw_len; j++) 612 data->pkt_tx_buff[j] = *tx_sbuf++; 613 } 614 } 615 616 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ 617 n_writes = data->bpw_len; 618 if (n_writes > PCH_MAX_FIFO_DEPTH) 619 n_writes = PCH_MAX_FIFO_DEPTH; 620 621 dev_dbg(&data->master->dev, 622 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", 623 __func__); 624 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 625 626 for (j = 0; j < n_writes; j++) 627 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); 628 629 /* update tx_index */ 630 data->tx_index = j; 631 632 /* reset transfer complete flag */ 633 data->transfer_complete = false; 634 data->transfer_active = true; 635} 636 637static void pch_spi_nomore_transfer(struct pch_spi_data *data) 638{ 639 struct spi_message *pmsg, *tmp; 640 dev_dbg(&data->master->dev, "%s called\n", __func__); 641 /* Invoke complete callback 642 * [To the spi core..indicating end of transfer] */ 643 data->current_msg->status = 0; 644 645 if (data->current_msg->complete) { 646 dev_dbg(&data->master->dev, 647 "%s:Invoking callback of SPI core\n", __func__); 648 data->current_msg->complete(data->current_msg->context); 649 } 650 651 /* update status in global variable */ 652 data->bcurrent_msg_processing = false; 653 654 dev_dbg(&data->master->dev, 655 "%s:data->bcurrent_msg_processing = false\n", __func__); 656 657 data->current_msg = NULL; 658 data->cur_trans = NULL; 659 660 /* check if we have items in list and not suspending 661 * return 1 if list empty */ 662 if ((list_empty(&data->queue) == 0) && 663 (!data->board_dat->suspend_sts) && 664 (data->status != STATUS_EXITING)) { 665 /* We have some more work to do (either there is more tranint 666 * bpw;sfer requests in the current message or there are 667 *more messages) 668 */ 669 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); 670 schedule_work(&data->work); 671 } else if (data->board_dat->suspend_sts || 672 data->status == STATUS_EXITING) { 673 dev_dbg(&data->master->dev, 674 "%s suspend/remove initiated, flushing queue\n", 675 __func__); 676 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 677 pmsg->status = -EIO; 678 679 if (pmsg->complete) 680 pmsg->complete(pmsg->context); 681 682 /* delete from queue */ 683 list_del_init(&pmsg->queue); 684 } 685 } 686} 687 688static void pch_spi_set_ir(struct pch_spi_data *data) 689{ 690 /* enable interrupts, set threshold, enable SPI */ 691 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) 692 /* set receive threshold to PCH_RX_THOLD */ 693 pch_spi_setclr_reg(data->master, PCH_SPCR, 694 PCH_RX_THOLD << SPCR_RFIC_FIELD | 695 SPCR_FIE_BIT | SPCR_RFIE_BIT | 696 SPCR_ORIE_BIT | SPCR_SPE_BIT, 697 MASK_RFIC_SPCR_BITS | PCH_ALL); 698 else 699 /* set receive threshold to maximum */ 700 pch_spi_setclr_reg(data->master, PCH_SPCR, 701 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | 702 SPCR_FIE_BIT | SPCR_ORIE_BIT | 703 SPCR_SPE_BIT, 704 MASK_RFIC_SPCR_BITS | PCH_ALL); 705 706 /* Wait until the transfer completes; go to sleep after 707 initiating the transfer. */ 708 dev_dbg(&data->master->dev, 709 "%s:waiting for transfer to get over\n", __func__); 710 711 wait_event_interruptible(data->wait, data->transfer_complete); 712 713 /* clear all interrupts */ 714 pch_spi_writereg(data->master, PCH_SPSR, 715 pch_spi_readreg(data->master, PCH_SPSR)); 716 /* Disable interrupts and SPI transfer */ 717 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); 718 /* clear FIFO */ 719 pch_spi_clear_fifo(data->master); 720} 721 722static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) 723{ 724 int j; 725 u8 *rx_buf; 726 u16 *rx_sbuf; 727 728 /* copy Rx Data */ 729 if (!data->cur_trans->rx_buf) 730 return; 731 732 if (bpw == 8) { 733 rx_buf = data->cur_trans->rx_buf; 734 for (j = 0; j < data->bpw_len; j++) 735 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; 736 } else { 737 rx_sbuf = data->cur_trans->rx_buf; 738 for (j = 0; j < data->bpw_len; j++) 739 *rx_sbuf++ = data->pkt_rx_buff[j]; 740 } 741} 742 743static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) 744{ 745 int j; 746 u8 *rx_buf; 747 u16 *rx_sbuf; 748 const u8 *rx_dma_buf; 749 const u16 *rx_dma_sbuf; 750 751 /* copy Rx Data */ 752 if (!data->cur_trans->rx_buf) 753 return; 754 755 if (bpw == 8) { 756 rx_buf = data->cur_trans->rx_buf; 757 rx_dma_buf = data->dma.rx_buf_virt; 758 for (j = 0; j < data->bpw_len; j++) 759 *rx_buf++ = *rx_dma_buf++ & 0xFF; 760 data->cur_trans->rx_buf = rx_buf; 761 } else { 762 rx_sbuf = data->cur_trans->rx_buf; 763 rx_dma_sbuf = data->dma.rx_buf_virt; 764 for (j = 0; j < data->bpw_len; j++) 765 *rx_sbuf++ = *rx_dma_sbuf++; 766 data->cur_trans->rx_buf = rx_sbuf; 767 } 768} 769 770static int pch_spi_start_transfer(struct pch_spi_data *data) 771{ 772 struct pch_spi_dma_ctrl *dma; 773 unsigned long flags; 774 int rtn; 775 776 dma = &data->dma; 777 778 spin_lock_irqsave(&data->lock, flags); 779 780 /* disable interrupts, SPI set enable */ 781 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); 782 783 spin_unlock_irqrestore(&data->lock, flags); 784 785 /* Wait until the transfer completes; go to sleep after 786 initiating the transfer. */ 787 dev_dbg(&data->master->dev, 788 "%s:waiting for transfer to get over\n", __func__); 789 rtn = wait_event_interruptible_timeout(data->wait, 790 data->transfer_complete, 791 msecs_to_jiffies(2 * HZ)); 792 if (!rtn) 793 dev_err(&data->master->dev, 794 "%s wait-event timeout\n", __func__); 795 796 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, 797 DMA_FROM_DEVICE); 798 799 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, 800 DMA_FROM_DEVICE); 801 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); 802 803 async_tx_ack(dma->desc_rx); 804 async_tx_ack(dma->desc_tx); 805 kfree(dma->sg_tx_p); 806 kfree(dma->sg_rx_p); 807 808 spin_lock_irqsave(&data->lock, flags); 809 810 /* clear fifo threshold, disable interrupts, disable SPI transfer */ 811 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 812 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | 813 SPCR_SPE_BIT); 814 /* clear all interrupts */ 815 pch_spi_writereg(data->master, PCH_SPSR, 816 pch_spi_readreg(data->master, PCH_SPSR)); 817 /* clear FIFO */ 818 pch_spi_clear_fifo(data->master); 819 820 spin_unlock_irqrestore(&data->lock, flags); 821 822 return rtn; 823} 824 825static void pch_dma_rx_complete(void *arg) 826{ 827 struct pch_spi_data *data = arg; 828 829 /* transfer is completed;inform pch_spi_process_messages_dma */ 830 data->transfer_complete = true; 831 wake_up_interruptible(&data->wait); 832} 833 834static bool pch_spi_filter(struct dma_chan *chan, void *slave) 835{ 836 struct pch_dma_slave *param = slave; 837 838 if ((chan->chan_id == param->chan_id) && 839 (param->dma_dev == chan->device->dev)) { 840 chan->private = param; 841 return true; 842 } else { 843 return false; 844 } 845} 846 847static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) 848{ 849 dma_cap_mask_t mask; 850 struct dma_chan *chan; 851 struct pci_dev *dma_dev; 852 struct pch_dma_slave *param; 853 struct pch_spi_dma_ctrl *dma; 854 unsigned int width; 855 856 if (bpw == 8) 857 width = PCH_DMA_WIDTH_1_BYTE; 858 else 859 width = PCH_DMA_WIDTH_2_BYTES; 860 861 dma = &data->dma; 862 dma_cap_zero(mask); 863 dma_cap_set(DMA_SLAVE, mask); 864 865 /* Get DMA's dev information */ 866 dma_dev = pci_get_slot(data->board_dat->pdev->bus, 867 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0)); 868 869 /* Set Tx DMA */ 870 param = &dma->param_tx; 871 param->dma_dev = &dma_dev->dev; 872 param->chan_id = data->ch * 2; /* Tx = 0, 2 */ 873 param->tx_reg = data->io_base_addr + PCH_SPDWR; 874 param->width = width; 875 chan = dma_request_channel(mask, pch_spi_filter, param); 876 if (!chan) { 877 dev_err(&data->master->dev, 878 "ERROR: dma_request_channel FAILS(Tx)\n"); 879 data->use_dma = 0; 880 return; 881 } 882 dma->chan_tx = chan; 883 884 /* Set Rx DMA */ 885 param = &dma->param_rx; 886 param->dma_dev = &dma_dev->dev; 887 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */ 888 param->rx_reg = data->io_base_addr + PCH_SPDRR; 889 param->width = width; 890 chan = dma_request_channel(mask, pch_spi_filter, param); 891 if (!chan) { 892 dev_err(&data->master->dev, 893 "ERROR: dma_request_channel FAILS(Rx)\n"); 894 dma_release_channel(dma->chan_tx); 895 dma->chan_tx = NULL; 896 data->use_dma = 0; 897 return; 898 } 899 dma->chan_rx = chan; 900} 901 902static void pch_spi_release_dma(struct pch_spi_data *data) 903{ 904 struct pch_spi_dma_ctrl *dma; 905 906 dma = &data->dma; 907 if (dma->chan_tx) { 908 dma_release_channel(dma->chan_tx); 909 dma->chan_tx = NULL; 910 } 911 if (dma->chan_rx) { 912 dma_release_channel(dma->chan_rx); 913 dma->chan_rx = NULL; 914 } 915} 916 917static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) 918{ 919 const u8 *tx_buf; 920 const u16 *tx_sbuf; 921 u8 *tx_dma_buf; 922 u16 *tx_dma_sbuf; 923 struct scatterlist *sg; 924 struct dma_async_tx_descriptor *desc_tx; 925 struct dma_async_tx_descriptor *desc_rx; 926 int num; 927 int i; 928 int size; 929 int rem; 930 int head; 931 unsigned long flags; 932 struct pch_spi_dma_ctrl *dma; 933 934 dma = &data->dma; 935 936 /* set baud rate if needed */ 937 if (data->cur_trans->speed_hz) { 938 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 939 spin_lock_irqsave(&data->lock, flags); 940 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 941 spin_unlock_irqrestore(&data->lock, flags); 942 } 943 944 /* set bits per word if needed */ 945 if (data->cur_trans->bits_per_word && 946 (data->current_msg->spi->bits_per_word != 947 data->cur_trans->bits_per_word)) { 948 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 949 spin_lock_irqsave(&data->lock, flags); 950 pch_spi_set_bits_per_word(data->master, 951 data->cur_trans->bits_per_word); 952 spin_unlock_irqrestore(&data->lock, flags); 953 *bpw = data->cur_trans->bits_per_word; 954 } else { 955 *bpw = data->current_msg->spi->bits_per_word; 956 } 957 data->bpw_len = data->cur_trans->len / (*bpw / 8); 958 959 if (data->bpw_len > PCH_BUF_SIZE) { 960 data->bpw_len = PCH_BUF_SIZE; 961 data->cur_trans->len -= PCH_BUF_SIZE; 962 } 963 964 /* copy Tx Data */ 965 if (data->cur_trans->tx_buf != NULL) { 966 if (*bpw == 8) { 967 tx_buf = data->cur_trans->tx_buf; 968 tx_dma_buf = dma->tx_buf_virt; 969 for (i = 0; i < data->bpw_len; i++) 970 *tx_dma_buf++ = *tx_buf++; 971 } else { 972 tx_sbuf = data->cur_trans->tx_buf; 973 tx_dma_sbuf = dma->tx_buf_virt; 974 for (i = 0; i < data->bpw_len; i++) 975 *tx_dma_sbuf++ = *tx_sbuf++; 976 } 977 } 978 979 /* Calculate Rx parameter for DMA transmitting */ 980 if (data->bpw_len > PCH_DMA_TRANS_SIZE) { 981 if (data->bpw_len % PCH_DMA_TRANS_SIZE) { 982 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 983 rem = data->bpw_len % PCH_DMA_TRANS_SIZE; 984 } else { 985 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 986 rem = PCH_DMA_TRANS_SIZE; 987 } 988 size = PCH_DMA_TRANS_SIZE; 989 } else { 990 num = 1; 991 size = data->bpw_len; 992 rem = data->bpw_len; 993 } 994 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", 995 __func__, num, size, rem); 996 spin_lock_irqsave(&data->lock, flags); 997 998 /* set receive fifo threshold and transmit fifo threshold */ 999 pch_spi_setclr_reg(data->master, PCH_SPCR, 1000 ((size - 1) << SPCR_RFIC_FIELD) | 1001 (PCH_TX_THOLD << SPCR_TFIC_FIELD), 1002 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); 1003 1004 spin_unlock_irqrestore(&data->lock, flags); 1005 1006 /* RX */ 1007 dma->sg_rx_p = kmalloc_array(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC); 1008 if (!dma->sg_rx_p) 1009 return; 1010 1011 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ 1012 /* offset, length setting */ 1013 sg = dma->sg_rx_p; 1014 for (i = 0; i < num; i++, sg++) { 1015 if (i == (num - 2)) { 1016 sg->offset = size * i; 1017 sg->offset = sg->offset * (*bpw / 8); 1018 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, 1019 sg->offset); 1020 sg_dma_len(sg) = rem; 1021 } else if (i == (num - 1)) { 1022 sg->offset = size * (i - 1) + rem; 1023 sg->offset = sg->offset * (*bpw / 8); 1024 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1025 sg->offset); 1026 sg_dma_len(sg) = size; 1027 } else { 1028 sg->offset = size * i; 1029 sg->offset = sg->offset * (*bpw / 8); 1030 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1031 sg->offset); 1032 sg_dma_len(sg) = size; 1033 } 1034 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; 1035 } 1036 sg = dma->sg_rx_p; 1037 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg, 1038 num, DMA_DEV_TO_MEM, 1039 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1040 if (!desc_rx) { 1041 dev_err(&data->master->dev, 1042 "%s:dmaengine_prep_slave_sg Failed\n", __func__); 1043 return; 1044 } 1045 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); 1046 desc_rx->callback = pch_dma_rx_complete; 1047 desc_rx->callback_param = data; 1048 dma->nent = num; 1049 dma->desc_rx = desc_rx; 1050 1051 /* Calculate Tx parameter for DMA transmitting */ 1052 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) { 1053 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE; 1054 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) { 1055 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 1056 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head; 1057 } else { 1058 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 1059 rem = data->bpw_len % PCH_DMA_TRANS_SIZE + 1060 PCH_DMA_TRANS_SIZE - head; 1061 } 1062 size = PCH_DMA_TRANS_SIZE; 1063 } else { 1064 num = 1; 1065 size = data->bpw_len; 1066 rem = data->bpw_len; 1067 head = 0; 1068 } 1069 1070 dma->sg_tx_p = kmalloc_array(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC); 1071 if (!dma->sg_tx_p) 1072 return; 1073 1074 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ 1075 /* offset, length setting */ 1076 sg = dma->sg_tx_p; 1077 for (i = 0; i < num; i++, sg++) { 1078 if (i == 0) { 1079 sg->offset = 0; 1080 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head, 1081 sg->offset); 1082 sg_dma_len(sg) = size + head; 1083 } else if (i == (num - 1)) { 1084 sg->offset = head + size * i; 1085 sg->offset = sg->offset * (*bpw / 8); 1086 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, 1087 sg->offset); 1088 sg_dma_len(sg) = rem; 1089 } else { 1090 sg->offset = head + size * i; 1091 sg->offset = sg->offset * (*bpw / 8); 1092 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, 1093 sg->offset); 1094 sg_dma_len(sg) = size; 1095 } 1096 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; 1097 } 1098 sg = dma->sg_tx_p; 1099 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx, 1100 sg, num, DMA_MEM_TO_DEV, 1101 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1102 if (!desc_tx) { 1103 dev_err(&data->master->dev, 1104 "%s:dmaengine_prep_slave_sg Failed\n", __func__); 1105 return; 1106 } 1107 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); 1108 desc_tx->callback = NULL; 1109 desc_tx->callback_param = data; 1110 dma->nent = num; 1111 dma->desc_tx = desc_tx; 1112 1113 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__); 1114 1115 spin_lock_irqsave(&data->lock, flags); 1116 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 1117 desc_rx->tx_submit(desc_rx); 1118 desc_tx->tx_submit(desc_tx); 1119 spin_unlock_irqrestore(&data->lock, flags); 1120 1121 /* reset transfer complete flag */ 1122 data->transfer_complete = false; 1123} 1124 1125static void pch_spi_process_messages(struct work_struct *pwork) 1126{ 1127 struct spi_message *pmsg, *tmp; 1128 struct pch_spi_data *data; 1129 int bpw; 1130 1131 data = container_of(pwork, struct pch_spi_data, work); 1132 dev_dbg(&data->master->dev, "%s data initialized\n", __func__); 1133 1134 spin_lock(&data->lock); 1135 /* check if suspend has been initiated;if yes flush queue */ 1136 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { 1137 dev_dbg(&data->master->dev, 1138 "%s suspend/remove initiated, flushing queue\n", __func__); 1139 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 1140 pmsg->status = -EIO; 1141 1142 if (pmsg->complete) { 1143 spin_unlock(&data->lock); 1144 pmsg->complete(pmsg->context); 1145 spin_lock(&data->lock); 1146 } 1147 1148 /* delete from queue */ 1149 list_del_init(&pmsg->queue); 1150 } 1151 1152 spin_unlock(&data->lock); 1153 return; 1154 } 1155 1156 data->bcurrent_msg_processing = true; 1157 dev_dbg(&data->master->dev, 1158 "%s Set data->bcurrent_msg_processing= true\n", __func__); 1159 1160 /* Get the message from the queue and delete it from there. */ 1161 data->current_msg = list_entry(data->queue.next, struct spi_message, 1162 queue); 1163 1164 list_del_init(&data->current_msg->queue); 1165 1166 data->current_msg->status = 0; 1167 1168 pch_spi_select_chip(data, data->current_msg->spi); 1169 1170 spin_unlock(&data->lock); 1171 1172 if (data->use_dma) 1173 pch_spi_request_dma(data, 1174 data->current_msg->spi->bits_per_word); 1175 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); 1176 do { 1177 int cnt; 1178 /* If we are already processing a message get the next 1179 transfer structure from the message otherwise retrieve 1180 the 1st transfer request from the message. */ 1181 spin_lock(&data->lock); 1182 if (data->cur_trans == NULL) { 1183 data->cur_trans = 1184 list_entry(data->current_msg->transfers.next, 1185 struct spi_transfer, transfer_list); 1186 dev_dbg(&data->master->dev, 1187 "%s :Getting 1st transfer message\n", 1188 __func__); 1189 } else { 1190 data->cur_trans = 1191 list_entry(data->cur_trans->transfer_list.next, 1192 struct spi_transfer, transfer_list); 1193 dev_dbg(&data->master->dev, 1194 "%s :Getting next transfer message\n", 1195 __func__); 1196 } 1197 spin_unlock(&data->lock); 1198 1199 if (!data->cur_trans->len) 1200 goto out; 1201 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1; 1202 data->save_total_len = data->cur_trans->len; 1203 if (data->use_dma) { 1204 int i; 1205 char *save_rx_buf = data->cur_trans->rx_buf; 1206 for (i = 0; i < cnt; i ++) { 1207 pch_spi_handle_dma(data, &bpw); 1208 if (!pch_spi_start_transfer(data)) { 1209 data->transfer_complete = true; 1210 data->current_msg->status = -EIO; 1211 data->current_msg->complete 1212 (data->current_msg->context); 1213 data->bcurrent_msg_processing = false; 1214 data->current_msg = NULL; 1215 data->cur_trans = NULL; 1216 goto out; 1217 } 1218 pch_spi_copy_rx_data_for_dma(data, bpw); 1219 } 1220 data->cur_trans->rx_buf = save_rx_buf; 1221 } else { 1222 pch_spi_set_tx(data, &bpw); 1223 pch_spi_set_ir(data); 1224 pch_spi_copy_rx_data(data, bpw); 1225 kfree(data->pkt_rx_buff); 1226 data->pkt_rx_buff = NULL; 1227 kfree(data->pkt_tx_buff); 1228 data->pkt_tx_buff = NULL; 1229 } 1230 /* increment message count */ 1231 data->cur_trans->len = data->save_total_len; 1232 data->current_msg->actual_length += data->cur_trans->len; 1233 1234 dev_dbg(&data->master->dev, 1235 "%s:data->current_msg->actual_length=%d\n", 1236 __func__, data->current_msg->actual_length); 1237 1238 spi_transfer_delay_exec(data->cur_trans); 1239 1240 spin_lock(&data->lock); 1241 1242 /* No more transfer in this message. */ 1243 if ((data->cur_trans->transfer_list.next) == 1244 &(data->current_msg->transfers)) { 1245 pch_spi_nomore_transfer(data); 1246 } 1247 1248 spin_unlock(&data->lock); 1249 1250 } while (data->cur_trans != NULL); 1251 1252out: 1253 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); 1254 if (data->use_dma) 1255 pch_spi_release_dma(data); 1256} 1257 1258static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, 1259 struct pch_spi_data *data) 1260{ 1261 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1262 1263 flush_work(&data->work); 1264} 1265 1266static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, 1267 struct pch_spi_data *data) 1268{ 1269 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1270 1271 /* reset PCH SPI h/w */ 1272 pch_spi_reset(data->master); 1273 dev_dbg(&board_dat->pdev->dev, 1274 "%s pch_spi_reset invoked successfully\n", __func__); 1275 1276 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); 1277 1278 return 0; 1279} 1280 1281static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, 1282 struct pch_spi_data *data) 1283{ 1284 struct pch_spi_dma_ctrl *dma; 1285 1286 dma = &data->dma; 1287 if (dma->tx_buf_dma) 1288 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1289 dma->tx_buf_virt, dma->tx_buf_dma); 1290 if (dma->rx_buf_dma) 1291 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1292 dma->rx_buf_virt, dma->rx_buf_dma); 1293} 1294 1295static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, 1296 struct pch_spi_data *data) 1297{ 1298 struct pch_spi_dma_ctrl *dma; 1299 int ret; 1300 1301 dma = &data->dma; 1302 ret = 0; 1303 /* Get Consistent memory for Tx DMA */ 1304 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1305 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); 1306 if (!dma->tx_buf_virt) 1307 ret = -ENOMEM; 1308 1309 /* Get Consistent memory for Rx DMA */ 1310 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1311 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); 1312 if (!dma->rx_buf_virt) 1313 ret = -ENOMEM; 1314 1315 return ret; 1316} 1317 1318static int pch_spi_pd_probe(struct platform_device *plat_dev) 1319{ 1320 int ret; 1321 struct spi_master *master; 1322 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1323 struct pch_spi_data *data; 1324 1325 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); 1326 1327 master = spi_alloc_master(&board_dat->pdev->dev, 1328 sizeof(struct pch_spi_data)); 1329 if (!master) { 1330 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", 1331 plat_dev->id); 1332 return -ENOMEM; 1333 } 1334 1335 data = spi_master_get_devdata(master); 1336 data->master = master; 1337 1338 platform_set_drvdata(plat_dev, data); 1339 1340 /* baseaddress + address offset) */ 1341 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + 1342 PCH_ADDRESS_SIZE * plat_dev->id; 1343 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0); 1344 if (!data->io_remap_addr) { 1345 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); 1346 ret = -ENOMEM; 1347 goto err_pci_iomap; 1348 } 1349 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id; 1350 1351 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", 1352 plat_dev->id, data->io_remap_addr); 1353 1354 /* initialize members of SPI master */ 1355 master->num_chipselect = PCH_MAX_CS; 1356 master->transfer = pch_spi_transfer; 1357 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1358 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 1359 master->max_speed_hz = PCH_MAX_BAUDRATE; 1360 1361 data->board_dat = board_dat; 1362 data->plat_dev = plat_dev; 1363 data->n_curnt_chip = 255; 1364 data->status = STATUS_RUNNING; 1365 data->ch = plat_dev->id; 1366 data->use_dma = use_dma; 1367 1368 INIT_LIST_HEAD(&data->queue); 1369 spin_lock_init(&data->lock); 1370 INIT_WORK(&data->work, pch_spi_process_messages); 1371 init_waitqueue_head(&data->wait); 1372 1373 ret = pch_spi_get_resources(board_dat, data); 1374 if (ret) { 1375 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); 1376 goto err_spi_get_resources; 1377 } 1378 1379 ret = request_irq(board_dat->pdev->irq, pch_spi_handler, 1380 IRQF_SHARED, KBUILD_MODNAME, data); 1381 if (ret) { 1382 dev_err(&plat_dev->dev, 1383 "%s request_irq failed\n", __func__); 1384 goto err_request_irq; 1385 } 1386 data->irq_reg_sts = true; 1387 1388 pch_spi_set_master_mode(master); 1389 1390 if (use_dma) { 1391 dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); 1392 ret = pch_alloc_dma_buf(board_dat, data); 1393 if (ret) 1394 goto err_spi_register_master; 1395 } 1396 1397 ret = spi_register_master(master); 1398 if (ret != 0) { 1399 dev_err(&plat_dev->dev, 1400 "%s spi_register_master FAILED\n", __func__); 1401 goto err_spi_register_master; 1402 } 1403 1404 return 0; 1405 1406err_spi_register_master: 1407 pch_free_dma_buf(board_dat, data); 1408 free_irq(board_dat->pdev->irq, data); 1409err_request_irq: 1410 pch_spi_free_resources(board_dat, data); 1411err_spi_get_resources: 1412 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1413err_pci_iomap: 1414 spi_master_put(master); 1415 1416 return ret; 1417} 1418 1419static int pch_spi_pd_remove(struct platform_device *plat_dev) 1420{ 1421 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1422 struct pch_spi_data *data = platform_get_drvdata(plat_dev); 1423 int count; 1424 unsigned long flags; 1425 1426 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", 1427 __func__, plat_dev->id, board_dat->pdev->irq); 1428 1429 if (use_dma) 1430 pch_free_dma_buf(board_dat, data); 1431 1432 /* check for any pending messages; no action is taken if the queue 1433 * is still full; but at least we tried. Unload anyway */ 1434 count = 500; 1435 spin_lock_irqsave(&data->lock, flags); 1436 data->status = STATUS_EXITING; 1437 while ((list_empty(&data->queue) == 0) && --count) { 1438 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", 1439 __func__); 1440 spin_unlock_irqrestore(&data->lock, flags); 1441 msleep(PCH_SLEEP_TIME); 1442 spin_lock_irqsave(&data->lock, flags); 1443 } 1444 spin_unlock_irqrestore(&data->lock, flags); 1445 1446 pch_spi_free_resources(board_dat, data); 1447 /* disable interrupts & free IRQ */ 1448 if (data->irq_reg_sts) { 1449 /* disable interrupts */ 1450 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1451 data->irq_reg_sts = false; 1452 free_irq(board_dat->pdev->irq, data); 1453 } 1454 1455 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1456 spi_unregister_master(data->master); 1457 1458 return 0; 1459} 1460#ifdef CONFIG_PM 1461static int pch_spi_pd_suspend(struct platform_device *pd_dev, 1462 pm_message_t state) 1463{ 1464 u8 count; 1465 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1466 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1467 1468 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); 1469 1470 if (!board_dat) { 1471 dev_err(&pd_dev->dev, 1472 "%s pci_get_drvdata returned NULL\n", __func__); 1473 return -EFAULT; 1474 } 1475 1476 /* check if the current message is processed: 1477 Only after thats done the transfer will be suspended */ 1478 count = 255; 1479 while ((--count) > 0) { 1480 if (!(data->bcurrent_msg_processing)) 1481 break; 1482 msleep(PCH_SLEEP_TIME); 1483 } 1484 1485 /* Free IRQ */ 1486 if (data->irq_reg_sts) { 1487 /* disable all interrupts */ 1488 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1489 pch_spi_reset(data->master); 1490 free_irq(board_dat->pdev->irq, data); 1491 1492 data->irq_reg_sts = false; 1493 dev_dbg(&pd_dev->dev, 1494 "%s free_irq invoked successfully.\n", __func__); 1495 } 1496 1497 return 0; 1498} 1499 1500static int pch_spi_pd_resume(struct platform_device *pd_dev) 1501{ 1502 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1503 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1504 int retval; 1505 1506 if (!board_dat) { 1507 dev_err(&pd_dev->dev, 1508 "%s pci_get_drvdata returned NULL\n", __func__); 1509 return -EFAULT; 1510 } 1511 1512 if (!data->irq_reg_sts) { 1513 /* register IRQ */ 1514 retval = request_irq(board_dat->pdev->irq, pch_spi_handler, 1515 IRQF_SHARED, KBUILD_MODNAME, data); 1516 if (retval < 0) { 1517 dev_err(&pd_dev->dev, 1518 "%s request_irq failed\n", __func__); 1519 return retval; 1520 } 1521 1522 /* reset PCH SPI h/w */ 1523 pch_spi_reset(data->master); 1524 pch_spi_set_master_mode(data->master); 1525 data->irq_reg_sts = true; 1526 } 1527 return 0; 1528} 1529#else 1530#define pch_spi_pd_suspend NULL 1531#define pch_spi_pd_resume NULL 1532#endif 1533 1534static struct platform_driver pch_spi_pd_driver = { 1535 .driver = { 1536 .name = "pch-spi", 1537 }, 1538 .probe = pch_spi_pd_probe, 1539 .remove = pch_spi_pd_remove, 1540 .suspend = pch_spi_pd_suspend, 1541 .resume = pch_spi_pd_resume 1542}; 1543 1544static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1545{ 1546 struct pch_spi_board_data *board_dat; 1547 struct platform_device *pd_dev = NULL; 1548 int retval; 1549 int i; 1550 struct pch_pd_dev_save *pd_dev_save; 1551 1552 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL); 1553 if (!pd_dev_save) 1554 return -ENOMEM; 1555 1556 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL); 1557 if (!board_dat) { 1558 retval = -ENOMEM; 1559 goto err_no_mem; 1560 } 1561 1562 retval = pci_request_regions(pdev, KBUILD_MODNAME); 1563 if (retval) { 1564 dev_err(&pdev->dev, "%s request_region failed\n", __func__); 1565 goto pci_request_regions; 1566 } 1567 1568 board_dat->pdev = pdev; 1569 board_dat->num = id->driver_data; 1570 pd_dev_save->num = id->driver_data; 1571 pd_dev_save->board_dat = board_dat; 1572 1573 retval = pci_enable_device(pdev); 1574 if (retval) { 1575 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); 1576 goto pci_enable_device; 1577 } 1578 1579 for (i = 0; i < board_dat->num; i++) { 1580 pd_dev = platform_device_alloc("pch-spi", i); 1581 if (!pd_dev) { 1582 dev_err(&pdev->dev, "platform_device_alloc failed\n"); 1583 retval = -ENOMEM; 1584 goto err_platform_device; 1585 } 1586 pd_dev_save->pd_save[i] = pd_dev; 1587 pd_dev->dev.parent = &pdev->dev; 1588 1589 retval = platform_device_add_data(pd_dev, board_dat, 1590 sizeof(*board_dat)); 1591 if (retval) { 1592 dev_err(&pdev->dev, 1593 "platform_device_add_data failed\n"); 1594 platform_device_put(pd_dev); 1595 goto err_platform_device; 1596 } 1597 1598 retval = platform_device_add(pd_dev); 1599 if (retval) { 1600 dev_err(&pdev->dev, "platform_device_add failed\n"); 1601 platform_device_put(pd_dev); 1602 goto err_platform_device; 1603 } 1604 } 1605 1606 pci_set_drvdata(pdev, pd_dev_save); 1607 1608 return 0; 1609 1610err_platform_device: 1611 while (--i >= 0) 1612 platform_device_unregister(pd_dev_save->pd_save[i]); 1613 pci_disable_device(pdev); 1614pci_enable_device: 1615 pci_release_regions(pdev); 1616pci_request_regions: 1617 kfree(board_dat); 1618err_no_mem: 1619 kfree(pd_dev_save); 1620 1621 return retval; 1622} 1623 1624static void pch_spi_remove(struct pci_dev *pdev) 1625{ 1626 int i; 1627 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1628 1629 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); 1630 1631 for (i = 0; i < pd_dev_save->num; i++) 1632 platform_device_unregister(pd_dev_save->pd_save[i]); 1633 1634 pci_disable_device(pdev); 1635 pci_release_regions(pdev); 1636 kfree(pd_dev_save->board_dat); 1637 kfree(pd_dev_save); 1638} 1639 1640static int __maybe_unused pch_spi_suspend(struct device *dev) 1641{ 1642 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev); 1643 1644 dev_dbg(dev, "%s ENTRY\n", __func__); 1645 1646 pd_dev_save->board_dat->suspend_sts = true; 1647 1648 return 0; 1649} 1650 1651static int __maybe_unused pch_spi_resume(struct device *dev) 1652{ 1653 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev); 1654 1655 dev_dbg(dev, "%s ENTRY\n", __func__); 1656 1657 /* set suspend status to false */ 1658 pd_dev_save->board_dat->suspend_sts = false; 1659 1660 return 0; 1661} 1662 1663static SIMPLE_DEV_PM_OPS(pch_spi_pm_ops, pch_spi_suspend, pch_spi_resume); 1664 1665static struct pci_driver pch_spi_pcidev_driver = { 1666 .name = "pch_spi", 1667 .id_table = pch_spi_pcidev_id, 1668 .probe = pch_spi_probe, 1669 .remove = pch_spi_remove, 1670 .driver.pm = &pch_spi_pm_ops, 1671}; 1672 1673static int __init pch_spi_init(void) 1674{ 1675 int ret; 1676 ret = platform_driver_register(&pch_spi_pd_driver); 1677 if (ret) 1678 return ret; 1679 1680 ret = pci_register_driver(&pch_spi_pcidev_driver); 1681 if (ret) { 1682 platform_driver_unregister(&pch_spi_pd_driver); 1683 return ret; 1684 } 1685 1686 return 0; 1687} 1688module_init(pch_spi_init); 1689 1690static void __exit pch_spi_exit(void) 1691{ 1692 pci_unregister_driver(&pch_spi_pcidev_driver); 1693 platform_driver_unregister(&pch_spi_pd_driver); 1694} 1695module_exit(pch_spi_exit); 1696 1697module_param(use_dma, int, 0644); 1698MODULE_PARM_DESC(use_dma, 1699 "to use DMA for data transfers pass 1 else 0; default 1"); 1700 1701MODULE_LICENSE("GPL"); 1702MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); 1703MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id); 1704 1705