1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright (c) 2009 Samsung Electronics Co., Ltd. 4// Jaswinder Singh <jassi.brar@samsung.com> 5 6#include <linux/init.h> 7#include <linux/module.h> 8#include <linux/interrupt.h> 9#include <linux/delay.h> 10#include <linux/clk.h> 11#include <linux/dma-mapping.h> 12#include <linux/dmaengine.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/spi/spi.h> 16#include <linux/gpio.h> 17#include <linux/of.h> 18#include <linux/of_gpio.h> 19 20#include <linux/platform_data/spi-s3c64xx.h> 21 22#define MAX_SPI_PORTS 6 23#define S3C64XX_SPI_QUIRK_POLL (1 << 0) 24#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 25#define AUTOSUSPEND_TIMEOUT 2000 26 27/* Registers and bit-fields */ 28 29#define S3C64XX_SPI_CH_CFG 0x00 30#define S3C64XX_SPI_CLK_CFG 0x04 31#define S3C64XX_SPI_MODE_CFG 0x08 32#define S3C64XX_SPI_CS_REG 0x0C 33#define S3C64XX_SPI_INT_EN 0x10 34#define S3C64XX_SPI_STATUS 0x14 35#define S3C64XX_SPI_TX_DATA 0x18 36#define S3C64XX_SPI_RX_DATA 0x1C 37#define S3C64XX_SPI_PACKET_CNT 0x20 38#define S3C64XX_SPI_PENDING_CLR 0x24 39#define S3C64XX_SPI_SWAP_CFG 0x28 40#define S3C64XX_SPI_FB_CLK 0x2C 41 42#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 43#define S3C64XX_SPI_CH_SW_RST (1<<5) 44#define S3C64XX_SPI_CH_SLAVE (1<<4) 45#define S3C64XX_SPI_CPOL_L (1<<3) 46#define S3C64XX_SPI_CPHA_B (1<<2) 47#define S3C64XX_SPI_CH_RXCH_ON (1<<1) 48#define S3C64XX_SPI_CH_TXCH_ON (1<<0) 49 50#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 51#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 52#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 53#define S3C64XX_SPI_PSR_MASK 0xff 54 55#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 56#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 57#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 58#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 59#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 60#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 61#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 62#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 63#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 64#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 65#define S3C64XX_SPI_MODE_4BURST (1<<0) 66 67#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 68#define S3C64XX_SPI_CS_AUTO (1<<1) 69#define S3C64XX_SPI_CS_SIG_INACT (1<<0) 70 71#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 72#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 73#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 74#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 75#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 76#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 77#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 78 79#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 80#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 81#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 82#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 83#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 84#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 85 86#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 87#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) 88 89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 93#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 94 95#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 96#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 97#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 98#define S3C64XX_SPI_SWAP_RX_EN (1<<4) 99#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 100#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 101#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 102#define S3C64XX_SPI_SWAP_TX_EN (1<<0) 103 104#define S3C64XX_SPI_FBCLK_MSK (3<<0) 105 106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 111 FIFO_LVL_MASK(i)) 112 113#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 114#define S3C64XX_SPI_TRAILCNT_OFF 19 115 116#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 117 118#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 119#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 120 121#define RXBUSY (1<<2) 122#define TXBUSY (1<<3) 123 124struct s3c64xx_spi_dma_data { 125 struct dma_chan *ch; 126 dma_cookie_t cookie; 127 enum dma_transfer_direction direction; 128}; 129 130/** 131 * struct s3c64xx_spi_info - SPI Controller hardware info 132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 135 * @quirks: Bitmask of known quirks 136 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 137 * @clk_from_cmu: True, if the controller does not include a clock mux and 138 * prescaler unit. 139 * @clk_ioclk: True if clock is present on this device 140 * 141 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 142 * differ in some aspects such as the size of the fifo and spi bus clock 143 * setup. Such differences are specified to the driver using this structure 144 * which is provided as driver data to the driver. 145 */ 146struct s3c64xx_spi_port_config { 147 int fifo_lvl_mask[MAX_SPI_PORTS]; 148 int rx_lvl_offset; 149 int tx_st_done; 150 int quirks; 151 bool high_speed; 152 bool clk_from_cmu; 153 bool clk_ioclk; 154}; 155 156/** 157 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 158 * @clk: Pointer to the spi clock. 159 * @src_clk: Pointer to the clock used to generate SPI signals. 160 * @ioclk: Pointer to the i/o clock between master and slave 161 * @pdev: Pointer to device's platform device data 162 * @master: Pointer to the SPI Protocol master. 163 * @cntrlr_info: Platform specific data for the controller this driver manages. 164 * @lock: Controller specific lock. 165 * @state: Set of FLAGS to indicate status. 166 * @sfr_start: BUS address of SPI controller regs. 167 * @regs: Pointer to ioremap'ed controller registers. 168 * @xfer_completion: To indicate completion of xfer task. 169 * @cur_mode: Stores the active configuration of the controller. 170 * @cur_bpw: Stores the active bits per word settings. 171 * @cur_speed: Current clock speed 172 * @rx_dma: Local receive DMA data (e.g. chan and direction) 173 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 174 * @port_conf: Local SPI port configuartion data 175 * @port_id: Port identification number 176 */ 177struct s3c64xx_spi_driver_data { 178 void __iomem *regs; 179 struct clk *clk; 180 struct clk *src_clk; 181 struct clk *ioclk; 182 struct platform_device *pdev; 183 struct spi_master *master; 184 struct s3c64xx_spi_info *cntrlr_info; 185 spinlock_t lock; 186 unsigned long sfr_start; 187 struct completion xfer_completion; 188 unsigned state; 189 unsigned cur_mode, cur_bpw; 190 unsigned cur_speed; 191 struct s3c64xx_spi_dma_data rx_dma; 192 struct s3c64xx_spi_dma_data tx_dma; 193 struct s3c64xx_spi_port_config *port_conf; 194 unsigned int port_id; 195}; 196 197static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 198{ 199 void __iomem *regs = sdd->regs; 200 unsigned long loops; 201 u32 val; 202 203 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 204 205 val = readl(regs + S3C64XX_SPI_CH_CFG); 206 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 207 writel(val, regs + S3C64XX_SPI_CH_CFG); 208 209 val = readl(regs + S3C64XX_SPI_CH_CFG); 210 val |= S3C64XX_SPI_CH_SW_RST; 211 val &= ~S3C64XX_SPI_CH_HS_EN; 212 writel(val, regs + S3C64XX_SPI_CH_CFG); 213 214 /* Flush TxFIFO*/ 215 loops = msecs_to_loops(1); 216 do { 217 val = readl(regs + S3C64XX_SPI_STATUS); 218 } while (TX_FIFO_LVL(val, sdd) && loops--); 219 220 if (loops == 0) 221 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 222 223 /* Flush RxFIFO*/ 224 loops = msecs_to_loops(1); 225 do { 226 val = readl(regs + S3C64XX_SPI_STATUS); 227 if (RX_FIFO_LVL(val, sdd)) 228 readl(regs + S3C64XX_SPI_RX_DATA); 229 else 230 break; 231 } while (loops--); 232 233 if (loops == 0) 234 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 235 236 val = readl(regs + S3C64XX_SPI_CH_CFG); 237 val &= ~S3C64XX_SPI_CH_SW_RST; 238 writel(val, regs + S3C64XX_SPI_CH_CFG); 239 240 val = readl(regs + S3C64XX_SPI_MODE_CFG); 241 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 242 writel(val, regs + S3C64XX_SPI_MODE_CFG); 243} 244 245static void s3c64xx_spi_dmacb(void *data) 246{ 247 struct s3c64xx_spi_driver_data *sdd; 248 struct s3c64xx_spi_dma_data *dma = data; 249 unsigned long flags; 250 251 if (dma->direction == DMA_DEV_TO_MEM) 252 sdd = container_of(data, 253 struct s3c64xx_spi_driver_data, rx_dma); 254 else 255 sdd = container_of(data, 256 struct s3c64xx_spi_driver_data, tx_dma); 257 258 spin_lock_irqsave(&sdd->lock, flags); 259 260 if (dma->direction == DMA_DEV_TO_MEM) { 261 sdd->state &= ~RXBUSY; 262 if (!(sdd->state & TXBUSY)) 263 complete(&sdd->xfer_completion); 264 } else { 265 sdd->state &= ~TXBUSY; 266 if (!(sdd->state & RXBUSY)) 267 complete(&sdd->xfer_completion); 268 } 269 270 spin_unlock_irqrestore(&sdd->lock, flags); 271} 272 273static int prepare_dma(struct s3c64xx_spi_dma_data *dma, 274 struct sg_table *sgt) 275{ 276 struct s3c64xx_spi_driver_data *sdd; 277 struct dma_slave_config config; 278 struct dma_async_tx_descriptor *desc; 279 int ret; 280 281 memset(&config, 0, sizeof(config)); 282 283 if (dma->direction == DMA_DEV_TO_MEM) { 284 sdd = container_of((void *)dma, 285 struct s3c64xx_spi_driver_data, rx_dma); 286 config.direction = dma->direction; 287 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 288 config.src_addr_width = sdd->cur_bpw / 8; 289 config.src_maxburst = 1; 290 dmaengine_slave_config(dma->ch, &config); 291 } else { 292 sdd = container_of((void *)dma, 293 struct s3c64xx_spi_driver_data, tx_dma); 294 config.direction = dma->direction; 295 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 296 config.dst_addr_width = sdd->cur_bpw / 8; 297 config.dst_maxburst = 1; 298 dmaengine_slave_config(dma->ch, &config); 299 } 300 301 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 302 dma->direction, DMA_PREP_INTERRUPT); 303 if (!desc) { 304 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 305 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 306 return -ENOMEM; 307 } 308 309 desc->callback = s3c64xx_spi_dmacb; 310 desc->callback_param = dma; 311 312 dma->cookie = dmaengine_submit(desc); 313 ret = dma_submit_error(dma->cookie); 314 if (ret) { 315 dev_err(&sdd->pdev->dev, "DMA submission failed"); 316 return -EIO; 317 } 318 319 dma_async_issue_pending(dma->ch); 320 return 0; 321} 322 323static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 324{ 325 struct s3c64xx_spi_driver_data *sdd = 326 spi_master_get_devdata(spi->master); 327 328 if (sdd->cntrlr_info->no_cs) 329 return; 330 331 if (enable) { 332 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 333 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 334 } else { 335 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 336 337 ssel |= (S3C64XX_SPI_CS_AUTO | 338 S3C64XX_SPI_CS_NSC_CNT_2); 339 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 340 } 341 } else { 342 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 343 writel(S3C64XX_SPI_CS_SIG_INACT, 344 sdd->regs + S3C64XX_SPI_CS_REG); 345 } 346} 347 348static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 349{ 350 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 351 352 if (is_polling(sdd)) 353 return 0; 354 355 spi->dma_rx = sdd->rx_dma.ch; 356 spi->dma_tx = sdd->tx_dma.ch; 357 358 return 0; 359} 360 361static bool s3c64xx_spi_can_dma(struct spi_master *master, 362 struct spi_device *spi, 363 struct spi_transfer *xfer) 364{ 365 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 366 367 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 368} 369 370static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 371 struct spi_transfer *xfer, int dma_mode) 372{ 373 void __iomem *regs = sdd->regs; 374 u32 modecfg, chcfg; 375 int ret = 0; 376 377 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 378 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 379 380 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 381 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 382 383 if (dma_mode) { 384 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 385 } else { 386 /* Always shift in data in FIFO, even if xfer is Tx only, 387 * this helps setting PCKT_CNT value for generating clocks 388 * as exactly needed. 389 */ 390 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 391 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 392 | S3C64XX_SPI_PACKET_CNT_EN, 393 regs + S3C64XX_SPI_PACKET_CNT); 394 } 395 396 if (xfer->tx_buf != NULL) { 397 sdd->state |= TXBUSY; 398 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 399 if (dma_mode) { 400 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 401 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 402 } else { 403 switch (sdd->cur_bpw) { 404 case 32: 405 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 406 xfer->tx_buf, xfer->len / 4); 407 break; 408 case 16: 409 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 410 xfer->tx_buf, xfer->len / 2); 411 break; 412 default: 413 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 414 xfer->tx_buf, xfer->len); 415 break; 416 } 417 } 418 } 419 420 if (xfer->rx_buf != NULL) { 421 sdd->state |= RXBUSY; 422 423 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 424 && !(sdd->cur_mode & SPI_CPHA)) 425 chcfg |= S3C64XX_SPI_CH_HS_EN; 426 427 if (dma_mode) { 428 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 429 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 430 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 431 | S3C64XX_SPI_PACKET_CNT_EN, 432 regs + S3C64XX_SPI_PACKET_CNT); 433 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 434 } 435 } 436 437 if (ret) 438 return ret; 439 440 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 441 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 442 443 return 0; 444} 445 446static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 447 int timeout_ms) 448{ 449 void __iomem *regs = sdd->regs; 450 unsigned long val = 1; 451 u32 status; 452 453 /* max fifo depth available */ 454 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 455 456 if (timeout_ms) 457 val = msecs_to_loops(timeout_ms); 458 459 do { 460 status = readl(regs + S3C64XX_SPI_STATUS); 461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 462 463 /* return the actual received data length */ 464 return RX_FIFO_LVL(status, sdd); 465} 466 467static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 468 struct spi_transfer *xfer) 469{ 470 void __iomem *regs = sdd->regs; 471 unsigned long val; 472 u32 status; 473 int ms; 474 475 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 476 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 477 ms += 30; /* some tolerance */ 478 ms = max(ms, 100); /* minimum timeout */ 479 480 val = msecs_to_jiffies(ms) + 10; 481 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 482 483 /* 484 * If the previous xfer was completed within timeout, then 485 * proceed further else return -EIO. 486 * DmaTx returns after simply writing data in the FIFO, 487 * w/o waiting for real transmission on the bus to finish. 488 * DmaRx returns only after Dma read data from FIFO which 489 * needs bus transmission to finish, so we don't worry if 490 * Xfer involved Rx(with or without Tx). 491 */ 492 if (val && !xfer->rx_buf) { 493 val = msecs_to_loops(10); 494 status = readl(regs + S3C64XX_SPI_STATUS); 495 while ((TX_FIFO_LVL(status, sdd) 496 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 497 && --val) { 498 cpu_relax(); 499 status = readl(regs + S3C64XX_SPI_STATUS); 500 } 501 502 } 503 504 /* If timed out while checking rx/tx status return error */ 505 if (!val) 506 return -EIO; 507 508 return 0; 509} 510 511static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 512 struct spi_transfer *xfer) 513{ 514 void __iomem *regs = sdd->regs; 515 unsigned long val; 516 u32 status; 517 int loops; 518 u32 cpy_len; 519 u8 *buf; 520 int ms; 521 522 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 523 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 524 ms += 10; /* some tolerance */ 525 526 val = msecs_to_loops(ms); 527 do { 528 status = readl(regs + S3C64XX_SPI_STATUS); 529 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 530 531 if (!val) 532 return -EIO; 533 534 /* If it was only Tx */ 535 if (!xfer->rx_buf) { 536 sdd->state &= ~TXBUSY; 537 return 0; 538 } 539 540 /* 541 * If the receive length is bigger than the controller fifo 542 * size, calculate the loops and read the fifo as many times. 543 * loops = length / max fifo size (calculated by using the 544 * fifo mask). 545 * For any size less than the fifo size the below code is 546 * executed atleast once. 547 */ 548 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 549 buf = xfer->rx_buf; 550 do { 551 /* wait for data to be received in the fifo */ 552 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 553 (loops ? ms : 0)); 554 555 switch (sdd->cur_bpw) { 556 case 32: 557 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 558 buf, cpy_len / 4); 559 break; 560 case 16: 561 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 562 buf, cpy_len / 2); 563 break; 564 default: 565 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 566 buf, cpy_len); 567 break; 568 } 569 570 buf = buf + cpy_len; 571 } while (loops--); 572 sdd->state &= ~RXBUSY; 573 574 return 0; 575} 576 577static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 578{ 579 void __iomem *regs = sdd->regs; 580 int ret; 581 u32 val; 582 583 /* Disable Clock */ 584 if (!sdd->port_conf->clk_from_cmu) { 585 val = readl(regs + S3C64XX_SPI_CLK_CFG); 586 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 587 writel(val, regs + S3C64XX_SPI_CLK_CFG); 588 } 589 590 /* Set Polarity and Phase */ 591 val = readl(regs + S3C64XX_SPI_CH_CFG); 592 val &= ~(S3C64XX_SPI_CH_SLAVE | 593 S3C64XX_SPI_CPOL_L | 594 S3C64XX_SPI_CPHA_B); 595 596 if (sdd->cur_mode & SPI_CPOL) 597 val |= S3C64XX_SPI_CPOL_L; 598 599 if (sdd->cur_mode & SPI_CPHA) 600 val |= S3C64XX_SPI_CPHA_B; 601 602 writel(val, regs + S3C64XX_SPI_CH_CFG); 603 604 /* Set Channel & DMA Mode */ 605 val = readl(regs + S3C64XX_SPI_MODE_CFG); 606 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 607 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 608 609 switch (sdd->cur_bpw) { 610 case 32: 611 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 612 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 613 break; 614 case 16: 615 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 616 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 617 break; 618 default: 619 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 620 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 621 break; 622 } 623 624 writel(val, regs + S3C64XX_SPI_MODE_CFG); 625 626 if (sdd->port_conf->clk_from_cmu) { 627 /* The src_clk clock is divided internally by 2 */ 628 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 629 if (ret) 630 return ret; 631 sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; 632 } else { 633 /* Configure Clock */ 634 val = readl(regs + S3C64XX_SPI_CLK_CFG); 635 val &= ~S3C64XX_SPI_PSR_MASK; 636 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 637 & S3C64XX_SPI_PSR_MASK); 638 writel(val, regs + S3C64XX_SPI_CLK_CFG); 639 640 /* Enable Clock */ 641 val = readl(regs + S3C64XX_SPI_CLK_CFG); 642 val |= S3C64XX_SPI_ENCLK_ENABLE; 643 writel(val, regs + S3C64XX_SPI_CLK_CFG); 644 } 645 646 return 0; 647} 648 649#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 650 651static int s3c64xx_spi_prepare_message(struct spi_master *master, 652 struct spi_message *msg) 653{ 654 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 655 struct spi_device *spi = msg->spi; 656 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 657 658 /* Configure feedback delay */ 659 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 660 661 return 0; 662} 663 664static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) 665{ 666 struct spi_controller *ctlr = spi->controller; 667 668 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; 669} 670 671static int s3c64xx_spi_transfer_one(struct spi_master *master, 672 struct spi_device *spi, 673 struct spi_transfer *xfer) 674{ 675 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 676 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1; 677 const void *tx_buf = NULL; 678 void *rx_buf = NULL; 679 int target_len = 0, origin_len = 0; 680 int use_dma = 0; 681 int status; 682 u32 speed; 683 u8 bpw; 684 unsigned long flags; 685 686 reinit_completion(&sdd->xfer_completion); 687 688 /* Only BPW and Speed may change across transfers */ 689 bpw = xfer->bits_per_word; 690 speed = xfer->speed_hz; 691 692 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 693 sdd->cur_bpw = bpw; 694 sdd->cur_speed = speed; 695 sdd->cur_mode = spi->mode; 696 status = s3c64xx_spi_config(sdd); 697 if (status) 698 return status; 699 } 700 701 if (!is_polling(sdd) && (xfer->len > fifo_len) && 702 sdd->rx_dma.ch && sdd->tx_dma.ch) { 703 use_dma = 1; 704 705 } else if (is_polling(sdd) && xfer->len > fifo_len) { 706 tx_buf = xfer->tx_buf; 707 rx_buf = xfer->rx_buf; 708 origin_len = xfer->len; 709 710 target_len = xfer->len; 711 if (xfer->len > fifo_len) 712 xfer->len = fifo_len; 713 } 714 715 do { 716 spin_lock_irqsave(&sdd->lock, flags); 717 718 /* Pending only which is to be done */ 719 sdd->state &= ~RXBUSY; 720 sdd->state &= ~TXBUSY; 721 722 /* Start the signals */ 723 s3c64xx_spi_set_cs(spi, true); 724 725 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 726 727 spin_unlock_irqrestore(&sdd->lock, flags); 728 729 if (status) { 730 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 731 break; 732 } 733 734 if (use_dma) 735 status = s3c64xx_wait_for_dma(sdd, xfer); 736 else 737 status = s3c64xx_wait_for_pio(sdd, xfer); 738 739 if (status) { 740 dev_err(&spi->dev, 741 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 742 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 743 (sdd->state & RXBUSY) ? 'f' : 'p', 744 (sdd->state & TXBUSY) ? 'f' : 'p', 745 xfer->len, use_dma ? 1 : 0, status); 746 747 if (use_dma) { 748 struct dma_tx_state s; 749 750 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 751 dmaengine_pause(sdd->tx_dma.ch); 752 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 753 dmaengine_terminate_all(sdd->tx_dma.ch); 754 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 755 756 } 757 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 758 dmaengine_pause(sdd->rx_dma.ch); 759 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 760 dmaengine_terminate_all(sdd->rx_dma.ch); 761 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 762 } 763 } 764 } else { 765 s3c64xx_flush_fifo(sdd); 766 } 767 if (target_len > 0) { 768 target_len -= xfer->len; 769 770 if (xfer->tx_buf) 771 xfer->tx_buf += xfer->len; 772 773 if (xfer->rx_buf) 774 xfer->rx_buf += xfer->len; 775 776 if (target_len > fifo_len) 777 xfer->len = fifo_len; 778 else 779 xfer->len = target_len; 780 } 781 } while (target_len > 0); 782 783 if (origin_len) { 784 /* Restore original xfer buffers and length */ 785 xfer->tx_buf = tx_buf; 786 xfer->rx_buf = rx_buf; 787 xfer->len = origin_len; 788 } 789 790 return status; 791} 792 793static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 794 struct spi_device *spi) 795{ 796 struct s3c64xx_spi_csinfo *cs; 797 struct device_node *slave_np, *data_np = NULL; 798 u32 fb_delay = 0; 799 800 slave_np = spi->dev.of_node; 801 if (!slave_np) { 802 dev_err(&spi->dev, "device node not found\n"); 803 return ERR_PTR(-EINVAL); 804 } 805 806 data_np = of_get_child_by_name(slave_np, "controller-data"); 807 if (!data_np) { 808 dev_err(&spi->dev, "child node 'controller-data' not found\n"); 809 return ERR_PTR(-EINVAL); 810 } 811 812 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 813 if (!cs) { 814 of_node_put(data_np); 815 return ERR_PTR(-ENOMEM); 816 } 817 818 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 819 cs->fb_delay = fb_delay; 820 of_node_put(data_np); 821 return cs; 822} 823 824/* 825 * Here we only check the validity of requested configuration 826 * and save the configuration in a local data-structure. 827 * The controller is actually configured only just before we 828 * get a message to transfer. 829 */ 830static int s3c64xx_spi_setup(struct spi_device *spi) 831{ 832 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 833 struct s3c64xx_spi_driver_data *sdd; 834 int err; 835 836 sdd = spi_master_get_devdata(spi->master); 837 if (spi->dev.of_node) { 838 cs = s3c64xx_get_slave_ctrldata(spi); 839 spi->controller_data = cs; 840 } else if (cs) { 841 /* On non-DT platforms the SPI core will set spi->cs_gpio 842 * to -ENOENT. The GPIO pin used to drive the chip select 843 * is defined by using platform data so spi->cs_gpio value 844 * has to be override to have the proper GPIO pin number. 845 */ 846 spi->cs_gpio = cs->line; 847 } 848 849 if (IS_ERR_OR_NULL(cs)) { 850 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 851 return -ENODEV; 852 } 853 854 if (!spi_get_ctldata(spi)) { 855 if (gpio_is_valid(spi->cs_gpio)) { 856 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, 857 dev_name(&spi->dev)); 858 if (err) { 859 dev_err(&spi->dev, 860 "Failed to get /CS gpio [%d]: %d\n", 861 spi->cs_gpio, err); 862 goto err_gpio_req; 863 } 864 } 865 866 spi_set_ctldata(spi, cs); 867 } 868 869 pm_runtime_get_sync(&sdd->pdev->dev); 870 871 /* Check if we can provide the requested rate */ 872 if (!sdd->port_conf->clk_from_cmu) { 873 u32 psr, speed; 874 875 /* Max possible */ 876 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 877 878 if (spi->max_speed_hz > speed) 879 spi->max_speed_hz = speed; 880 881 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 882 psr &= S3C64XX_SPI_PSR_MASK; 883 if (psr == S3C64XX_SPI_PSR_MASK) 884 psr--; 885 886 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 887 if (spi->max_speed_hz < speed) { 888 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 889 psr++; 890 } else { 891 err = -EINVAL; 892 goto setup_exit; 893 } 894 } 895 896 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 897 if (spi->max_speed_hz >= speed) { 898 spi->max_speed_hz = speed; 899 } else { 900 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 901 spi->max_speed_hz); 902 err = -EINVAL; 903 goto setup_exit; 904 } 905 } 906 907 pm_runtime_mark_last_busy(&sdd->pdev->dev); 908 pm_runtime_put_autosuspend(&sdd->pdev->dev); 909 s3c64xx_spi_set_cs(spi, false); 910 911 return 0; 912 913setup_exit: 914 pm_runtime_mark_last_busy(&sdd->pdev->dev); 915 pm_runtime_put_autosuspend(&sdd->pdev->dev); 916 /* setup() returns with device de-selected */ 917 s3c64xx_spi_set_cs(spi, false); 918 919 if (gpio_is_valid(spi->cs_gpio)) 920 gpio_free(spi->cs_gpio); 921 spi_set_ctldata(spi, NULL); 922 923err_gpio_req: 924 if (spi->dev.of_node) 925 kfree(cs); 926 927 return err; 928} 929 930static void s3c64xx_spi_cleanup(struct spi_device *spi) 931{ 932 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 933 934 if (gpio_is_valid(spi->cs_gpio)) { 935 gpio_free(spi->cs_gpio); 936 if (spi->dev.of_node) 937 kfree(cs); 938 else { 939 /* On non-DT platforms, the SPI core sets 940 * spi->cs_gpio to -ENOENT and .setup() 941 * overrides it with the GPIO pin value 942 * passed using platform data. 943 */ 944 spi->cs_gpio = -ENOENT; 945 } 946 } 947 948 spi_set_ctldata(spi, NULL); 949} 950 951static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 952{ 953 struct s3c64xx_spi_driver_data *sdd = data; 954 struct spi_master *spi = sdd->master; 955 unsigned int val, clr = 0; 956 957 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 958 959 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 960 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 961 dev_err(&spi->dev, "RX overrun\n"); 962 } 963 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 964 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 965 dev_err(&spi->dev, "RX underrun\n"); 966 } 967 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 968 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 969 dev_err(&spi->dev, "TX overrun\n"); 970 } 971 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 972 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 973 dev_err(&spi->dev, "TX underrun\n"); 974 } 975 976 /* Clear the pending irq by setting and then clearing it */ 977 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 978 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 979 980 return IRQ_HANDLED; 981} 982 983static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 984{ 985 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 986 void __iomem *regs = sdd->regs; 987 unsigned int val; 988 989 sdd->cur_speed = 0; 990 991 if (sci->no_cs) 992 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 993 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 994 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 995 996 /* Disable Interrupts - we use Polling if not DMA mode */ 997 writel(0, regs + S3C64XX_SPI_INT_EN); 998 999 if (!sdd->port_conf->clk_from_cmu) 1000 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1001 regs + S3C64XX_SPI_CLK_CFG); 1002 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1003 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1004 1005 /* Clear any irq pending bits, should set and clear the bits */ 1006 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1007 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1008 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1009 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1010 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1011 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1012 1013 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1014 1015 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1016 val &= ~S3C64XX_SPI_MODE_4BURST; 1017 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1018 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1019 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1020 1021 s3c64xx_flush_fifo(sdd); 1022} 1023 1024#ifdef CONFIG_OF 1025static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1026{ 1027 struct s3c64xx_spi_info *sci; 1028 u32 temp; 1029 1030 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1031 if (!sci) 1032 return ERR_PTR(-ENOMEM); 1033 1034 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1035 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1036 sci->src_clk_nr = 0; 1037 } else { 1038 sci->src_clk_nr = temp; 1039 } 1040 1041 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1042 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1043 sci->num_cs = 1; 1044 } else { 1045 sci->num_cs = temp; 1046 } 1047 1048 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1049 1050 return sci; 1051} 1052#else 1053static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1054{ 1055 return dev_get_platdata(dev); 1056} 1057#endif 1058 1059static const struct of_device_id s3c64xx_spi_dt_match[]; 1060 1061static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1062 struct platform_device *pdev) 1063{ 1064#ifdef CONFIG_OF 1065 if (pdev->dev.of_node) { 1066 const struct of_device_id *match; 1067 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); 1068 return (struct s3c64xx_spi_port_config *)match->data; 1069 } 1070#endif 1071 return (struct s3c64xx_spi_port_config *) 1072 platform_get_device_id(pdev)->driver_data; 1073} 1074 1075static int s3c64xx_spi_probe(struct platform_device *pdev) 1076{ 1077 struct resource *mem_res; 1078 struct s3c64xx_spi_driver_data *sdd; 1079 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1080 struct spi_master *master; 1081 int ret, irq; 1082 char clk_name[16]; 1083 1084 if (!sci && pdev->dev.of_node) { 1085 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1086 if (IS_ERR(sci)) 1087 return PTR_ERR(sci); 1088 } 1089 1090 if (!sci) { 1091 dev_err(&pdev->dev, "platform_data missing!\n"); 1092 return -ENODEV; 1093 } 1094 1095 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1096 if (mem_res == NULL) { 1097 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1098 return -ENXIO; 1099 } 1100 1101 irq = platform_get_irq(pdev, 0); 1102 if (irq < 0) { 1103 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1104 return irq; 1105 } 1106 1107 master = spi_alloc_master(&pdev->dev, 1108 sizeof(struct s3c64xx_spi_driver_data)); 1109 if (master == NULL) { 1110 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1111 return -ENOMEM; 1112 } 1113 1114 platform_set_drvdata(pdev, master); 1115 1116 sdd = spi_master_get_devdata(master); 1117 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1118 sdd->master = master; 1119 sdd->cntrlr_info = sci; 1120 sdd->pdev = pdev; 1121 sdd->sfr_start = mem_res->start; 1122 if (pdev->dev.of_node) { 1123 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1124 if (ret < 0) { 1125 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1126 ret); 1127 goto err_deref_master; 1128 } 1129 sdd->port_id = ret; 1130 } else { 1131 sdd->port_id = pdev->id; 1132 } 1133 1134 sdd->cur_bpw = 8; 1135 1136 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1137 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1138 1139 master->dev.of_node = pdev->dev.of_node; 1140 master->bus_num = sdd->port_id; 1141 master->setup = s3c64xx_spi_setup; 1142 master->cleanup = s3c64xx_spi_cleanup; 1143 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1144 master->prepare_message = s3c64xx_spi_prepare_message; 1145 master->transfer_one = s3c64xx_spi_transfer_one; 1146 master->max_transfer_size = s3c64xx_spi_max_transfer_size; 1147 master->num_chipselect = sci->num_cs; 1148 master->dma_alignment = 8; 1149 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1150 SPI_BPW_MASK(8); 1151 /* the spi->mode bits understood by this driver: */ 1152 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1153 master->auto_runtime_pm = true; 1154 if (!is_polling(sdd)) 1155 master->can_dma = s3c64xx_spi_can_dma; 1156 1157 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1158 if (IS_ERR(sdd->regs)) { 1159 ret = PTR_ERR(sdd->regs); 1160 goto err_deref_master; 1161 } 1162 1163 if (sci->cfg_gpio && sci->cfg_gpio()) { 1164 dev_err(&pdev->dev, "Unable to config gpio\n"); 1165 ret = -EBUSY; 1166 goto err_deref_master; 1167 } 1168 1169 /* Setup clocks */ 1170 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1171 if (IS_ERR(sdd->clk)) { 1172 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1173 ret = PTR_ERR(sdd->clk); 1174 goto err_deref_master; 1175 } 1176 1177 ret = clk_prepare_enable(sdd->clk); 1178 if (ret) { 1179 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1180 goto err_deref_master; 1181 } 1182 1183 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1184 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1185 if (IS_ERR(sdd->src_clk)) { 1186 dev_err(&pdev->dev, 1187 "Unable to acquire clock '%s'\n", clk_name); 1188 ret = PTR_ERR(sdd->src_clk); 1189 goto err_disable_clk; 1190 } 1191 1192 ret = clk_prepare_enable(sdd->src_clk); 1193 if (ret) { 1194 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1195 goto err_disable_clk; 1196 } 1197 1198 if (sdd->port_conf->clk_ioclk) { 1199 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); 1200 if (IS_ERR(sdd->ioclk)) { 1201 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); 1202 ret = PTR_ERR(sdd->ioclk); 1203 goto err_disable_src_clk; 1204 } 1205 1206 ret = clk_prepare_enable(sdd->ioclk); 1207 if (ret) { 1208 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); 1209 goto err_disable_src_clk; 1210 } 1211 } 1212 1213 if (!is_polling(sdd)) { 1214 /* Acquire DMA channels */ 1215 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx"); 1216 if (IS_ERR(sdd->rx_dma.ch)) { 1217 dev_err(&pdev->dev, "Failed to get RX DMA channel\n"); 1218 ret = PTR_ERR(sdd->rx_dma.ch); 1219 goto err_disable_io_clk; 1220 } 1221 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx"); 1222 if (IS_ERR(sdd->tx_dma.ch)) { 1223 dev_err(&pdev->dev, "Failed to get TX DMA channel\n"); 1224 ret = PTR_ERR(sdd->tx_dma.ch); 1225 goto err_release_rx_dma; 1226 } 1227 } 1228 1229 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1230 pm_runtime_use_autosuspend(&pdev->dev); 1231 pm_runtime_set_active(&pdev->dev); 1232 pm_runtime_enable(&pdev->dev); 1233 pm_runtime_get_sync(&pdev->dev); 1234 1235 /* Setup Deufult Mode */ 1236 s3c64xx_spi_hwinit(sdd); 1237 1238 spin_lock_init(&sdd->lock); 1239 init_completion(&sdd->xfer_completion); 1240 1241 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1242 "spi-s3c64xx", sdd); 1243 if (ret != 0) { 1244 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1245 irq, ret); 1246 goto err_pm_put; 1247 } 1248 1249 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1250 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1251 sdd->regs + S3C64XX_SPI_INT_EN); 1252 1253 ret = devm_spi_register_master(&pdev->dev, master); 1254 if (ret != 0) { 1255 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1256 goto err_pm_put; 1257 } 1258 1259 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1260 sdd->port_id, master->num_chipselect); 1261 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1262 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); 1263 1264 pm_runtime_mark_last_busy(&pdev->dev); 1265 pm_runtime_put_autosuspend(&pdev->dev); 1266 1267 return 0; 1268 1269err_pm_put: 1270 pm_runtime_put_noidle(&pdev->dev); 1271 pm_runtime_disable(&pdev->dev); 1272 pm_runtime_set_suspended(&pdev->dev); 1273 1274 if (!is_polling(sdd)) 1275 dma_release_channel(sdd->tx_dma.ch); 1276err_release_rx_dma: 1277 if (!is_polling(sdd)) 1278 dma_release_channel(sdd->rx_dma.ch); 1279err_disable_io_clk: 1280 clk_disable_unprepare(sdd->ioclk); 1281err_disable_src_clk: 1282 clk_disable_unprepare(sdd->src_clk); 1283err_disable_clk: 1284 clk_disable_unprepare(sdd->clk); 1285err_deref_master: 1286 spi_master_put(master); 1287 1288 return ret; 1289} 1290 1291static int s3c64xx_spi_remove(struct platform_device *pdev) 1292{ 1293 struct spi_master *master = platform_get_drvdata(pdev); 1294 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1295 1296 pm_runtime_get_sync(&pdev->dev); 1297 1298 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1299 1300 if (!is_polling(sdd)) { 1301 dma_release_channel(sdd->rx_dma.ch); 1302 dma_release_channel(sdd->tx_dma.ch); 1303 } 1304 1305 clk_disable_unprepare(sdd->ioclk); 1306 1307 clk_disable_unprepare(sdd->src_clk); 1308 1309 clk_disable_unprepare(sdd->clk); 1310 1311 pm_runtime_put_noidle(&pdev->dev); 1312 pm_runtime_disable(&pdev->dev); 1313 pm_runtime_set_suspended(&pdev->dev); 1314 1315 return 0; 1316} 1317 1318#ifdef CONFIG_PM_SLEEP 1319static int s3c64xx_spi_suspend(struct device *dev) 1320{ 1321 struct spi_master *master = dev_get_drvdata(dev); 1322 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1323 1324 int ret = spi_master_suspend(master); 1325 if (ret) 1326 return ret; 1327 1328 ret = pm_runtime_force_suspend(dev); 1329 if (ret < 0) 1330 return ret; 1331 1332 sdd->cur_speed = 0; /* Output Clock is stopped */ 1333 1334 return 0; 1335} 1336 1337static int s3c64xx_spi_resume(struct device *dev) 1338{ 1339 struct spi_master *master = dev_get_drvdata(dev); 1340 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1341 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1342 int ret; 1343 1344 if (sci->cfg_gpio) 1345 sci->cfg_gpio(); 1346 1347 ret = pm_runtime_force_resume(dev); 1348 if (ret < 0) 1349 return ret; 1350 1351 return spi_master_resume(master); 1352} 1353#endif /* CONFIG_PM_SLEEP */ 1354 1355#ifdef CONFIG_PM 1356static int s3c64xx_spi_runtime_suspend(struct device *dev) 1357{ 1358 struct spi_master *master = dev_get_drvdata(dev); 1359 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1360 1361 clk_disable_unprepare(sdd->clk); 1362 clk_disable_unprepare(sdd->src_clk); 1363 clk_disable_unprepare(sdd->ioclk); 1364 1365 return 0; 1366} 1367 1368static int s3c64xx_spi_runtime_resume(struct device *dev) 1369{ 1370 struct spi_master *master = dev_get_drvdata(dev); 1371 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1372 int ret; 1373 1374 if (sdd->port_conf->clk_ioclk) { 1375 ret = clk_prepare_enable(sdd->ioclk); 1376 if (ret != 0) 1377 return ret; 1378 } 1379 1380 ret = clk_prepare_enable(sdd->src_clk); 1381 if (ret != 0) 1382 goto err_disable_ioclk; 1383 1384 ret = clk_prepare_enable(sdd->clk); 1385 if (ret != 0) 1386 goto err_disable_src_clk; 1387 1388 s3c64xx_spi_hwinit(sdd); 1389 1390 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1391 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1392 sdd->regs + S3C64XX_SPI_INT_EN); 1393 1394 return 0; 1395 1396err_disable_src_clk: 1397 clk_disable_unprepare(sdd->src_clk); 1398err_disable_ioclk: 1399 clk_disable_unprepare(sdd->ioclk); 1400 1401 return ret; 1402} 1403#endif /* CONFIG_PM */ 1404 1405static const struct dev_pm_ops s3c64xx_spi_pm = { 1406 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1407 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1408 s3c64xx_spi_runtime_resume, NULL) 1409}; 1410 1411static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1412 .fifo_lvl_mask = { 0x7f }, 1413 .rx_lvl_offset = 13, 1414 .tx_st_done = 21, 1415 .high_speed = true, 1416}; 1417 1418static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1419 .fifo_lvl_mask = { 0x7f, 0x7F }, 1420 .rx_lvl_offset = 13, 1421 .tx_st_done = 21, 1422}; 1423 1424static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1425 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1426 .rx_lvl_offset = 15, 1427 .tx_st_done = 25, 1428 .high_speed = true, 1429}; 1430 1431static struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1432 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1433 .rx_lvl_offset = 15, 1434 .tx_st_done = 25, 1435 .high_speed = true, 1436 .clk_from_cmu = true, 1437 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1438}; 1439 1440static struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1441 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1442 .rx_lvl_offset = 15, 1443 .tx_st_done = 25, 1444 .high_speed = true, 1445 .clk_from_cmu = true, 1446 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1447}; 1448 1449static struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1450 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1451 .rx_lvl_offset = 15, 1452 .tx_st_done = 25, 1453 .high_speed = true, 1454 .clk_from_cmu = true, 1455 .clk_ioclk = true, 1456 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1457}; 1458 1459static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1460 { 1461 .name = "s3c2443-spi", 1462 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1463 }, { 1464 .name = "s3c6410-spi", 1465 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1466 }, 1467 { }, 1468}; 1469 1470static const struct of_device_id s3c64xx_spi_dt_match[] = { 1471 { .compatible = "samsung,s3c2443-spi", 1472 .data = (void *)&s3c2443_spi_port_config, 1473 }, 1474 { .compatible = "samsung,s3c6410-spi", 1475 .data = (void *)&s3c6410_spi_port_config, 1476 }, 1477 { .compatible = "samsung,s5pv210-spi", 1478 .data = (void *)&s5pv210_spi_port_config, 1479 }, 1480 { .compatible = "samsung,exynos4210-spi", 1481 .data = (void *)&exynos4_spi_port_config, 1482 }, 1483 { .compatible = "samsung,exynos7-spi", 1484 .data = (void *)&exynos7_spi_port_config, 1485 }, 1486 { .compatible = "samsung,exynos5433-spi", 1487 .data = (void *)&exynos5433_spi_port_config, 1488 }, 1489 { }, 1490}; 1491MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1492 1493static struct platform_driver s3c64xx_spi_driver = { 1494 .driver = { 1495 .name = "s3c64xx-spi", 1496 .pm = &s3c64xx_spi_pm, 1497 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1498 }, 1499 .probe = s3c64xx_spi_probe, 1500 .remove = s3c64xx_spi_remove, 1501 .id_table = s3c64xx_spi_driver_ids, 1502}; 1503MODULE_ALIAS("platform:s3c64xx-spi"); 1504 1505module_platform_driver(s3c64xx_spi_driver); 1506 1507MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1508MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1509MODULE_LICENSE("GPL"); 1510