18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2004 Fetron GmbH 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * S3C2410 SPI register definition 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#ifndef __SPI_S3C2410_H 98c2ecf20Sopenharmony_ci#define __SPI_S3C2410_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#define S3C2410_SPCON (0x00) 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ 148c2ecf20Sopenharmony_ci#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ 158c2ecf20Sopenharmony_ci#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ 168c2ecf20Sopenharmony_ci#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ 178c2ecf20Sopenharmony_ci#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ 188c2ecf20Sopenharmony_ci#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ 198c2ecf20Sopenharmony_ci#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ 228c2ecf20Sopenharmony_ci#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#define S3C2410_SPSTA (0x04) 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ 278c2ecf20Sopenharmony_ci#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ 288c2ecf20Sopenharmony_ci#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ 298c2ecf20Sopenharmony_ci#define S3C2412_SPSTA_READY_ORG (1 << 3) 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#define S3C2410_SPPIN (0x08) 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ 348c2ecf20Sopenharmony_ci#define S3C2410_SPPIN_RESERVED (1 << 1) 358c2ecf20Sopenharmony_ci#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci#define S3C2410_SPPRE (0x0C) 388c2ecf20Sopenharmony_ci#define S3C2410_SPTDAT (0x10) 398c2ecf20Sopenharmony_ci#define S3C2410_SPRDAT (0x14) 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci#endif /* __SPI_S3C2410_H */ 42