1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * CE4100's SPI device is more or less the same one as found on PXA 4 * 5 * Copyright (C) 2016, Intel Corporation 6 */ 7#include <linux/clk-provider.h> 8#include <linux/module.h> 9#include <linux/pci.h> 10#include <linux/platform_device.h> 11#include <linux/spi/pxa2xx_spi.h> 12 13#include <linux/dmaengine.h> 14#include <linux/platform_data/dma-dw.h> 15 16enum { 17 PORT_QUARK_X1000, 18 PORT_BYT, 19 PORT_MRFLD, 20 PORT_BSW0, 21 PORT_BSW1, 22 PORT_BSW2, 23 PORT_CE4100, 24 PORT_LPT0, 25 PORT_LPT1, 26}; 27 28struct pxa_spi_info { 29 enum pxa_ssp_type type; 30 int port_id; 31 int num_chipselect; 32 unsigned long max_clk_rate; 33 34 /* DMA channel request parameters */ 35 bool (*dma_filter)(struct dma_chan *chan, void *param); 36 void *tx_param; 37 void *rx_param; 38 39 int dma_burst_size; 40 41 int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c); 42}; 43 44static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; 45static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; 46 47static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 }; 48static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 }; 49static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 }; 50static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 }; 51static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 }; 52static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 }; 53 54static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; 55static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; 56static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; 57static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 }; 58static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 }; 59static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 }; 60 61static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 }; 62static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 }; 63static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 }; 64static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 }; 65 66static bool lpss_dma_filter(struct dma_chan *chan, void *param) 67{ 68 struct dw_dma_slave *dws = param; 69 70 if (dws->dma_dev != chan->device->dev) 71 return false; 72 73 chan->private = dws; 74 return true; 75} 76 77static void lpss_dma_put_device(void *dma_dev) 78{ 79 pci_dev_put(dma_dev); 80} 81 82static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) 83{ 84 struct pci_dev *dma_dev; 85 int ret; 86 87 c->num_chipselect = 1; 88 c->max_clk_rate = 50000000; 89 90 dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); 91 ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev); 92 if (ret) 93 return ret; 94 95 if (c->tx_param) { 96 struct dw_dma_slave *slave = c->tx_param; 97 98 slave->dma_dev = &dma_dev->dev; 99 slave->m_master = 0; 100 slave->p_master = 1; 101 } 102 103 if (c->rx_param) { 104 struct dw_dma_slave *slave = c->rx_param; 105 106 slave->dma_dev = &dma_dev->dev; 107 slave->m_master = 0; 108 slave->p_master = 1; 109 } 110 111 c->dma_filter = lpss_dma_filter; 112 return 0; 113} 114 115static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) 116{ 117 struct dw_dma_slave *tx, *rx; 118 struct pci_dev *dma_dev; 119 int ret; 120 121 switch (PCI_FUNC(dev->devfn)) { 122 case 0: 123 c->port_id = 3; 124 c->num_chipselect = 1; 125 c->tx_param = &mrfld3_tx_param; 126 c->rx_param = &mrfld3_rx_param; 127 break; 128 case 1: 129 c->port_id = 5; 130 c->num_chipselect = 4; 131 c->tx_param = &mrfld5_tx_param; 132 c->rx_param = &mrfld5_rx_param; 133 break; 134 case 2: 135 c->port_id = 6; 136 c->num_chipselect = 1; 137 c->tx_param = &mrfld6_tx_param; 138 c->rx_param = &mrfld6_rx_param; 139 break; 140 default: 141 return -ENODEV; 142 } 143 144 dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0)); 145 ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev); 146 if (ret) 147 return ret; 148 149 tx = c->tx_param; 150 tx->dma_dev = &dma_dev->dev; 151 152 rx = c->rx_param; 153 rx->dma_dev = &dma_dev->dev; 154 155 c->dma_filter = lpss_dma_filter; 156 c->dma_burst_size = 8; 157 return 0; 158} 159 160static struct pxa_spi_info spi_info_configs[] = { 161 [PORT_CE4100] = { 162 .type = PXA25x_SSP, 163 .port_id = -1, 164 .num_chipselect = -1, 165 .max_clk_rate = 3686400, 166 }, 167 [PORT_BYT] = { 168 .type = LPSS_BYT_SSP, 169 .port_id = 0, 170 .setup = lpss_spi_setup, 171 .tx_param = &byt_tx_param, 172 .rx_param = &byt_rx_param, 173 }, 174 [PORT_BSW0] = { 175 .type = LPSS_BSW_SSP, 176 .port_id = 0, 177 .setup = lpss_spi_setup, 178 .tx_param = &bsw0_tx_param, 179 .rx_param = &bsw0_rx_param, 180 }, 181 [PORT_BSW1] = { 182 .type = LPSS_BSW_SSP, 183 .port_id = 1, 184 .setup = lpss_spi_setup, 185 .tx_param = &bsw1_tx_param, 186 .rx_param = &bsw1_rx_param, 187 }, 188 [PORT_BSW2] = { 189 .type = LPSS_BSW_SSP, 190 .port_id = 2, 191 .setup = lpss_spi_setup, 192 .tx_param = &bsw2_tx_param, 193 .rx_param = &bsw2_rx_param, 194 }, 195 [PORT_MRFLD] = { 196 .type = PXA27x_SSP, 197 .max_clk_rate = 25000000, 198 .setup = mrfld_spi_setup, 199 }, 200 [PORT_QUARK_X1000] = { 201 .type = QUARK_X1000_SSP, 202 .port_id = -1, 203 .num_chipselect = 1, 204 .max_clk_rate = 50000000, 205 }, 206 [PORT_LPT0] = { 207 .type = LPSS_LPT_SSP, 208 .port_id = 0, 209 .setup = lpss_spi_setup, 210 .tx_param = &lpt0_tx_param, 211 .rx_param = &lpt0_rx_param, 212 }, 213 [PORT_LPT1] = { 214 .type = LPSS_LPT_SSP, 215 .port_id = 1, 216 .setup = lpss_spi_setup, 217 .tx_param = &lpt1_tx_param, 218 .rx_param = &lpt1_rx_param, 219 }, 220}; 221 222static int pxa2xx_spi_pci_probe(struct pci_dev *dev, 223 const struct pci_device_id *ent) 224{ 225 struct platform_device_info pi; 226 int ret; 227 struct platform_device *pdev; 228 struct pxa2xx_spi_controller spi_pdata; 229 struct ssp_device *ssp; 230 struct pxa_spi_info *c; 231 char buf[40]; 232 233 ret = pcim_enable_device(dev); 234 if (ret) 235 return ret; 236 237 ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI"); 238 if (ret) 239 return ret; 240 241 c = &spi_info_configs[ent->driver_data]; 242 if (c->setup) { 243 ret = c->setup(dev, c); 244 if (ret) 245 return ret; 246 } 247 248 memset(&spi_pdata, 0, sizeof(spi_pdata)); 249 spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn; 250 spi_pdata.dma_filter = c->dma_filter; 251 spi_pdata.tx_param = c->tx_param; 252 spi_pdata.rx_param = c->rx_param; 253 spi_pdata.enable_dma = c->rx_param && c->tx_param; 254 spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1; 255 256 ssp = &spi_pdata.ssp; 257 ssp->phys_base = pci_resource_start(dev, 0); 258 ssp->mmio_base = pcim_iomap_table(dev)[0]; 259 ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; 260 ssp->type = c->type; 261 262 pci_set_master(dev); 263 264 ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 265 if (ret < 0) 266 return ret; 267 ssp->irq = pci_irq_vector(dev, 0); 268 269 snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); 270 ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0, 271 c->max_clk_rate); 272 if (IS_ERR(ssp->clk)) 273 return PTR_ERR(ssp->clk); 274 275 memset(&pi, 0, sizeof(pi)); 276 pi.fwnode = dev->dev.fwnode; 277 pi.parent = &dev->dev; 278 pi.name = "pxa2xx-spi"; 279 pi.id = ssp->port_id; 280 pi.data = &spi_pdata; 281 pi.size_data = sizeof(spi_pdata); 282 283 pdev = platform_device_register_full(&pi); 284 if (IS_ERR(pdev)) { 285 clk_unregister(ssp->clk); 286 return PTR_ERR(pdev); 287 } 288 289 pci_set_drvdata(dev, pdev); 290 291 return 0; 292} 293 294static void pxa2xx_spi_pci_remove(struct pci_dev *dev) 295{ 296 struct platform_device *pdev = pci_get_drvdata(dev); 297 struct pxa2xx_spi_controller *spi_pdata; 298 299 spi_pdata = dev_get_platdata(&pdev->dev); 300 301 platform_device_unregister(pdev); 302 clk_unregister(spi_pdata->ssp.clk); 303} 304 305static const struct pci_device_id pxa2xx_spi_pci_devices[] = { 306 { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 }, 307 { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT }, 308 { PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD }, 309 { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 }, 310 { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 }, 311 { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 }, 312 { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 }, 313 { PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 }, 314 { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 }, 315 { } 316}; 317MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices); 318 319static struct pci_driver pxa2xx_spi_pci_driver = { 320 .name = "pxa2xx_spi_pci", 321 .id_table = pxa2xx_spi_pci_devices, 322 .probe = pxa2xx_spi_pci_probe, 323 .remove = pxa2xx_spi_pci_remove, 324}; 325 326module_pci_driver(pxa2xx_spi_pci_driver); 327 328MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver"); 329MODULE_LICENSE("GPL v2"); 330MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>"); 331