1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2019 Nuvoton Technology corporation. 3 4#include <linux/bits.h> 5#include <linux/init.h> 6#include <linux/kernel.h> 7#include <linux/device.h> 8#include <linux/module.h> 9#include <linux/ioport.h> 10#include <linux/clk.h> 11#include <linux/platform_device.h> 12#include <linux/io.h> 13#include <linux/vmalloc.h> 14#include <linux/regmap.h> 15#include <linux/of_device.h> 16#include <linux/spi/spi-mem.h> 17#include <linux/mfd/syscon.h> 18 19/* NPCM7xx GCR module */ 20#define NPCM7XX_INTCR3_OFFSET 0x9C 21#define NPCM7XX_INTCR3_FIU_FIX BIT(6) 22 23/* Flash Interface Unit (FIU) Registers */ 24#define NPCM_FIU_DRD_CFG 0x00 25#define NPCM_FIU_DWR_CFG 0x04 26#define NPCM_FIU_UMA_CFG 0x08 27#define NPCM_FIU_UMA_CTS 0x0C 28#define NPCM_FIU_UMA_CMD 0x10 29#define NPCM_FIU_UMA_ADDR 0x14 30#define NPCM_FIU_PRT_CFG 0x18 31#define NPCM_FIU_UMA_DW0 0x20 32#define NPCM_FIU_UMA_DW1 0x24 33#define NPCM_FIU_UMA_DW2 0x28 34#define NPCM_FIU_UMA_DW3 0x2C 35#define NPCM_FIU_UMA_DR0 0x30 36#define NPCM_FIU_UMA_DR1 0x34 37#define NPCM_FIU_UMA_DR2 0x38 38#define NPCM_FIU_UMA_DR3 0x3C 39#define NPCM_FIU_MAX_REG_LIMIT 0x80 40 41/* FIU Direct Read Configuration Register */ 42#define NPCM_FIU_DRD_CFG_LCK BIT(31) 43#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) 44#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16) 45#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) 46#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) 47#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) 48#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 49#define NPCM_FIU_DRD_DBW_SHIFT 12 50#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 51 52/* FIU Direct Write Configuration Register */ 53#define NPCM_FIU_DWR_CFG_LCK BIT(31) 54#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) 55#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16) 56#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) 57#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) 58#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) 59#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 60#define NPCM_FIU_DWR_ABPCK_SHIFT 10 61#define NPCM_FIU_DWR_DBPCK_SHIFT 8 62 63/* FIU UMA Configuration Register */ 64#define NPCM_FIU_UMA_CFG_LCK BIT(31) 65#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30) 66#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) 67#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) 68#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) 69#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11) 70#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10) 71#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8) 72#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6) 73#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4) 74#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2) 75#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0) 76#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2 77#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4 78#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6 79#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8 80#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11 81#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16 82#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21 83#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24 84 85/* FIU UMA Control and Status Register */ 86#define NPCM_FIU_UMA_CTS_RDYIE BIT(25) 87#define NPCM_FIU_UMA_CTS_RDYST BIT(24) 88#define NPCM_FIU_UMA_CTS_SW_CS BIT(16) 89#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8) 90#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0) 91#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8 92 93/* FIU UMA Command Register */ 94#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24) 95#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16) 96#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8) 97#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0) 98 99/* FIU UMA Address Register */ 100#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0) 101#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24) 102#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16) 103#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8) 104#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0) 105 106/* FIU UMA Write Data Bytes 0-3 Register */ 107#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24) 108#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16) 109#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8) 110#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0) 111 112/* FIU UMA Write Data Bytes 4-7 Register */ 113#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24) 114#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16) 115#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8) 116#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0) 117 118/* FIU UMA Write Data Bytes 8-11 Register */ 119#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24) 120#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16) 121#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8) 122#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0) 123 124/* FIU UMA Write Data Bytes 12-15 Register */ 125#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24) 126#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16) 127#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8) 128#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0) 129 130/* FIU UMA Read Data Bytes 0-3 Register */ 131#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24) 132#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16) 133#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8) 134#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0) 135 136/* FIU UMA Read Data Bytes 4-7 Register */ 137#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24) 138#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16) 139#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8) 140#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0) 141 142/* FIU UMA Read Data Bytes 8-11 Register */ 143#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24) 144#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16) 145#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8) 146#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0) 147 148/* FIU UMA Read Data Bytes 12-15 Register */ 149#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24) 150#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16) 151#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8) 152#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0) 153 154/* FIU Read Mode */ 155enum { 156 DRD_SINGLE_WIRE_MODE = 0, 157 DRD_DUAL_IO_MODE = 1, 158 DRD_QUAD_IO_MODE = 2, 159 DRD_SPI_X_MODE = 3, 160}; 161 162enum { 163 DWR_ABPCK_BIT_PER_CLK = 0, 164 DWR_ABPCK_2_BIT_PER_CLK = 1, 165 DWR_ABPCK_4_BIT_PER_CLK = 2, 166}; 167 168enum { 169 DWR_DBPCK_BIT_PER_CLK = 0, 170 DWR_DBPCK_2_BIT_PER_CLK = 1, 171 DWR_DBPCK_4_BIT_PER_CLK = 2, 172}; 173 174#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000 175#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000 176 177#define MAP_SIZE_128MB 0x8000000 178#define MAP_SIZE_16MB 0x1000000 179#define MAP_SIZE_8MB 0x800000 180 181#define FIU_DRD_MAX_DUMMY_NUMBER 3 182#define NPCM_MAX_CHIP_NUM 4 183#define CHUNK_SIZE 16 184#define UMA_MICRO_SEC_TIMEOUT 150 185 186enum { 187 FIU0 = 0, 188 FIU3, 189 FIUX, 190}; 191 192struct npcm_fiu_info { 193 char *name; 194 u32 fiu_id; 195 u32 max_map_size; 196 u32 max_cs; 197}; 198 199struct fiu_data { 200 const struct npcm_fiu_info *npcm_fiu_data_info; 201 int fiu_max; 202}; 203 204static const struct npcm_fiu_info npxm7xx_fiu_info[] = { 205 {.name = "FIU0", .fiu_id = FIU0, 206 .max_map_size = MAP_SIZE_128MB, .max_cs = 2}, 207 {.name = "FIU3", .fiu_id = FIU3, 208 .max_map_size = MAP_SIZE_128MB, .max_cs = 4}, 209 {.name = "FIUX", .fiu_id = FIUX, 210 .max_map_size = MAP_SIZE_16MB, .max_cs = 2} }; 211 212static const struct fiu_data npxm7xx_fiu_data = { 213 .npcm_fiu_data_info = npxm7xx_fiu_info, 214 .fiu_max = 3, 215}; 216 217struct npcm_fiu_spi; 218 219struct npcm_fiu_chip { 220 void __iomem *flash_region_mapped_ptr; 221 struct npcm_fiu_spi *fiu; 222 unsigned long clkrate; 223 u32 chipselect; 224}; 225 226struct npcm_fiu_spi { 227 struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM]; 228 const struct npcm_fiu_info *info; 229 struct spi_mem_op drd_op; 230 struct resource *res_mem; 231 struct regmap *regmap; 232 unsigned long clkrate; 233 struct device *dev; 234 struct clk *clk; 235 bool spix_mode; 236}; 237 238static const struct regmap_config npcm_mtd_regmap_config = { 239 .reg_bits = 32, 240 .val_bits = 32, 241 .reg_stride = 4, 242 .max_register = NPCM_FIU_MAX_REG_LIMIT, 243}; 244 245static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu, 246 const struct spi_mem_op *op) 247{ 248 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 249 NPCM_FIU_DRD_CFG_ACCTYPE, 250 ilog2(op->addr.buswidth) << 251 NPCM_FIU_DRD_ACCTYPE_SHIFT); 252 fiu->drd_op.addr.buswidth = op->addr.buswidth; 253 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 254 NPCM_FIU_DRD_CFG_DBW, 255 ((op->dummy.nbytes * ilog2(op->addr.buswidth)) / BITS_PER_BYTE) 256 << NPCM_FIU_DRD_DBW_SHIFT); 257 fiu->drd_op.dummy.nbytes = op->dummy.nbytes; 258 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 259 NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode); 260 fiu->drd_op.cmd.opcode = op->cmd.opcode; 261 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 262 NPCM_FIU_DRD_CFG_ADDSIZ, 263 (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT); 264 fiu->drd_op.addr.nbytes = op->addr.nbytes; 265} 266 267static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, 268 u64 offs, size_t len, void *buf) 269{ 270 struct npcm_fiu_spi *fiu = 271 spi_controller_get_devdata(desc->mem->spi->master); 272 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; 273 void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + 274 offs); 275 u8 *buf_rx = buf; 276 u32 i; 277 278 if (fiu->spix_mode) { 279 for (i = 0 ; i < len ; i++) 280 *(buf_rx + i) = ioread8(src + i); 281 } else { 282 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth || 283 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes || 284 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode || 285 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes) 286 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); 287 288 memcpy_fromio(buf_rx, src, len); 289 } 290 291 return len; 292} 293 294static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc, 295 u64 offs, size_t len, const void *buf) 296{ 297 struct npcm_fiu_spi *fiu = 298 spi_controller_get_devdata(desc->mem->spi->master); 299 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; 300 void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + 301 offs); 302 const u8 *buf_tx = buf; 303 u32 i; 304 305 if (fiu->spix_mode) 306 for (i = 0 ; i < len ; i++) 307 iowrite8(*(buf_tx + i), dst + i); 308 else 309 memcpy_toio(dst, buf_tx, len); 310 311 return len; 312} 313 314static int npcm_fiu_uma_read(struct spi_mem *mem, 315 const struct spi_mem_op *op, u32 addr, 316 bool is_address_size, u8 *data, u32 data_size) 317{ 318 struct npcm_fiu_spi *fiu = 319 spi_controller_get_devdata(mem->spi->master); 320 u32 uma_cfg = BIT(10); 321 u32 data_reg[4]; 322 int ret; 323 u32 val; 324 u32 i; 325 326 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 327 NPCM_FIU_UMA_CTS_DEV_NUM, 328 (mem->spi->chip_select << 329 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 330 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, 331 NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); 332 333 if (is_address_size) { 334 uma_cfg |= ilog2(op->cmd.buswidth); 335 uma_cfg |= ilog2(op->addr.buswidth) 336 << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; 337 if (op->dummy.nbytes) 338 uma_cfg |= ilog2(op->dummy.buswidth) 339 << NPCM_FIU_UMA_CFG_DBPCK_SHIFT; 340 uma_cfg |= ilog2(op->data.buswidth) 341 << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT; 342 uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT; 343 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; 344 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr); 345 } else { 346 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); 347 } 348 349 uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT; 350 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); 351 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 352 NPCM_FIU_UMA_CTS_EXEC_DONE, 353 NPCM_FIU_UMA_CTS_EXEC_DONE); 354 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, 355 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, 356 UMA_MICRO_SEC_TIMEOUT); 357 if (ret) 358 return ret; 359 360 if (data_size) { 361 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) 362 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4), 363 &data_reg[i]); 364 memcpy(data, data_reg, data_size); 365 } 366 367 return 0; 368} 369 370static int npcm_fiu_uma_write(struct spi_mem *mem, 371 const struct spi_mem_op *op, u8 cmd, 372 bool is_address_size, u8 *data, u32 data_size) 373{ 374 struct npcm_fiu_spi *fiu = 375 spi_controller_get_devdata(mem->spi->master); 376 u32 uma_cfg = BIT(10); 377 u32 data_reg[4] = {0}; 378 u32 val; 379 u32 i; 380 381 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 382 NPCM_FIU_UMA_CTS_DEV_NUM, 383 (mem->spi->chip_select << 384 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 385 386 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, 387 NPCM_FIU_UMA_CMD_CMD, cmd); 388 389 if (data_size) { 390 memcpy(data_reg, data, data_size); 391 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) 392 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4), 393 data_reg[i]); 394 } 395 396 if (is_address_size) { 397 uma_cfg |= ilog2(op->cmd.buswidth); 398 uma_cfg |= ilog2(op->addr.buswidth) << 399 NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; 400 uma_cfg |= ilog2(op->data.buswidth) << 401 NPCM_FIU_UMA_CFG_WDBPCK_SHIFT; 402 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; 403 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); 404 } else { 405 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); 406 } 407 408 uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT); 409 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); 410 411 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 412 NPCM_FIU_UMA_CTS_EXEC_DONE, 413 NPCM_FIU_UMA_CTS_EXEC_DONE); 414 415 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, 416 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, 417 UMA_MICRO_SEC_TIMEOUT); 418} 419 420static int npcm_fiu_manualwrite(struct spi_mem *mem, 421 const struct spi_mem_op *op) 422{ 423 struct npcm_fiu_spi *fiu = 424 spi_controller_get_devdata(mem->spi->master); 425 u8 *data = (u8 *)op->data.buf.out; 426 u32 num_data_chunks; 427 u32 remain_data; 428 u32 idx = 0; 429 int ret; 430 431 num_data_chunks = op->data.nbytes / CHUNK_SIZE; 432 remain_data = op->data.nbytes % CHUNK_SIZE; 433 434 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 435 NPCM_FIU_UMA_CTS_DEV_NUM, 436 (mem->spi->chip_select << 437 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 438 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 439 NPCM_FIU_UMA_CTS_SW_CS, 0); 440 441 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0); 442 if (ret) 443 return ret; 444 445 /* Starting the data writing loop in multiples of 8 */ 446 for (idx = 0; idx < num_data_chunks; ++idx) { 447 ret = npcm_fiu_uma_write(mem, op, data[0], false, 448 &data[1], CHUNK_SIZE - 1); 449 if (ret) 450 return ret; 451 452 data += CHUNK_SIZE; 453 } 454 455 /* Handling chunk remains */ 456 if (remain_data > 0) { 457 ret = npcm_fiu_uma_write(mem, op, data[0], false, 458 &data[1], remain_data - 1); 459 if (ret) 460 return ret; 461 } 462 463 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 464 NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS); 465 466 return 0; 467} 468 469static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op) 470{ 471 u8 *data = op->data.buf.in; 472 int i, readlen, currlen; 473 u8 *buf_ptr; 474 u32 addr; 475 int ret; 476 477 i = 0; 478 currlen = op->data.nbytes; 479 480 do { 481 addr = ((u32)op->addr.val + i); 482 if (currlen < 16) 483 readlen = currlen; 484 else 485 readlen = 16; 486 487 buf_ptr = data + i; 488 ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr, 489 readlen); 490 if (ret) 491 return ret; 492 493 i += readlen; 494 currlen -= 16; 495 } while (currlen > 0); 496 497 return 0; 498} 499 500static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu) 501{ 502 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG, 503 NPCM_FIU_DWR_16_BYTE_BURST); 504 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, 505 NPCM_FIU_DWR_CFG_ABPCK, 506 DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT); 507 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, 508 NPCM_FIU_DWR_CFG_DBPCK, 509 DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT); 510} 511 512static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu) 513{ 514 u32 rx_dummy = 0; 515 516 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG, 517 NPCM_FIU_DRD_16_BYTE_BURST); 518 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 519 NPCM_FIU_DRD_CFG_ACCTYPE, 520 DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT); 521 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 522 NPCM_FIU_DRD_CFG_DBW, 523 rx_dummy << NPCM_FIU_DRD_DBW_SHIFT); 524} 525 526static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 527{ 528 struct npcm_fiu_spi *fiu = 529 spi_controller_get_devdata(mem->spi->master); 530 struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select]; 531 int ret = 0; 532 u8 *buf; 533 534 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", 535 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 536 op->dummy.buswidth, op->data.buswidth, op->addr.val, 537 op->data.nbytes); 538 539 if (fiu->spix_mode || op->addr.nbytes > 4) 540 return -ENOTSUPP; 541 542 if (fiu->clkrate != chip->clkrate) { 543 ret = clk_set_rate(fiu->clk, chip->clkrate); 544 if (ret < 0) 545 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n", 546 chip->clkrate, fiu->clkrate); 547 else 548 fiu->clkrate = chip->clkrate; 549 } 550 551 if (op->data.dir == SPI_MEM_DATA_IN) { 552 if (!op->addr.nbytes) { 553 buf = op->data.buf.in; 554 ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, 555 buf, op->data.nbytes); 556 } else { 557 ret = npcm_fiu_read(mem, op); 558 } 559 } else { 560 if (!op->addr.nbytes && !op->data.nbytes) 561 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 562 NULL, 0); 563 if (op->addr.nbytes && !op->data.nbytes) { 564 int i; 565 u8 buf_addr[4]; 566 u32 addr = op->addr.val; 567 568 for (i = op->addr.nbytes - 1; i >= 0; i--) { 569 buf_addr[i] = addr & 0xff; 570 addr >>= 8; 571 } 572 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 573 buf_addr, op->addr.nbytes); 574 } 575 if (!op->addr.nbytes && op->data.nbytes) 576 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 577 (u8 *)op->data.buf.out, 578 op->data.nbytes); 579 if (op->addr.nbytes && op->data.nbytes) 580 ret = npcm_fiu_manualwrite(mem, op); 581 } 582 583 return ret; 584} 585 586static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) 587{ 588 struct npcm_fiu_spi *fiu = 589 spi_controller_get_devdata(desc->mem->spi->master); 590 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; 591 struct regmap *gcr_regmap; 592 593 if (!fiu->res_mem) { 594 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n"); 595 desc->nodirmap = true; 596 return 0; 597 } 598 599 if (!fiu->spix_mode && 600 desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { 601 desc->nodirmap = true; 602 return 0; 603 } 604 605 if (!chip->flash_region_mapped_ptr) { 606 chip->flash_region_mapped_ptr = 607 devm_ioremap(fiu->dev, (fiu->res_mem->start + 608 (fiu->info->max_map_size * 609 desc->mem->spi->chip_select)), 610 (u32)desc->info.length); 611 if (!chip->flash_region_mapped_ptr) { 612 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); 613 desc->nodirmap = true; 614 return 0; 615 } 616 } 617 618 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) { 619 gcr_regmap = 620 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 621 if (IS_ERR(gcr_regmap)) { 622 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n"); 623 desc->nodirmap = true; 624 return 0; 625 } 626 regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET, 627 NPCM7XX_INTCR3_FIU_FIX, 628 NPCM7XX_INTCR3_FIU_FIX); 629 } 630 631 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { 632 if (!fiu->spix_mode) 633 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); 634 else 635 npcm_fiux_set_direct_rd(fiu); 636 637 } else { 638 npcm_fiux_set_direct_wr(fiu); 639 } 640 641 return 0; 642} 643 644static int npcm_fiu_setup(struct spi_device *spi) 645{ 646 struct spi_controller *ctrl = spi->master; 647 struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl); 648 struct npcm_fiu_chip *chip; 649 650 chip = &fiu->chip[spi->chip_select]; 651 chip->fiu = fiu; 652 chip->chipselect = spi->chip_select; 653 chip->clkrate = spi->max_speed_hz; 654 655 fiu->clkrate = clk_get_rate(fiu->clk); 656 657 return 0; 658} 659 660static const struct spi_controller_mem_ops npcm_fiu_mem_ops = { 661 .exec_op = npcm_fiu_exec_op, 662 .dirmap_create = npcm_fiu_dirmap_create, 663 .dirmap_read = npcm_fiu_direct_read, 664 .dirmap_write = npcm_fiu_direct_write, 665}; 666 667static const struct of_device_id npcm_fiu_dt_ids[] = { 668 { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data }, 669 { /* sentinel */ } 670}; 671 672static int npcm_fiu_probe(struct platform_device *pdev) 673{ 674 const struct fiu_data *fiu_data_match; 675 const struct of_device_id *match; 676 struct device *dev = &pdev->dev; 677 struct spi_controller *ctrl; 678 struct npcm_fiu_spi *fiu; 679 void __iomem *regbase; 680 struct resource *res; 681 int id, ret; 682 683 ctrl = devm_spi_alloc_master(dev, sizeof(*fiu)); 684 if (!ctrl) 685 return -ENOMEM; 686 687 fiu = spi_controller_get_devdata(ctrl); 688 689 match = of_match_device(npcm_fiu_dt_ids, dev); 690 if (!match || !match->data) { 691 dev_err(dev, "No compatible OF match\n"); 692 return -ENODEV; 693 } 694 695 fiu_data_match = match->data; 696 id = of_alias_get_id(dev->of_node, "fiu"); 697 if (id < 0 || id >= fiu_data_match->fiu_max) { 698 dev_err(dev, "Invalid platform device id: %d\n", id); 699 return -EINVAL; 700 } 701 702 fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; 703 704 platform_set_drvdata(pdev, fiu); 705 fiu->dev = dev; 706 707 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); 708 regbase = devm_ioremap_resource(dev, res); 709 if (IS_ERR(regbase)) 710 return PTR_ERR(regbase); 711 712 fiu->regmap = devm_regmap_init_mmio(dev, regbase, 713 &npcm_mtd_regmap_config); 714 if (IS_ERR(fiu->regmap)) { 715 dev_err(dev, "Failed to create regmap\n"); 716 return PTR_ERR(fiu->regmap); 717 } 718 719 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, 720 "memory"); 721 fiu->clk = devm_clk_get(dev, NULL); 722 if (IS_ERR(fiu->clk)) 723 return PTR_ERR(fiu->clk); 724 725 fiu->spix_mode = of_property_read_bool(dev->of_node, 726 "nuvoton,spix-mode"); 727 728 platform_set_drvdata(pdev, fiu); 729 clk_prepare_enable(fiu->clk); 730 731 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD 732 | SPI_TX_DUAL | SPI_TX_QUAD; 733 ctrl->setup = npcm_fiu_setup; 734 ctrl->bus_num = -1; 735 ctrl->mem_ops = &npcm_fiu_mem_ops; 736 ctrl->num_chipselect = fiu->info->max_cs; 737 ctrl->dev.of_node = dev->of_node; 738 739 ret = devm_spi_register_master(dev, ctrl); 740 if (ret) 741 clk_disable_unprepare(fiu->clk); 742 743 return ret; 744} 745 746static int npcm_fiu_remove(struct platform_device *pdev) 747{ 748 struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev); 749 750 clk_disable_unprepare(fiu->clk); 751 return 0; 752} 753 754MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids); 755 756static struct platform_driver npcm_fiu_driver = { 757 .driver = { 758 .name = "NPCM-FIU", 759 .bus = &platform_bus_type, 760 .of_match_table = npcm_fiu_dt_ids, 761 }, 762 .probe = npcm_fiu_probe, 763 .remove = npcm_fiu_remove, 764}; 765module_platform_driver(npcm_fiu_driver); 766 767MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver"); 768MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 769MODULE_LICENSE("GPL v2"); 770