1// SPDX-License-Identifier: GPL-2.0
2//
3// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
4//
5// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
6// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
8//
9// Some parts are based on spi-orion.c:
10//   Author: Shadi Ammouri <shadi@marvell.com>
11//   Copyright (C) 2007-2008 Marvell Ltd.
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/reset.h>
19#include <linux/spi/spi.h>
20
21#define DRIVER_NAME		"spi-mt7621"
22
23/* in usec */
24#define RALINK_SPI_WAIT_MAX_LOOP 2000
25
26/* SPISTAT register bit field */
27#define SPISTAT_BUSY		BIT(0)
28
29#define MT7621_SPI_TRANS	0x00
30#define SPITRANS_BUSY		BIT(16)
31
32#define MT7621_SPI_OPCODE	0x04
33#define MT7621_SPI_DATA0	0x08
34#define MT7621_SPI_DATA4	0x18
35#define SPI_CTL_TX_RX_CNT_MASK	0xff
36#define SPI_CTL_START		BIT(8)
37
38#define MT7621_SPI_MASTER	0x28
39#define MASTER_MORE_BUFMODE	BIT(2)
40#define MASTER_FULL_DUPLEX	BIT(10)
41#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
42#define MASTER_RS_CLK_SEL_SHIFT	16
43#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
44
45#define MT7621_SPI_MOREBUF	0x2c
46#define MT7621_SPI_POLAR	0x38
47#define MT7621_SPI_SPACE	0x3c
48
49#define MT7621_CPHA		BIT(5)
50#define MT7621_CPOL		BIT(4)
51#define MT7621_LSB_FIRST	BIT(3)
52
53struct mt7621_spi {
54	struct spi_controller	*master;
55	void __iomem		*base;
56	unsigned int		sys_freq;
57	unsigned int		speed;
58	struct clk		*clk;
59	int			pending_write;
60};
61
62static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
63{
64	return spi_controller_get_devdata(spi->master);
65}
66
67static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
68{
69	return ioread32(rs->base + reg);
70}
71
72static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
73{
74	iowrite32(val, rs->base + reg);
75}
76
77static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
78{
79	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
80	int cs = spi->chip_select;
81	u32 polar = 0;
82	u32 master;
83
84	/*
85	 * Select SPI device 7, enable "more buffer mode" and disable
86	 * full-duplex (only half-duplex really works on this chip
87	 * reliably)
88	 */
89	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
90	master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
91	master &= ~MASTER_FULL_DUPLEX;
92	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
93
94	rs->pending_write = 0;
95
96	if (enable)
97		polar = BIT(cs);
98	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
99}
100
101static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
102{
103	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
104	u32 rate;
105	u32 reg;
106
107	dev_dbg(&spi->dev, "speed:%u\n", speed);
108
109	rate = DIV_ROUND_UP(rs->sys_freq, speed);
110	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
111
112	if (rate > 4097)
113		return -EINVAL;
114
115	if (rate < 2)
116		rate = 2;
117
118	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
119	reg &= ~MASTER_RS_CLK_SEL;
120	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
121	rs->speed = speed;
122
123	reg &= ~MT7621_LSB_FIRST;
124	if (spi->mode & SPI_LSB_FIRST)
125		reg |= MT7621_LSB_FIRST;
126
127	/*
128	 * This SPI controller seems to be tested on SPI flash only and some
129	 * bits are swizzled under other SPI modes probably due to incorrect
130	 * wiring inside the silicon. Only mode 0 works correctly.
131	 */
132	reg &= ~(MT7621_CPHA | MT7621_CPOL);
133
134	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
135
136	return 0;
137}
138
139static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
140{
141	int i;
142
143	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
144		u32 status;
145
146		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
147		if ((status & SPITRANS_BUSY) == 0)
148			return 0;
149		cpu_relax();
150		udelay(1);
151	}
152
153	return -ETIMEDOUT;
154}
155
156static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
157					int rx_len, u8 *buf)
158{
159	int tx_len;
160
161	/*
162	 * Combine with any pending write, and perform one or more half-duplex
163	 * transactions reading 'len' bytes. Data to be written is already in
164	 * MT7621_SPI_DATA.
165	 */
166	tx_len = rs->pending_write;
167	rs->pending_write = 0;
168
169	while (rx_len || tx_len) {
170		int i;
171		u32 val = (min(tx_len, 4) * 8) << 24;
172		int rx = min(rx_len, 32);
173
174		if (tx_len > 4)
175			val |= (tx_len - 4) * 8;
176		val |= (rx * 8) << 12;
177		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
178
179		tx_len = 0;
180
181		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
182		val |= SPI_CTL_START;
183		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
184
185		mt7621_spi_wait_till_ready(rs);
186
187		for (i = 0; i < rx; i++) {
188			if ((i % 4) == 0)
189				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
190			*buf++ = val & 0xff;
191			val >>= 8;
192		}
193
194		rx_len -= i;
195	}
196}
197
198static inline void mt7621_spi_flush(struct mt7621_spi *rs)
199{
200	mt7621_spi_read_half_duplex(rs, 0, NULL);
201}
202
203static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
204					 int tx_len, const u8 *buf)
205{
206	int len = rs->pending_write;
207	int val = 0;
208
209	if (len & 3) {
210		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
211		if (len < 4) {
212			val <<= (4 - len) * 8;
213			val = swab32(val);
214		}
215	}
216
217	while (tx_len > 0) {
218		if (len >= 36) {
219			rs->pending_write = len;
220			mt7621_spi_flush(rs);
221			len = 0;
222		}
223
224		val |= *buf++ << (8 * (len & 3));
225		len++;
226		if ((len & 3) == 0) {
227			if (len == 4)
228				/* The byte-order of the opcode is weird! */
229				val = swab32(val);
230			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
231			val = 0;
232		}
233		tx_len -= 1;
234	}
235
236	if (len & 3) {
237		if (len < 4) {
238			val = swab32(val);
239			val >>= (4 - len) * 8;
240		}
241		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
242	}
243
244	rs->pending_write = len;
245}
246
247static int mt7621_spi_transfer_one_message(struct spi_controller *master,
248					   struct spi_message *m)
249{
250	struct mt7621_spi *rs = spi_controller_get_devdata(master);
251	struct spi_device *spi = m->spi;
252	unsigned int speed = spi->max_speed_hz;
253	struct spi_transfer *t = NULL;
254	int status = 0;
255
256	mt7621_spi_wait_till_ready(rs);
257
258	list_for_each_entry(t, &m->transfers, transfer_list)
259		if (t->speed_hz < speed)
260			speed = t->speed_hz;
261
262	if (mt7621_spi_prepare(spi, speed)) {
263		status = -EIO;
264		goto msg_done;
265	}
266
267	/* Assert CS */
268	mt7621_spi_set_cs(spi, 1);
269
270	m->actual_length = 0;
271	list_for_each_entry(t, &m->transfers, transfer_list) {
272		if ((t->rx_buf) && (t->tx_buf)) {
273			/*
274			 * This controller will shift some extra data out
275			 * of spi_opcode if (mosi_bit_cnt > 0) &&
276			 * (cmd_bit_cnt == 0). So the claimed full-duplex
277			 * support is broken since we have no way to read
278			 * the MISO value during that bit.
279			 */
280			status = -EIO;
281			goto msg_done;
282		} else if (t->rx_buf) {
283			mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
284		} else if (t->tx_buf) {
285			mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
286		}
287		m->actual_length += t->len;
288	}
289
290	/* Flush data and deassert CS */
291	mt7621_spi_flush(rs);
292	mt7621_spi_set_cs(spi, 0);
293
294msg_done:
295	m->status = status;
296	spi_finalize_current_message(master);
297
298	return 0;
299}
300
301static int mt7621_spi_setup(struct spi_device *spi)
302{
303	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
304
305	if ((spi->max_speed_hz == 0) ||
306	    (spi->max_speed_hz > (rs->sys_freq / 2)))
307		spi->max_speed_hz = rs->sys_freq / 2;
308
309	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
310		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
311			spi->max_speed_hz);
312		return -EINVAL;
313	}
314
315	return 0;
316}
317
318static const struct of_device_id mt7621_spi_match[] = {
319	{ .compatible = "ralink,mt7621-spi" },
320	{},
321};
322MODULE_DEVICE_TABLE(of, mt7621_spi_match);
323
324static int mt7621_spi_probe(struct platform_device *pdev)
325{
326	const struct of_device_id *match;
327	struct spi_controller *master;
328	struct mt7621_spi *rs;
329	void __iomem *base;
330	int status = 0;
331	struct clk *clk;
332	int ret;
333
334	match = of_match_device(mt7621_spi_match, &pdev->dev);
335	if (!match)
336		return -EINVAL;
337
338	base = devm_platform_ioremap_resource(pdev, 0);
339	if (IS_ERR(base))
340		return PTR_ERR(base);
341
342	clk = devm_clk_get(&pdev->dev, NULL);
343	if (IS_ERR(clk))
344		return dev_err_probe(&pdev->dev, PTR_ERR(clk),
345				     "unable to get SYS clock\n");
346
347	status = clk_prepare_enable(clk);
348	if (status)
349		return status;
350
351	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
352	if (!master) {
353		dev_info(&pdev->dev, "master allocation failed\n");
354		clk_disable_unprepare(clk);
355		return -ENOMEM;
356	}
357
358	master->mode_bits = SPI_LSB_FIRST;
359	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
360	master->setup = mt7621_spi_setup;
361	master->transfer_one_message = mt7621_spi_transfer_one_message;
362	master->bits_per_word_mask = SPI_BPW_MASK(8);
363	master->dev.of_node = pdev->dev.of_node;
364	master->num_chipselect = 2;
365
366	dev_set_drvdata(&pdev->dev, master);
367
368	rs = spi_controller_get_devdata(master);
369	rs->base = base;
370	rs->clk = clk;
371	rs->master = master;
372	rs->sys_freq = clk_get_rate(rs->clk);
373	rs->pending_write = 0;
374	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
375
376	ret = device_reset(&pdev->dev);
377	if (ret) {
378		dev_err(&pdev->dev, "SPI reset failed!\n");
379		clk_disable_unprepare(clk);
380		return ret;
381	}
382
383	ret = spi_register_controller(master);
384	if (ret)
385		clk_disable_unprepare(clk);
386
387	return ret;
388}
389
390static int mt7621_spi_remove(struct platform_device *pdev)
391{
392	struct spi_controller *master;
393	struct mt7621_spi *rs;
394
395	master = dev_get_drvdata(&pdev->dev);
396	rs = spi_controller_get_devdata(master);
397
398	spi_unregister_controller(master);
399	clk_disable_unprepare(rs->clk);
400
401	return 0;
402}
403
404MODULE_ALIAS("platform:" DRIVER_NAME);
405
406static struct platform_driver mt7621_spi_driver = {
407	.driver = {
408		.name = DRIVER_NAME,
409		.of_match_table = mt7621_spi_match,
410	},
411	.probe = mt7621_spi_probe,
412	.remove = mt7621_spi_remove,
413};
414
415module_platform_driver(mt7621_spi_driver);
416
417MODULE_DESCRIPTION("MT7621 SPI driver");
418MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
419MODULE_LICENSE("GPL");
420