1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Leilk Liu <leilk.liu@mediatek.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/device.h> 9#include <linux/err.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/ioport.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_gpio.h> 16#include <linux/platform_device.h> 17#include <linux/platform_data/spi-mt65xx.h> 18#include <linux/pm_runtime.h> 19#include <linux/spi/spi.h> 20#include <linux/dma-mapping.h> 21 22#define SPI_CFG0_REG 0x0000 23#define SPI_CFG1_REG 0x0004 24#define SPI_TX_SRC_REG 0x0008 25#define SPI_RX_DST_REG 0x000c 26#define SPI_TX_DATA_REG 0x0010 27#define SPI_RX_DATA_REG 0x0014 28#define SPI_CMD_REG 0x0018 29#define SPI_STATUS0_REG 0x001c 30#define SPI_PAD_SEL_REG 0x0024 31#define SPI_CFG2_REG 0x0028 32#define SPI_TX_SRC_REG_64 0x002c 33#define SPI_RX_DST_REG_64 0x0030 34 35#define SPI_CFG0_SCK_HIGH_OFFSET 0 36#define SPI_CFG0_SCK_LOW_OFFSET 8 37#define SPI_CFG0_CS_HOLD_OFFSET 16 38#define SPI_CFG0_CS_SETUP_OFFSET 24 39#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 40#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 41 42#define SPI_CFG1_CS_IDLE_OFFSET 0 43#define SPI_CFG1_PACKET_LOOP_OFFSET 8 44#define SPI_CFG1_PACKET_LENGTH_OFFSET 16 45#define SPI_CFG1_GET_TICK_DLY_OFFSET 30 46 47#define SPI_CFG1_CS_IDLE_MASK 0xff 48#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 49#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 50#define SPI_CFG2_SCK_HIGH_OFFSET 0 51#define SPI_CFG2_SCK_LOW_OFFSET 16 52 53#define SPI_CMD_ACT BIT(0) 54#define SPI_CMD_RESUME BIT(1) 55#define SPI_CMD_RST BIT(2) 56#define SPI_CMD_PAUSE_EN BIT(4) 57#define SPI_CMD_DEASSERT BIT(5) 58#define SPI_CMD_SAMPLE_SEL BIT(6) 59#define SPI_CMD_CS_POL BIT(7) 60#define SPI_CMD_CPHA BIT(8) 61#define SPI_CMD_CPOL BIT(9) 62#define SPI_CMD_RX_DMA BIT(10) 63#define SPI_CMD_TX_DMA BIT(11) 64#define SPI_CMD_TXMSBF BIT(12) 65#define SPI_CMD_RXMSBF BIT(13) 66#define SPI_CMD_RX_ENDIAN BIT(14) 67#define SPI_CMD_TX_ENDIAN BIT(15) 68#define SPI_CMD_FINISH_IE BIT(16) 69#define SPI_CMD_PAUSE_IE BIT(17) 70 71#define MT8173_SPI_MAX_PAD_SEL 3 72 73#define MTK_SPI_PAUSE_INT_STATUS 0x2 74 75#define MTK_SPI_IDLE 0 76#define MTK_SPI_PAUSED 1 77 78#define MTK_SPI_MAX_FIFO_SIZE 32U 79#define MTK_SPI_PACKET_SIZE 1024 80#define MTK_SPI_32BITS_MASK (0xffffffff) 81 82#define DMA_ADDR_EXT_BITS (36) 83#define DMA_ADDR_DEF_BITS (32) 84 85struct mtk_spi_compatible { 86 bool need_pad_sel; 87 /* Must explicitly send dummy Tx bytes to do Rx only transfer */ 88 bool must_tx; 89 /* some IC design adjust cfg register to enhance time accuracy */ 90 bool enhance_timing; 91 /* some IC support DMA addr extension */ 92 bool dma_ext; 93}; 94 95struct mtk_spi { 96 void __iomem *base; 97 u32 state; 98 int pad_num; 99 u32 *pad_sel; 100 struct clk *parent_clk, *sel_clk, *spi_clk; 101 struct spi_transfer *cur_transfer; 102 u32 xfer_len; 103 u32 num_xfered; 104 struct scatterlist *tx_sgl, *rx_sgl; 105 u32 tx_sgl_len, rx_sgl_len; 106 const struct mtk_spi_compatible *dev_comp; 107}; 108 109static const struct mtk_spi_compatible mtk_common_compat; 110 111static const struct mtk_spi_compatible mt2712_compat = { 112 .must_tx = true, 113}; 114 115static const struct mtk_spi_compatible mt6765_compat = { 116 .need_pad_sel = true, 117 .must_tx = true, 118 .enhance_timing = true, 119 .dma_ext = true, 120}; 121 122static const struct mtk_spi_compatible mt7622_compat = { 123 .must_tx = true, 124 .enhance_timing = true, 125}; 126 127static const struct mtk_spi_compatible mt8173_compat = { 128 .need_pad_sel = true, 129 .must_tx = true, 130}; 131 132static const struct mtk_spi_compatible mt8183_compat = { 133 .need_pad_sel = true, 134 .must_tx = true, 135 .enhance_timing = true, 136}; 137 138/* 139 * A piece of default chip info unless the platform 140 * supplies it. 141 */ 142static const struct mtk_chip_config mtk_default_chip_info = { 143 .sample_sel = 0, 144}; 145 146static const struct of_device_id mtk_spi_of_match[] = { 147 { .compatible = "mediatek,mt2701-spi", 148 .data = (void *)&mtk_common_compat, 149 }, 150 { .compatible = "mediatek,mt2712-spi", 151 .data = (void *)&mt2712_compat, 152 }, 153 { .compatible = "mediatek,mt6589-spi", 154 .data = (void *)&mtk_common_compat, 155 }, 156 { .compatible = "mediatek,mt6765-spi", 157 .data = (void *)&mt6765_compat, 158 }, 159 { .compatible = "mediatek,mt7622-spi", 160 .data = (void *)&mt7622_compat, 161 }, 162 { .compatible = "mediatek,mt7629-spi", 163 .data = (void *)&mt7622_compat, 164 }, 165 { .compatible = "mediatek,mt8135-spi", 166 .data = (void *)&mtk_common_compat, 167 }, 168 { .compatible = "mediatek,mt8173-spi", 169 .data = (void *)&mt8173_compat, 170 }, 171 { .compatible = "mediatek,mt8183-spi", 172 .data = (void *)&mt8183_compat, 173 }, 174 { .compatible = "mediatek,mt8192-spi", 175 .data = (void *)&mt6765_compat, 176 }, 177 {} 178}; 179MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 180 181static void mtk_spi_reset(struct mtk_spi *mdata) 182{ 183 u32 reg_val; 184 185 /* set the software reset bit in SPI_CMD_REG. */ 186 reg_val = readl(mdata->base + SPI_CMD_REG); 187 reg_val |= SPI_CMD_RST; 188 writel(reg_val, mdata->base + SPI_CMD_REG); 189 190 reg_val = readl(mdata->base + SPI_CMD_REG); 191 reg_val &= ~SPI_CMD_RST; 192 writel(reg_val, mdata->base + SPI_CMD_REG); 193} 194 195static int mtk_spi_prepare_message(struct spi_master *master, 196 struct spi_message *msg) 197{ 198 u16 cpha, cpol; 199 u32 reg_val; 200 struct spi_device *spi = msg->spi; 201 struct mtk_chip_config *chip_config = spi->controller_data; 202 struct mtk_spi *mdata = spi_master_get_devdata(master); 203 204 cpha = spi->mode & SPI_CPHA ? 1 : 0; 205 cpol = spi->mode & SPI_CPOL ? 1 : 0; 206 207 reg_val = readl(mdata->base + SPI_CMD_REG); 208 if (cpha) 209 reg_val |= SPI_CMD_CPHA; 210 else 211 reg_val &= ~SPI_CMD_CPHA; 212 if (cpol) 213 reg_val |= SPI_CMD_CPOL; 214 else 215 reg_val &= ~SPI_CMD_CPOL; 216 217 /* set the mlsbx and mlsbtx */ 218 if (spi->mode & SPI_LSB_FIRST) { 219 reg_val &= ~SPI_CMD_TXMSBF; 220 reg_val &= ~SPI_CMD_RXMSBF; 221 } else { 222 reg_val |= SPI_CMD_TXMSBF; 223 reg_val |= SPI_CMD_RXMSBF; 224 } 225 226 /* set the tx/rx endian */ 227#ifdef __LITTLE_ENDIAN 228 reg_val &= ~SPI_CMD_TX_ENDIAN; 229 reg_val &= ~SPI_CMD_RX_ENDIAN; 230#else 231 reg_val |= SPI_CMD_TX_ENDIAN; 232 reg_val |= SPI_CMD_RX_ENDIAN; 233#endif 234 235 if (mdata->dev_comp->enhance_timing) { 236 /* set CS polarity */ 237 if (spi->mode & SPI_CS_HIGH) 238 reg_val |= SPI_CMD_CS_POL; 239 else 240 reg_val &= ~SPI_CMD_CS_POL; 241 242 if (chip_config->sample_sel) 243 reg_val |= SPI_CMD_SAMPLE_SEL; 244 else 245 reg_val &= ~SPI_CMD_SAMPLE_SEL; 246 } 247 248 /* set finish and pause interrupt always enable */ 249 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 250 251 /* disable dma mode */ 252 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 253 254 /* disable deassert mode */ 255 reg_val &= ~SPI_CMD_DEASSERT; 256 257 writel(reg_val, mdata->base + SPI_CMD_REG); 258 259 /* pad select */ 260 if (mdata->dev_comp->need_pad_sel) 261 writel(mdata->pad_sel[spi->chip_select], 262 mdata->base + SPI_PAD_SEL_REG); 263 264 return 0; 265} 266 267static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 268{ 269 u32 reg_val; 270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 271 272 if (spi->mode & SPI_CS_HIGH) 273 enable = !enable; 274 275 reg_val = readl(mdata->base + SPI_CMD_REG); 276 if (!enable) { 277 reg_val |= SPI_CMD_PAUSE_EN; 278 writel(reg_val, mdata->base + SPI_CMD_REG); 279 } else { 280 reg_val &= ~SPI_CMD_PAUSE_EN; 281 writel(reg_val, mdata->base + SPI_CMD_REG); 282 mdata->state = MTK_SPI_IDLE; 283 mtk_spi_reset(mdata); 284 } 285} 286 287static void mtk_spi_prepare_transfer(struct spi_master *master, 288 struct spi_transfer *xfer) 289{ 290 u32 spi_clk_hz, div, sck_time, cs_time, reg_val; 291 struct mtk_spi *mdata = spi_master_get_devdata(master); 292 293 spi_clk_hz = clk_get_rate(mdata->spi_clk); 294 if (xfer->speed_hz < spi_clk_hz / 2) 295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); 296 else 297 div = 1; 298 299 sck_time = (div + 1) / 2; 300 cs_time = sck_time * 2; 301 302 if (mdata->dev_comp->enhance_timing) { 303 reg_val = (((sck_time - 1) & 0xffff) 304 << SPI_CFG2_SCK_HIGH_OFFSET); 305 reg_val |= (((sck_time - 1) & 0xffff) 306 << SPI_CFG2_SCK_LOW_OFFSET); 307 writel(reg_val, mdata->base + SPI_CFG2_REG); 308 reg_val = (((cs_time - 1) & 0xffff) 309 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 310 reg_val |= (((cs_time - 1) & 0xffff) 311 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 312 writel(reg_val, mdata->base + SPI_CFG0_REG); 313 } else { 314 reg_val = (((sck_time - 1) & 0xff) 315 << SPI_CFG0_SCK_HIGH_OFFSET); 316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 317 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 318 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); 319 writel(reg_val, mdata->base + SPI_CFG0_REG); 320 } 321 322 reg_val = readl(mdata->base + SPI_CFG1_REG); 323 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 324 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 325 writel(reg_val, mdata->base + SPI_CFG1_REG); 326} 327 328static void mtk_spi_setup_packet(struct spi_master *master) 329{ 330 u32 packet_size, packet_loop, reg_val; 331 struct mtk_spi *mdata = spi_master_get_devdata(master); 332 333 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); 334 packet_loop = mdata->xfer_len / packet_size; 335 336 reg_val = readl(mdata->base + SPI_CFG1_REG); 337 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); 338 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 339 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 340 writel(reg_val, mdata->base + SPI_CFG1_REG); 341} 342 343static void mtk_spi_enable_transfer(struct spi_master *master) 344{ 345 u32 cmd; 346 struct mtk_spi *mdata = spi_master_get_devdata(master); 347 348 cmd = readl(mdata->base + SPI_CMD_REG); 349 if (mdata->state == MTK_SPI_IDLE) 350 cmd |= SPI_CMD_ACT; 351 else 352 cmd |= SPI_CMD_RESUME; 353 writel(cmd, mdata->base + SPI_CMD_REG); 354} 355 356static int mtk_spi_get_mult_delta(u32 xfer_len) 357{ 358 u32 mult_delta; 359 360 if (xfer_len > MTK_SPI_PACKET_SIZE) 361 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 362 else 363 mult_delta = 0; 364 365 return mult_delta; 366} 367 368static void mtk_spi_update_mdata_len(struct spi_master *master) 369{ 370 int mult_delta; 371 struct mtk_spi *mdata = spi_master_get_devdata(master); 372 373 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 374 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 375 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 376 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 377 mdata->rx_sgl_len = mult_delta; 378 mdata->tx_sgl_len -= mdata->xfer_len; 379 } else { 380 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 381 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 382 mdata->tx_sgl_len = mult_delta; 383 mdata->rx_sgl_len -= mdata->xfer_len; 384 } 385 } else if (mdata->tx_sgl_len) { 386 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 387 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 388 mdata->tx_sgl_len = mult_delta; 389 } else if (mdata->rx_sgl_len) { 390 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 391 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 392 mdata->rx_sgl_len = mult_delta; 393 } 394} 395 396static void mtk_spi_setup_dma_addr(struct spi_master *master, 397 struct spi_transfer *xfer) 398{ 399 struct mtk_spi *mdata = spi_master_get_devdata(master); 400 401 if (mdata->tx_sgl) { 402 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), 403 mdata->base + SPI_TX_SRC_REG); 404#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 405 if (mdata->dev_comp->dma_ext) 406 writel((u32)(xfer->tx_dma >> 32), 407 mdata->base + SPI_TX_SRC_REG_64); 408#endif 409 } 410 411 if (mdata->rx_sgl) { 412 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), 413 mdata->base + SPI_RX_DST_REG); 414#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 415 if (mdata->dev_comp->dma_ext) 416 writel((u32)(xfer->rx_dma >> 32), 417 mdata->base + SPI_RX_DST_REG_64); 418#endif 419 } 420} 421 422static int mtk_spi_fifo_transfer(struct spi_master *master, 423 struct spi_device *spi, 424 struct spi_transfer *xfer) 425{ 426 int cnt, remainder; 427 u32 reg_val; 428 struct mtk_spi *mdata = spi_master_get_devdata(master); 429 430 mdata->cur_transfer = xfer; 431 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); 432 mdata->num_xfered = 0; 433 mtk_spi_prepare_transfer(master, xfer); 434 mtk_spi_setup_packet(master); 435 436 if (xfer->tx_buf) { 437 cnt = xfer->len / 4; 438 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 439 remainder = xfer->len % 4; 440 if (remainder > 0) { 441 reg_val = 0; 442 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); 443 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 444 } 445 } 446 447 mtk_spi_enable_transfer(master); 448 449 return 1; 450} 451 452static int mtk_spi_dma_transfer(struct spi_master *master, 453 struct spi_device *spi, 454 struct spi_transfer *xfer) 455{ 456 int cmd; 457 struct mtk_spi *mdata = spi_master_get_devdata(master); 458 459 mdata->tx_sgl = NULL; 460 mdata->rx_sgl = NULL; 461 mdata->tx_sgl_len = 0; 462 mdata->rx_sgl_len = 0; 463 mdata->cur_transfer = xfer; 464 mdata->num_xfered = 0; 465 466 mtk_spi_prepare_transfer(master, xfer); 467 468 cmd = readl(mdata->base + SPI_CMD_REG); 469 if (xfer->tx_buf) 470 cmd |= SPI_CMD_TX_DMA; 471 if (xfer->rx_buf) 472 cmd |= SPI_CMD_RX_DMA; 473 writel(cmd, mdata->base + SPI_CMD_REG); 474 475 if (xfer->tx_buf) 476 mdata->tx_sgl = xfer->tx_sg.sgl; 477 if (xfer->rx_buf) 478 mdata->rx_sgl = xfer->rx_sg.sgl; 479 480 if (mdata->tx_sgl) { 481 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 482 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 483 } 484 if (mdata->rx_sgl) { 485 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 486 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 487 } 488 489 mtk_spi_update_mdata_len(master); 490 mtk_spi_setup_packet(master); 491 mtk_spi_setup_dma_addr(master, xfer); 492 mtk_spi_enable_transfer(master); 493 494 return 1; 495} 496 497static int mtk_spi_transfer_one(struct spi_master *master, 498 struct spi_device *spi, 499 struct spi_transfer *xfer) 500{ 501 if (master->can_dma(master, spi, xfer)) 502 return mtk_spi_dma_transfer(master, spi, xfer); 503 else 504 return mtk_spi_fifo_transfer(master, spi, xfer); 505} 506 507static bool mtk_spi_can_dma(struct spi_master *master, 508 struct spi_device *spi, 509 struct spi_transfer *xfer) 510{ 511 /* Buffers for DMA transactions must be 4-byte aligned */ 512 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && 513 (unsigned long)xfer->tx_buf % 4 == 0 && 514 (unsigned long)xfer->rx_buf % 4 == 0); 515} 516 517static int mtk_spi_setup(struct spi_device *spi) 518{ 519 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 520 521 if (!spi->controller_data) 522 spi->controller_data = (void *)&mtk_default_chip_info; 523 524 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) 525 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 526 527 return 0; 528} 529 530static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 531{ 532 u32 cmd, reg_val, cnt, remainder, len; 533 struct spi_master *master = dev_id; 534 struct mtk_spi *mdata = spi_master_get_devdata(master); 535 struct spi_transfer *trans = mdata->cur_transfer; 536 537 reg_val = readl(mdata->base + SPI_STATUS0_REG); 538 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 539 mdata->state = MTK_SPI_PAUSED; 540 else 541 mdata->state = MTK_SPI_IDLE; 542 543 if (!master->can_dma(master, NULL, trans)) { 544 if (trans->rx_buf) { 545 cnt = mdata->xfer_len / 4; 546 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 547 trans->rx_buf + mdata->num_xfered, cnt); 548 remainder = mdata->xfer_len % 4; 549 if (remainder > 0) { 550 reg_val = readl(mdata->base + SPI_RX_DATA_REG); 551 memcpy(trans->rx_buf + 552 mdata->num_xfered + 553 (cnt * 4), 554 ®_val, 555 remainder); 556 } 557 } 558 559 mdata->num_xfered += mdata->xfer_len; 560 if (mdata->num_xfered == trans->len) { 561 spi_finalize_current_transfer(master); 562 return IRQ_HANDLED; 563 } 564 565 len = trans->len - mdata->num_xfered; 566 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); 567 mtk_spi_setup_packet(master); 568 569 cnt = mdata->xfer_len / 4; 570 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, 571 trans->tx_buf + mdata->num_xfered, cnt); 572 573 remainder = mdata->xfer_len % 4; 574 if (remainder > 0) { 575 reg_val = 0; 576 memcpy(®_val, 577 trans->tx_buf + (cnt * 4) + mdata->num_xfered, 578 remainder); 579 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 580 } 581 582 mtk_spi_enable_transfer(master); 583 584 return IRQ_HANDLED; 585 } 586 587 if (mdata->tx_sgl) 588 trans->tx_dma += mdata->xfer_len; 589 if (mdata->rx_sgl) 590 trans->rx_dma += mdata->xfer_len; 591 592 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 593 mdata->tx_sgl = sg_next(mdata->tx_sgl); 594 if (mdata->tx_sgl) { 595 trans->tx_dma = sg_dma_address(mdata->tx_sgl); 596 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 597 } 598 } 599 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 600 mdata->rx_sgl = sg_next(mdata->rx_sgl); 601 if (mdata->rx_sgl) { 602 trans->rx_dma = sg_dma_address(mdata->rx_sgl); 603 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 604 } 605 } 606 607 if (!mdata->tx_sgl && !mdata->rx_sgl) { 608 /* spi disable dma */ 609 cmd = readl(mdata->base + SPI_CMD_REG); 610 cmd &= ~SPI_CMD_TX_DMA; 611 cmd &= ~SPI_CMD_RX_DMA; 612 writel(cmd, mdata->base + SPI_CMD_REG); 613 614 spi_finalize_current_transfer(master); 615 return IRQ_HANDLED; 616 } 617 618 mtk_spi_update_mdata_len(master); 619 mtk_spi_setup_packet(master); 620 mtk_spi_setup_dma_addr(master, trans); 621 mtk_spi_enable_transfer(master); 622 623 return IRQ_HANDLED; 624} 625 626static int mtk_spi_probe(struct platform_device *pdev) 627{ 628 struct spi_master *master; 629 struct mtk_spi *mdata; 630 const struct of_device_id *of_id; 631 int i, irq, ret, addr_bits; 632 633 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 634 if (!master) { 635 dev_err(&pdev->dev, "failed to alloc spi master\n"); 636 return -ENOMEM; 637 } 638 639 master->auto_runtime_pm = true; 640 master->dev.of_node = pdev->dev.of_node; 641 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 642 643 master->set_cs = mtk_spi_set_cs; 644 master->prepare_message = mtk_spi_prepare_message; 645 master->transfer_one = mtk_spi_transfer_one; 646 master->can_dma = mtk_spi_can_dma; 647 master->setup = mtk_spi_setup; 648 649 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); 650 if (!of_id) { 651 dev_err(&pdev->dev, "failed to probe of_node\n"); 652 ret = -EINVAL; 653 goto err_put_master; 654 } 655 656 mdata = spi_master_get_devdata(master); 657 mdata->dev_comp = of_id->data; 658 659 if (mdata->dev_comp->enhance_timing) 660 master->mode_bits |= SPI_CS_HIGH; 661 662 if (mdata->dev_comp->must_tx) 663 master->flags = SPI_MASTER_MUST_TX; 664 665 if (mdata->dev_comp->need_pad_sel) { 666 mdata->pad_num = of_property_count_u32_elems( 667 pdev->dev.of_node, 668 "mediatek,pad-select"); 669 if (mdata->pad_num < 0) { 670 dev_err(&pdev->dev, 671 "No 'mediatek,pad-select' property\n"); 672 ret = -EINVAL; 673 goto err_put_master; 674 } 675 676 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, 677 sizeof(u32), GFP_KERNEL); 678 if (!mdata->pad_sel) { 679 ret = -ENOMEM; 680 goto err_put_master; 681 } 682 683 for (i = 0; i < mdata->pad_num; i++) { 684 of_property_read_u32_index(pdev->dev.of_node, 685 "mediatek,pad-select", 686 i, &mdata->pad_sel[i]); 687 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { 688 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", 689 i, mdata->pad_sel[i]); 690 ret = -EINVAL; 691 goto err_put_master; 692 } 693 } 694 } 695 696 platform_set_drvdata(pdev, master); 697 mdata->base = devm_platform_ioremap_resource(pdev, 0); 698 if (IS_ERR(mdata->base)) { 699 ret = PTR_ERR(mdata->base); 700 goto err_put_master; 701 } 702 703 irq = platform_get_irq(pdev, 0); 704 if (irq < 0) { 705 ret = irq; 706 goto err_put_master; 707 } 708 709 if (!pdev->dev.dma_mask) 710 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 711 712 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, 713 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); 714 if (ret) { 715 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); 716 goto err_put_master; 717 } 718 719 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); 720 if (IS_ERR(mdata->parent_clk)) { 721 ret = PTR_ERR(mdata->parent_clk); 722 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); 723 goto err_put_master; 724 } 725 726 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); 727 if (IS_ERR(mdata->sel_clk)) { 728 ret = PTR_ERR(mdata->sel_clk); 729 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); 730 goto err_put_master; 731 } 732 733 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); 734 if (IS_ERR(mdata->spi_clk)) { 735 ret = PTR_ERR(mdata->spi_clk); 736 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); 737 goto err_put_master; 738 } 739 740 ret = clk_prepare_enable(mdata->spi_clk); 741 if (ret < 0) { 742 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); 743 goto err_put_master; 744 } 745 746 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); 747 if (ret < 0) { 748 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); 749 clk_disable_unprepare(mdata->spi_clk); 750 goto err_put_master; 751 } 752 753 clk_disable_unprepare(mdata->spi_clk); 754 755 pm_runtime_enable(&pdev->dev); 756 757 ret = devm_spi_register_master(&pdev->dev, master); 758 if (ret) { 759 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); 760 goto err_disable_runtime_pm; 761 } 762 763 if (mdata->dev_comp->need_pad_sel) { 764 if (mdata->pad_num != master->num_chipselect) { 765 dev_err(&pdev->dev, 766 "pad_num does not match num_chipselect(%d != %d)\n", 767 mdata->pad_num, master->num_chipselect); 768 ret = -EINVAL; 769 goto err_disable_runtime_pm; 770 } 771 772 if (!master->cs_gpios && master->num_chipselect > 1) { 773 dev_err(&pdev->dev, 774 "cs_gpios not specified and num_chipselect > 1\n"); 775 ret = -EINVAL; 776 goto err_disable_runtime_pm; 777 } 778 779 if (master->cs_gpios) { 780 for (i = 0; i < master->num_chipselect; i++) { 781 ret = devm_gpio_request(&pdev->dev, 782 master->cs_gpios[i], 783 dev_name(&pdev->dev)); 784 if (ret) { 785 dev_err(&pdev->dev, 786 "can't get CS GPIO %i\n", i); 787 goto err_disable_runtime_pm; 788 } 789 } 790 } 791 } 792 793 if (mdata->dev_comp->dma_ext) 794 addr_bits = DMA_ADDR_EXT_BITS; 795 else 796 addr_bits = DMA_ADDR_DEF_BITS; 797 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); 798 if (ret) 799 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", 800 addr_bits, ret); 801 802 return 0; 803 804err_disable_runtime_pm: 805 pm_runtime_disable(&pdev->dev); 806err_put_master: 807 spi_master_put(master); 808 809 return ret; 810} 811 812static int mtk_spi_remove(struct platform_device *pdev) 813{ 814 struct spi_master *master = platform_get_drvdata(pdev); 815 struct mtk_spi *mdata = spi_master_get_devdata(master); 816 817 pm_runtime_disable(&pdev->dev); 818 819 mtk_spi_reset(mdata); 820 821 return 0; 822} 823 824#ifdef CONFIG_PM_SLEEP 825static int mtk_spi_suspend(struct device *dev) 826{ 827 int ret; 828 struct spi_master *master = dev_get_drvdata(dev); 829 struct mtk_spi *mdata = spi_master_get_devdata(master); 830 831 ret = spi_master_suspend(master); 832 if (ret) 833 return ret; 834 835 if (!pm_runtime_suspended(dev)) 836 clk_disable_unprepare(mdata->spi_clk); 837 838 return ret; 839} 840 841static int mtk_spi_resume(struct device *dev) 842{ 843 int ret; 844 struct spi_master *master = dev_get_drvdata(dev); 845 struct mtk_spi *mdata = spi_master_get_devdata(master); 846 847 if (!pm_runtime_suspended(dev)) { 848 ret = clk_prepare_enable(mdata->spi_clk); 849 if (ret < 0) { 850 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 851 return ret; 852 } 853 } 854 855 ret = spi_master_resume(master); 856 if (ret < 0) 857 clk_disable_unprepare(mdata->spi_clk); 858 859 return ret; 860} 861#endif /* CONFIG_PM_SLEEP */ 862 863#ifdef CONFIG_PM 864static int mtk_spi_runtime_suspend(struct device *dev) 865{ 866 struct spi_master *master = dev_get_drvdata(dev); 867 struct mtk_spi *mdata = spi_master_get_devdata(master); 868 869 clk_disable_unprepare(mdata->spi_clk); 870 871 return 0; 872} 873 874static int mtk_spi_runtime_resume(struct device *dev) 875{ 876 struct spi_master *master = dev_get_drvdata(dev); 877 struct mtk_spi *mdata = spi_master_get_devdata(master); 878 int ret; 879 880 ret = clk_prepare_enable(mdata->spi_clk); 881 if (ret < 0) { 882 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 883 return ret; 884 } 885 886 return 0; 887} 888#endif /* CONFIG_PM */ 889 890static const struct dev_pm_ops mtk_spi_pm = { 891 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 892 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 893 mtk_spi_runtime_resume, NULL) 894}; 895 896static struct platform_driver mtk_spi_driver = { 897 .driver = { 898 .name = "mtk-spi", 899 .pm = &mtk_spi_pm, 900 .of_match_table = mtk_spi_of_match, 901 }, 902 .probe = mtk_spi_probe, 903 .remove = mtk_spi_remove, 904}; 905 906module_platform_driver(mtk_spi_driver); 907 908MODULE_DESCRIPTION("MTK SPI Controller driver"); 909MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 910MODULE_LICENSE("GPL v2"); 911MODULE_ALIAS("platform:mtk-spi"); 912