1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4#include <linux/clk.h> 5#include <linux/interrupt.h> 6#include <linux/io.h> 7#include <linux/log2.h> 8#include <linux/module.h> 9#include <linux/platform_device.h> 10#include <linux/pm_opp.h> 11#include <linux/pm_runtime.h> 12#include <linux/qcom-geni-se.h> 13#include <linux/spi/spi.h> 14#include <linux/spinlock.h> 15 16/* SPI SE specific registers and respective register fields */ 17#define SE_SPI_CPHA 0x224 18#define CPHA BIT(0) 19 20#define SE_SPI_LOOPBACK 0x22c 21#define LOOPBACK_ENABLE 0x1 22#define NORMAL_MODE 0x0 23#define LOOPBACK_MSK GENMASK(1, 0) 24 25#define SE_SPI_CPOL 0x230 26#define CPOL BIT(2) 27 28#define SE_SPI_DEMUX_OUTPUT_INV 0x24c 29#define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 30 31#define SE_SPI_DEMUX_SEL 0x250 32#define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 33 34#define SE_SPI_TRANS_CFG 0x25c 35#define CS_TOGGLE BIT(1) 36 37#define SE_SPI_WORD_LEN 0x268 38#define WORD_LEN_MSK GENMASK(9, 0) 39#define MIN_WORD_LEN 4 40 41#define SE_SPI_TX_TRANS_LEN 0x26c 42#define SE_SPI_RX_TRANS_LEN 0x270 43#define TRANS_LEN_MSK GENMASK(23, 0) 44 45#define SE_SPI_PRE_POST_CMD_DLY 0x274 46 47#define SE_SPI_DELAY_COUNTERS 0x278 48#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 49#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 50#define SPI_CS_CLK_DELAY_SHFT 10 51 52/* M_CMD OP codes for SPI */ 53#define SPI_TX_ONLY 1 54#define SPI_RX_ONLY 2 55#define SPI_TX_RX 7 56#define SPI_CS_ASSERT 8 57#define SPI_CS_DEASSERT 9 58#define SPI_SCK_ONLY 10 59/* M_CMD params for SPI */ 60#define SPI_PRE_CMD_DELAY BIT(0) 61#define TIMESTAMP_BEFORE BIT(1) 62#define FRAGMENTATION BIT(2) 63#define TIMESTAMP_AFTER BIT(3) 64#define POST_CMD_DELAY BIT(4) 65 66struct spi_geni_master { 67 struct geni_se se; 68 struct device *dev; 69 u32 tx_fifo_depth; 70 u32 fifo_width_bits; 71 u32 tx_wm; 72 u32 last_mode; 73 unsigned long cur_speed_hz; 74 unsigned long cur_sclk_hz; 75 unsigned int cur_bits_per_word; 76 unsigned int tx_rem_bytes; 77 unsigned int rx_rem_bytes; 78 const struct spi_transfer *cur_xfer; 79 struct completion cs_done; 80 struct completion cancel_done; 81 struct completion abort_done; 82 unsigned int oversampling; 83 spinlock_t lock; 84 int irq; 85 bool cs_flag; 86 bool abort_failed; 87}; 88 89static int get_spi_clk_cfg(unsigned int speed_hz, 90 struct spi_geni_master *mas, 91 unsigned int *clk_idx, 92 unsigned int *clk_div) 93{ 94 unsigned long sclk_freq; 95 unsigned int actual_hz; 96 int ret; 97 98 ret = geni_se_clk_freq_match(&mas->se, 99 speed_hz * mas->oversampling, 100 clk_idx, &sclk_freq, false); 101 if (ret) { 102 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 103 ret, speed_hz); 104 return ret; 105 } 106 107 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 108 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 109 110 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 111 actual_hz, sclk_freq, *clk_idx, *clk_div); 112 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 113 if (ret) 114 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 115 else 116 mas->cur_sclk_hz = sclk_freq; 117 118 return ret; 119} 120 121static void handle_fifo_timeout(struct spi_master *spi, 122 struct spi_message *msg) 123{ 124 struct spi_geni_master *mas = spi_master_get_devdata(spi); 125 unsigned long time_left; 126 struct geni_se *se = &mas->se; 127 128 spin_lock_irq(&mas->lock); 129 reinit_completion(&mas->cancel_done); 130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 131 mas->cur_xfer = NULL; 132 geni_se_cancel_m_cmd(se); 133 spin_unlock_irq(&mas->lock); 134 135 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 136 if (time_left) 137 return; 138 139 spin_lock_irq(&mas->lock); 140 reinit_completion(&mas->abort_done); 141 geni_se_abort_m_cmd(se); 142 spin_unlock_irq(&mas->lock); 143 144 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 145 if (!time_left) { 146 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 147 148 /* 149 * No need for a lock since SPI core has a lock and we never 150 * access this from an interrupt. 151 */ 152 mas->abort_failed = true; 153 } 154} 155 156static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 157{ 158 struct geni_se *se = &mas->se; 159 u32 m_irq, m_irq_en; 160 161 if (!mas->abort_failed) 162 return false; 163 164 /* 165 * The only known case where a transfer times out and then a cancel 166 * times out then an abort times out is if something is blocking our 167 * interrupt handler from running. Avoid starting any new transfers 168 * until that sorts itself out. 169 */ 170 spin_lock_irq(&mas->lock); 171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 173 spin_unlock_irq(&mas->lock); 174 175 if (m_irq & m_irq_en) { 176 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 177 m_irq & m_irq_en); 178 return true; 179 } 180 181 /* 182 * If we're here the problem resolved itself so no need to check more 183 * on future transfers. 184 */ 185 mas->abort_failed = false; 186 187 return false; 188} 189 190static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) 191{ 192 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 193 struct spi_master *spi = dev_get_drvdata(mas->dev); 194 struct geni_se *se = &mas->se; 195 unsigned long time_left; 196 197 if (!(slv->mode & SPI_CS_HIGH)) 198 set_flag = !set_flag; 199 200 if (set_flag == mas->cs_flag) 201 return; 202 203 pm_runtime_get_sync(mas->dev); 204 205 if (spi_geni_is_abort_still_pending(mas)) { 206 dev_err(mas->dev, "Can't set chip select\n"); 207 goto exit; 208 } 209 210 mas->cs_flag = set_flag; 211 212 spin_lock_irq(&mas->lock); 213 reinit_completion(&mas->cs_done); 214 if (set_flag) 215 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); 216 else 217 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); 218 spin_unlock_irq(&mas->lock); 219 220 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 221 if (!time_left) 222 handle_fifo_timeout(spi, NULL); 223 224exit: 225 pm_runtime_put(mas->dev); 226} 227 228static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 229 unsigned int bits_per_word) 230{ 231 unsigned int pack_words; 232 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 233 struct geni_se *se = &mas->se; 234 u32 word_len; 235 236 /* 237 * If bits_per_word isn't a byte aligned value, set the packing to be 238 * 1 SPI word per FIFO word. 239 */ 240 if (!(mas->fifo_width_bits % bits_per_word)) 241 pack_words = mas->fifo_width_bits / bits_per_word; 242 else 243 pack_words = 1; 244 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 245 true, true); 246 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 247 writel(word_len, se->base + SE_SPI_WORD_LEN); 248} 249 250static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 251 unsigned long clk_hz) 252{ 253 u32 clk_sel, m_clk_cfg, idx, div; 254 struct geni_se *se = &mas->se; 255 int ret; 256 257 if (clk_hz == mas->cur_speed_hz) 258 return 0; 259 260 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 261 if (ret) { 262 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 263 return ret; 264 } 265 266 /* 267 * SPI core clock gets configured with the requested frequency 268 * or the frequency closer to the requested frequency. 269 * For that reason requested frequency is stored in the 270 * cur_speed_hz and referred in the consecutive transfer instead 271 * of calling clk_get_rate() API. 272 */ 273 mas->cur_speed_hz = clk_hz; 274 275 clk_sel = idx & CLK_SEL_MSK; 276 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 277 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 278 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 279 280 /* Set BW quota for CPU as driver supports FIFO mode only. */ 281 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 282 ret = geni_icc_set_bw(se); 283 if (ret) 284 return ret; 285 286 return 0; 287} 288 289static int setup_fifo_params(struct spi_device *spi_slv, 290 struct spi_master *spi) 291{ 292 struct spi_geni_master *mas = spi_master_get_devdata(spi); 293 struct geni_se *se = &mas->se; 294 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; 295 u32 demux_sel; 296 297 if (mas->last_mode != spi_slv->mode) { 298 if (spi_slv->mode & SPI_LOOP) 299 loopback_cfg = LOOPBACK_ENABLE; 300 301 if (spi_slv->mode & SPI_CPOL) 302 cpol = CPOL; 303 304 if (spi_slv->mode & SPI_CPHA) 305 cpha = CPHA; 306 307 if (spi_slv->mode & SPI_CS_HIGH) 308 demux_output_inv = BIT(spi_slv->chip_select); 309 310 demux_sel = spi_slv->chip_select; 311 mas->cur_bits_per_word = spi_slv->bits_per_word; 312 313 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); 314 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); 315 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); 316 writel(cpha, se->base + SE_SPI_CPHA); 317 writel(cpol, se->base + SE_SPI_CPOL); 318 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); 319 320 mas->last_mode = spi_slv->mode; 321 } 322 323 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); 324} 325 326static int spi_geni_prepare_message(struct spi_master *spi, 327 struct spi_message *spi_msg) 328{ 329 int ret; 330 struct spi_geni_master *mas = spi_master_get_devdata(spi); 331 332 if (spi_geni_is_abort_still_pending(mas)) 333 return -EBUSY; 334 335 ret = setup_fifo_params(spi_msg->spi, spi); 336 if (ret) 337 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 338 return ret; 339} 340 341static int spi_geni_init(struct spi_geni_master *mas) 342{ 343 struct geni_se *se = &mas->se; 344 unsigned int proto, major, minor, ver; 345 u32 spi_tx_cfg; 346 347 pm_runtime_get_sync(mas->dev); 348 349 proto = geni_se_read_proto(se); 350 if (proto != GENI_SE_SPI) { 351 dev_err(mas->dev, "Invalid proto %d\n", proto); 352 pm_runtime_put(mas->dev); 353 return -ENXIO; 354 } 355 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 356 357 /* Width of Tx and Rx FIFO is same */ 358 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 359 360 /* 361 * Hardware programming guide suggests to configure 362 * RX FIFO RFR level to fifo_depth-2. 363 */ 364 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 365 /* Transmit an entire FIFO worth of data per IRQ */ 366 mas->tx_wm = 1; 367 ver = geni_se_get_qup_hw_version(se); 368 major = GENI_SE_VERSION_MAJOR(ver); 369 minor = GENI_SE_VERSION_MINOR(ver); 370 371 if (major == 1 && minor == 0) 372 mas->oversampling = 2; 373 else 374 mas->oversampling = 1; 375 376 geni_se_select_mode(se, GENI_SE_FIFO); 377 378 /* We always control CS manually */ 379 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 380 spi_tx_cfg &= ~CS_TOGGLE; 381 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 382 383 pm_runtime_put(mas->dev); 384 return 0; 385} 386 387static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 388{ 389 /* 390 * Calculate how many bytes we'll put in each FIFO word. If the 391 * transfer words don't pack cleanly into a FIFO word we'll just put 392 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 393 */ 394 if (mas->fifo_width_bits % mas->cur_bits_per_word) 395 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 396 BITS_PER_BYTE)); 397 398 return mas->fifo_width_bits / BITS_PER_BYTE; 399} 400 401static bool geni_spi_handle_tx(struct spi_geni_master *mas) 402{ 403 struct geni_se *se = &mas->se; 404 unsigned int max_bytes; 405 const u8 *tx_buf; 406 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 407 unsigned int i = 0; 408 409 /* Stop the watermark IRQ if nothing to send */ 410 if (!mas->cur_xfer) { 411 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 412 return false; 413 } 414 415 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 416 if (mas->tx_rem_bytes < max_bytes) 417 max_bytes = mas->tx_rem_bytes; 418 419 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 420 while (i < max_bytes) { 421 unsigned int j; 422 unsigned int bytes_to_write; 423 u32 fifo_word = 0; 424 u8 *fifo_byte = (u8 *)&fifo_word; 425 426 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 427 for (j = 0; j < bytes_to_write; j++) 428 fifo_byte[j] = tx_buf[i++]; 429 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 430 } 431 mas->tx_rem_bytes -= max_bytes; 432 if (!mas->tx_rem_bytes) { 433 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 434 return false; 435 } 436 return true; 437} 438 439static void geni_spi_handle_rx(struct spi_geni_master *mas) 440{ 441 struct geni_se *se = &mas->se; 442 u32 rx_fifo_status; 443 unsigned int rx_bytes; 444 unsigned int rx_last_byte_valid; 445 u8 *rx_buf; 446 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 447 unsigned int i = 0; 448 449 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 450 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 451 if (rx_fifo_status & RX_LAST) { 452 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 453 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 454 if (rx_last_byte_valid && rx_last_byte_valid < 4) 455 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 456 } 457 458 /* Clear out the FIFO and bail if nowhere to put it */ 459 if (!mas->cur_xfer) { 460 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 461 readl(se->base + SE_GENI_RX_FIFOn); 462 return; 463 } 464 465 if (mas->rx_rem_bytes < rx_bytes) 466 rx_bytes = mas->rx_rem_bytes; 467 468 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 469 while (i < rx_bytes) { 470 u32 fifo_word = 0; 471 u8 *fifo_byte = (u8 *)&fifo_word; 472 unsigned int bytes_to_read; 473 unsigned int j; 474 475 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 476 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 477 for (j = 0; j < bytes_to_read; j++) 478 rx_buf[i++] = fifo_byte[j]; 479 } 480 mas->rx_rem_bytes -= rx_bytes; 481} 482 483static void setup_fifo_xfer(struct spi_transfer *xfer, 484 struct spi_geni_master *mas, 485 u16 mode, struct spi_master *spi) 486{ 487 u32 m_cmd = 0; 488 u32 len; 489 struct geni_se *se = &mas->se; 490 int ret; 491 492 /* 493 * Ensure that our interrupt handler isn't still running from some 494 * prior command before we start messing with the hardware behind 495 * its back. We don't need to _keep_ the lock here since we're only 496 * worried about racing with out interrupt handler. The SPI core 497 * already handles making sure that we're not trying to do two 498 * transfers at once or setting a chip select and doing a transfer 499 * concurrently. 500 * 501 * NOTE: we actually _can't_ hold the lock here because possibly we 502 * might call clk_set_rate() which needs to be able to sleep. 503 */ 504 spin_lock_irq(&mas->lock); 505 spin_unlock_irq(&mas->lock); 506 507 if (xfer->bits_per_word != mas->cur_bits_per_word) { 508 spi_setup_word_len(mas, mode, xfer->bits_per_word); 509 mas->cur_bits_per_word = xfer->bits_per_word; 510 } 511 512 /* Speed and bits per word can be overridden per transfer */ 513 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 514 if (ret) 515 return; 516 517 mas->tx_rem_bytes = 0; 518 mas->rx_rem_bytes = 0; 519 520 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) 521 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; 522 else 523 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); 524 len &= TRANS_LEN_MSK; 525 526 mas->cur_xfer = xfer; 527 if (xfer->tx_buf) { 528 m_cmd |= SPI_TX_ONLY; 529 mas->tx_rem_bytes = xfer->len; 530 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 531 } 532 533 if (xfer->rx_buf) { 534 m_cmd |= SPI_RX_ONLY; 535 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 536 mas->rx_rem_bytes = xfer->len; 537 } 538 539 /* 540 * Lock around right before we start the transfer since our 541 * interrupt could come in at any time now. 542 */ 543 spin_lock_irq(&mas->lock); 544 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 545 546 /* 547 * TX_WATERMARK_REG should be set after SPI configuration and 548 * setting up GENI SE engine, as driver starts data transfer 549 * for the watermark interrupt. 550 */ 551 if (m_cmd & SPI_TX_ONLY) { 552 if (geni_spi_handle_tx(mas)) 553 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 554 } 555 spin_unlock_irq(&mas->lock); 556} 557 558static int spi_geni_transfer_one(struct spi_master *spi, 559 struct spi_device *slv, 560 struct spi_transfer *xfer) 561{ 562 struct spi_geni_master *mas = spi_master_get_devdata(spi); 563 564 if (spi_geni_is_abort_still_pending(mas)) 565 return -EBUSY; 566 567 /* Terminate and return success for 0 byte length transfer */ 568 if (!xfer->len) 569 return 0; 570 571 setup_fifo_xfer(xfer, mas, slv->mode, spi); 572 return 1; 573} 574 575static irqreturn_t geni_spi_isr(int irq, void *data) 576{ 577 struct spi_master *spi = data; 578 struct spi_geni_master *mas = spi_master_get_devdata(spi); 579 struct geni_se *se = &mas->se; 580 u32 m_irq; 581 582 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 583 if (!m_irq) 584 return IRQ_NONE; 585 586 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 587 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 588 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 589 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 590 591 spin_lock(&mas->lock); 592 593 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 594 geni_spi_handle_rx(mas); 595 596 if (m_irq & M_TX_FIFO_WATERMARK_EN) 597 geni_spi_handle_tx(mas); 598 599 if (m_irq & M_CMD_DONE_EN) { 600 if (mas->cur_xfer) { 601 spi_finalize_current_transfer(spi); 602 mas->cur_xfer = NULL; 603 /* 604 * If this happens, then a CMD_DONE came before all the 605 * Tx buffer bytes were sent out. This is unusual, log 606 * this condition and disable the WM interrupt to 607 * prevent the system from stalling due an interrupt 608 * storm. 609 * 610 * If this happens when all Rx bytes haven't been 611 * received, log the condition. The only known time 612 * this can happen is if bits_per_word != 8 and some 613 * registers that expect xfer lengths in num spi_words 614 * weren't written correctly. 615 */ 616 if (mas->tx_rem_bytes) { 617 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 618 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 619 mas->tx_rem_bytes, mas->cur_bits_per_word); 620 } 621 if (mas->rx_rem_bytes) 622 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 623 mas->rx_rem_bytes, mas->cur_bits_per_word); 624 } else { 625 complete(&mas->cs_done); 626 } 627 } 628 629 if (m_irq & M_CMD_CANCEL_EN) 630 complete(&mas->cancel_done); 631 if (m_irq & M_CMD_ABORT_EN) 632 complete(&mas->abort_done); 633 634 /* 635 * It's safe or a good idea to Ack all of our our interrupts at the 636 * end of the function. Specifically: 637 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 638 * clearing Acks. Clearing at the end relies on nobody else having 639 * started a new transfer yet or else we could be clearing _their_ 640 * done bit, but everyone grabs the spinlock before starting a new 641 * transfer. 642 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 643 * to be "latched level" interrupts so it's important to clear them 644 * _after_ you've handled the condition and always safe to do so 645 * since they'll re-assert if they're still happening. 646 */ 647 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 648 649 spin_unlock(&mas->lock); 650 651 return IRQ_HANDLED; 652} 653 654static int spi_geni_probe(struct platform_device *pdev) 655{ 656 int ret, irq; 657 struct spi_master *spi; 658 struct spi_geni_master *mas; 659 void __iomem *base; 660 struct clk *clk; 661 struct device *dev = &pdev->dev; 662 663 irq = platform_get_irq(pdev, 0); 664 if (irq < 0) 665 return irq; 666 667 base = devm_platform_ioremap_resource(pdev, 0); 668 if (IS_ERR(base)) 669 return PTR_ERR(base); 670 671 clk = devm_clk_get(dev, "se"); 672 if (IS_ERR(clk)) 673 return PTR_ERR(clk); 674 675 spi = devm_spi_alloc_master(dev, sizeof(*mas)); 676 if (!spi) 677 return -ENOMEM; 678 679 platform_set_drvdata(pdev, spi); 680 mas = spi_master_get_devdata(spi); 681 mas->irq = irq; 682 mas->dev = dev; 683 mas->se.dev = dev; 684 mas->se.wrapper = dev_get_drvdata(dev->parent); 685 mas->se.base = base; 686 mas->se.clk = clk; 687 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); 688 if (IS_ERR(mas->se.opp_table)) 689 return PTR_ERR(mas->se.opp_table); 690 /* OPP table is optional */ 691 ret = dev_pm_opp_of_add_table(&pdev->dev); 692 if (ret && ret != -ENODEV) { 693 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 694 goto put_clkname; 695 } 696 697 spi->bus_num = -1; 698 spi->dev.of_node = dev->of_node; 699 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 700 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 701 spi->num_chipselect = 4; 702 spi->max_speed_hz = 50000000; 703 spi->prepare_message = spi_geni_prepare_message; 704 spi->transfer_one = spi_geni_transfer_one; 705 spi->auto_runtime_pm = true; 706 spi->handle_err = handle_fifo_timeout; 707 spi->set_cs = spi_geni_set_cs; 708 709 init_completion(&mas->cs_done); 710 init_completion(&mas->cancel_done); 711 init_completion(&mas->abort_done); 712 spin_lock_init(&mas->lock); 713 pm_runtime_use_autosuspend(&pdev->dev); 714 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 715 pm_runtime_enable(dev); 716 717 ret = geni_icc_get(&mas->se, NULL); 718 if (ret) 719 goto spi_geni_probe_runtime_disable; 720 /* Set the bus quota to a reasonable value for register access */ 721 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 722 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 723 724 ret = geni_icc_set_bw(&mas->se); 725 if (ret) 726 goto spi_geni_probe_runtime_disable; 727 728 ret = spi_geni_init(mas); 729 if (ret) 730 goto spi_geni_probe_runtime_disable; 731 732 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 733 if (ret) 734 goto spi_geni_probe_runtime_disable; 735 736 ret = spi_register_master(spi); 737 if (ret) 738 goto spi_geni_probe_free_irq; 739 740 return 0; 741spi_geni_probe_free_irq: 742 free_irq(mas->irq, spi); 743spi_geni_probe_runtime_disable: 744 pm_runtime_disable(dev); 745 dev_pm_opp_of_remove_table(&pdev->dev); 746put_clkname: 747 dev_pm_opp_put_clkname(mas->se.opp_table); 748 return ret; 749} 750 751static int spi_geni_remove(struct platform_device *pdev) 752{ 753 struct spi_master *spi = platform_get_drvdata(pdev); 754 struct spi_geni_master *mas = spi_master_get_devdata(spi); 755 756 /* Unregister _before_ disabling pm_runtime() so we stop transfers */ 757 spi_unregister_master(spi); 758 759 free_irq(mas->irq, spi); 760 pm_runtime_disable(&pdev->dev); 761 dev_pm_opp_of_remove_table(&pdev->dev); 762 dev_pm_opp_put_clkname(mas->se.opp_table); 763 return 0; 764} 765 766static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 767{ 768 struct spi_master *spi = dev_get_drvdata(dev); 769 struct spi_geni_master *mas = spi_master_get_devdata(spi); 770 int ret; 771 772 /* Drop the performance state vote */ 773 dev_pm_opp_set_rate(dev, 0); 774 775 ret = geni_se_resources_off(&mas->se); 776 if (ret) 777 return ret; 778 779 return geni_icc_disable(&mas->se); 780} 781 782static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 783{ 784 struct spi_master *spi = dev_get_drvdata(dev); 785 struct spi_geni_master *mas = spi_master_get_devdata(spi); 786 int ret; 787 788 ret = geni_icc_enable(&mas->se); 789 if (ret) 790 return ret; 791 792 ret = geni_se_resources_on(&mas->se); 793 if (ret) 794 return ret; 795 796 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 797} 798 799static int __maybe_unused spi_geni_suspend(struct device *dev) 800{ 801 struct spi_master *spi = dev_get_drvdata(dev); 802 int ret; 803 804 ret = spi_master_suspend(spi); 805 if (ret) 806 return ret; 807 808 ret = pm_runtime_force_suspend(dev); 809 if (ret) 810 spi_master_resume(spi); 811 812 return ret; 813} 814 815static int __maybe_unused spi_geni_resume(struct device *dev) 816{ 817 struct spi_master *spi = dev_get_drvdata(dev); 818 int ret; 819 820 ret = pm_runtime_force_resume(dev); 821 if (ret) 822 return ret; 823 824 ret = spi_master_resume(spi); 825 if (ret) 826 pm_runtime_force_suspend(dev); 827 828 return ret; 829} 830 831static const struct dev_pm_ops spi_geni_pm_ops = { 832 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 833 spi_geni_runtime_resume, NULL) 834 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 835}; 836 837static const struct of_device_id spi_geni_dt_match[] = { 838 { .compatible = "qcom,geni-spi" }, 839 {} 840}; 841MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 842 843static struct platform_driver spi_geni_driver = { 844 .probe = spi_geni_probe, 845 .remove = spi_geni_remove, 846 .driver = { 847 .name = "geni_spi", 848 .pm = &spi_geni_pm_ops, 849 .of_match_table = spi_geni_dt_match, 850 }, 851}; 852module_platform_driver(spi_geni_driver); 853 854MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 855MODULE_LICENSE("GPL v2"); 856