1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/regmap.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi-fsl-dspi.h>
21
22#define DRIVER_NAME			"fsl-dspi"
23
24#define SPI_MCR				0x00
25#define SPI_MCR_MASTER			BIT(31)
26#define SPI_MCR_PCSIS(x)		((x) << 16)
27#define SPI_MCR_CLR_TXF			BIT(11)
28#define SPI_MCR_CLR_RXF			BIT(10)
29#define SPI_MCR_XSPI			BIT(3)
30#define SPI_MCR_DIS_TXF			BIT(13)
31#define SPI_MCR_DIS_RXF			BIT(12)
32#define SPI_MCR_HALT			BIT(0)
33
34#define SPI_TCR				0x08
35#define SPI_TCR_GET_TCNT(x)		(((x) & GENMASK(31, 16)) >> 16)
36
37#define SPI_CTAR(x)			(0x0c + (((x) & GENMASK(1, 0)) * 4))
38#define SPI_CTAR_FMSZ(x)		(((x) << 27) & GENMASK(30, 27))
39#define SPI_CTAR_CPOL			BIT(26)
40#define SPI_CTAR_CPHA			BIT(25)
41#define SPI_CTAR_LSBFE			BIT(24)
42#define SPI_CTAR_PCSSCK(x)		(((x) << 22) & GENMASK(23, 22))
43#define SPI_CTAR_PASC(x)		(((x) << 20) & GENMASK(21, 20))
44#define SPI_CTAR_PDT(x)			(((x) << 18) & GENMASK(19, 18))
45#define SPI_CTAR_PBR(x)			(((x) << 16) & GENMASK(17, 16))
46#define SPI_CTAR_CSSCK(x)		(((x) << 12) & GENMASK(15, 12))
47#define SPI_CTAR_ASC(x)			(((x) << 8) & GENMASK(11, 8))
48#define SPI_CTAR_DT(x)			(((x) << 4) & GENMASK(7, 4))
49#define SPI_CTAR_BR(x)			((x) & GENMASK(3, 0))
50#define SPI_CTAR_SCALE_BITS		0xf
51
52#define SPI_CTAR0_SLAVE			0x0c
53
54#define SPI_SR				0x2c
55#define SPI_SR_TCFQF			BIT(31)
56#define SPI_SR_TFUF			BIT(27)
57#define SPI_SR_TFFF			BIT(25)
58#define SPI_SR_CMDTCF			BIT(23)
59#define SPI_SR_SPEF			BIT(21)
60#define SPI_SR_RFOF			BIT(19)
61#define SPI_SR_TFIWF			BIT(18)
62#define SPI_SR_RFDF			BIT(17)
63#define SPI_SR_CMDFFF			BIT(16)
64#define SPI_SR_CLEAR			(SPI_SR_TCFQF | \
65					SPI_SR_TFUF | SPI_SR_TFFF | \
66					SPI_SR_CMDTCF | SPI_SR_SPEF | \
67					SPI_SR_RFOF | SPI_SR_TFIWF | \
68					SPI_SR_RFDF | SPI_SR_CMDFFF)
69
70#define SPI_RSER_TFFFE			BIT(25)
71#define SPI_RSER_TFFFD			BIT(24)
72#define SPI_RSER_RFDFE			BIT(17)
73#define SPI_RSER_RFDFD			BIT(16)
74
75#define SPI_RSER			0x30
76#define SPI_RSER_TCFQE			BIT(31)
77#define SPI_RSER_CMDTCFE		BIT(23)
78
79#define SPI_PUSHR			0x34
80#define SPI_PUSHR_CMD_CONT		BIT(15)
81#define SPI_PUSHR_CMD_CTAS(x)		(((x) << 12 & GENMASK(14, 12)))
82#define SPI_PUSHR_CMD_EOQ		BIT(11)
83#define SPI_PUSHR_CMD_CTCNT		BIT(10)
84#define SPI_PUSHR_CMD_PCS(x)		(BIT(x) & GENMASK(5, 0))
85
86#define SPI_PUSHR_SLAVE			0x34
87
88#define SPI_POPR			0x38
89
90#define SPI_TXFR0			0x3c
91#define SPI_TXFR1			0x40
92#define SPI_TXFR2			0x44
93#define SPI_TXFR3			0x48
94#define SPI_RXFR0			0x7c
95#define SPI_RXFR1			0x80
96#define SPI_RXFR2			0x84
97#define SPI_RXFR3			0x88
98
99#define SPI_CTARE(x)			(0x11c + (((x) & GENMASK(1, 0)) * 4))
100#define SPI_CTARE_FMSZE(x)		(((x) & 0x1) << 16)
101#define SPI_CTARE_DTCP(x)		((x) & 0x7ff)
102
103#define SPI_SREX			0x13c
104
105#define SPI_FRAME_BITS(bits)		SPI_CTAR_FMSZ((bits) - 1)
106#define SPI_FRAME_EBITS(bits)		SPI_CTARE_FMSZE(((bits) - 1) >> 4)
107
108#define DMA_COMPLETION_TIMEOUT		msecs_to_jiffies(3000)
109
110struct chip_data {
111	u32			ctar_val;
112};
113
114enum dspi_trans_mode {
115	DSPI_XSPI_MODE,
116	DSPI_DMA_MODE,
117};
118
119struct fsl_dspi_devtype_data {
120	enum dspi_trans_mode	trans_mode;
121	u8			max_clock_factor;
122	int			fifo_size;
123};
124
125enum {
126	LS1021A,
127	LS1012A,
128	LS1028A,
129	LS1043A,
130	LS1046A,
131	LS2080A,
132	LS2085A,
133	LX2160A,
134	MCF5441X,
135	VF610,
136};
137
138static const struct fsl_dspi_devtype_data devtype_data[] = {
139	[VF610] = {
140		.trans_mode		= DSPI_DMA_MODE,
141		.max_clock_factor	= 2,
142		.fifo_size		= 4,
143	},
144	[LS1021A] = {
145		/* Has A-011218 DMA erratum */
146		.trans_mode		= DSPI_XSPI_MODE,
147		.max_clock_factor	= 8,
148		.fifo_size		= 4,
149	},
150	[LS1012A] = {
151		/* Has A-011218 DMA erratum */
152		.trans_mode		= DSPI_XSPI_MODE,
153		.max_clock_factor	= 8,
154		.fifo_size		= 16,
155	},
156	[LS1028A] = {
157		.trans_mode		= DSPI_XSPI_MODE,
158		.max_clock_factor	= 8,
159		.fifo_size		= 4,
160	},
161	[LS1043A] = {
162		/* Has A-011218 DMA erratum */
163		.trans_mode		= DSPI_XSPI_MODE,
164		.max_clock_factor	= 8,
165		.fifo_size		= 16,
166	},
167	[LS1046A] = {
168		/* Has A-011218 DMA erratum */
169		.trans_mode		= DSPI_XSPI_MODE,
170		.max_clock_factor	= 8,
171		.fifo_size		= 16,
172	},
173	[LS2080A] = {
174		.trans_mode		= DSPI_XSPI_MODE,
175		.max_clock_factor	= 8,
176		.fifo_size		= 4,
177	},
178	[LS2085A] = {
179		.trans_mode		= DSPI_XSPI_MODE,
180		.max_clock_factor	= 8,
181		.fifo_size		= 4,
182	},
183	[LX2160A] = {
184		.trans_mode		= DSPI_XSPI_MODE,
185		.max_clock_factor	= 8,
186		.fifo_size		= 4,
187	},
188	[MCF5441X] = {
189		.trans_mode		= DSPI_DMA_MODE,
190		.max_clock_factor	= 8,
191		.fifo_size		= 16,
192	},
193};
194
195struct fsl_dspi_dma {
196	u32					*tx_dma_buf;
197	struct dma_chan				*chan_tx;
198	dma_addr_t				tx_dma_phys;
199	struct completion			cmd_tx_complete;
200	struct dma_async_tx_descriptor		*tx_desc;
201
202	u32					*rx_dma_buf;
203	struct dma_chan				*chan_rx;
204	dma_addr_t				rx_dma_phys;
205	struct completion			cmd_rx_complete;
206	struct dma_async_tx_descriptor		*rx_desc;
207};
208
209struct fsl_dspi {
210	struct spi_controller			*ctlr;
211	struct platform_device			*pdev;
212
213	struct regmap				*regmap;
214	struct regmap				*regmap_pushr;
215	int					irq;
216	struct clk				*clk;
217
218	struct spi_transfer			*cur_transfer;
219	struct spi_message			*cur_msg;
220	struct chip_data			*cur_chip;
221	size_t					progress;
222	size_t					len;
223	const void				*tx;
224	void					*rx;
225	u16					tx_cmd;
226	const struct fsl_dspi_devtype_data	*devtype_data;
227
228	struct completion			xfer_done;
229
230	struct fsl_dspi_dma			*dma;
231
232	int					oper_word_size;
233	int					oper_bits_per_word;
234
235	int					words_in_flight;
236
237	/*
238	 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
239	 * individually (in XSPI mode)
240	 */
241	int					pushr_cmd;
242	int					pushr_tx;
243
244	void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
245	void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
246};
247
248static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
249{
250	switch (dspi->oper_word_size) {
251	case 1:
252		*txdata = *(u8 *)dspi->tx;
253		break;
254	case 2:
255		*txdata = *(u16 *)dspi->tx;
256		break;
257	case 4:
258		*txdata = *(u32 *)dspi->tx;
259		break;
260	}
261	dspi->tx += dspi->oper_word_size;
262}
263
264static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
265{
266	switch (dspi->oper_word_size) {
267	case 1:
268		*(u8 *)dspi->rx = rxdata;
269		break;
270	case 2:
271		*(u16 *)dspi->rx = rxdata;
272		break;
273	case 4:
274		*(u32 *)dspi->rx = rxdata;
275		break;
276	}
277	dspi->rx += dspi->oper_word_size;
278}
279
280static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
281{
282	*txdata = cpu_to_be32(*(u32 *)dspi->tx);
283	dspi->tx += sizeof(u32);
284}
285
286static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
287{
288	*(u32 *)dspi->rx = be32_to_cpu(rxdata);
289	dspi->rx += sizeof(u32);
290}
291
292static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
293{
294	*txdata = cpu_to_be16(*(u16 *)dspi->tx);
295	dspi->tx += sizeof(u16);
296}
297
298static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
299{
300	*(u16 *)dspi->rx = be16_to_cpu(rxdata);
301	dspi->rx += sizeof(u16);
302}
303
304static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
305{
306	u16 hi = *(u16 *)dspi->tx;
307	u16 lo = *(u16 *)(dspi->tx + 2);
308
309	*txdata = (u32)hi << 16 | lo;
310	dspi->tx += sizeof(u32);
311}
312
313static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
314{
315	u16 hi = rxdata & 0xffff;
316	u16 lo = rxdata >> 16;
317
318	*(u16 *)dspi->rx = lo;
319	*(u16 *)(dspi->rx + 2) = hi;
320	dspi->rx += sizeof(u32);
321}
322
323/*
324 * Pop one word from the TX buffer for pushing into the
325 * PUSHR register (TX FIFO)
326 */
327static u32 dspi_pop_tx(struct fsl_dspi *dspi)
328{
329	u32 txdata = 0;
330
331	if (dspi->tx)
332		dspi->host_to_dev(dspi, &txdata);
333	dspi->len -= dspi->oper_word_size;
334	return txdata;
335}
336
337/* Prepare one TX FIFO entry (txdata plus cmd) */
338static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
339{
340	u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
341
342	if (spi_controller_is_slave(dspi->ctlr))
343		return data;
344
345	if (dspi->len > 0)
346		cmd |= SPI_PUSHR_CMD_CONT;
347	return cmd << 16 | data;
348}
349
350/* Push one word to the RX buffer from the POPR register (RX FIFO) */
351static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
352{
353	if (!dspi->rx)
354		return;
355	dspi->dev_to_host(dspi, rxdata);
356}
357
358static void dspi_tx_dma_callback(void *arg)
359{
360	struct fsl_dspi *dspi = arg;
361	struct fsl_dspi_dma *dma = dspi->dma;
362
363	complete(&dma->cmd_tx_complete);
364}
365
366static void dspi_rx_dma_callback(void *arg)
367{
368	struct fsl_dspi *dspi = arg;
369	struct fsl_dspi_dma *dma = dspi->dma;
370	int i;
371
372	if (dspi->rx) {
373		for (i = 0; i < dspi->words_in_flight; i++)
374			dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
375	}
376
377	complete(&dma->cmd_rx_complete);
378}
379
380static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
381{
382	struct device *dev = &dspi->pdev->dev;
383	struct fsl_dspi_dma *dma = dspi->dma;
384	int time_left;
385	int i;
386
387	for (i = 0; i < dspi->words_in_flight; i++)
388		dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
389
390	dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
391					dma->tx_dma_phys,
392					dspi->words_in_flight *
393					DMA_SLAVE_BUSWIDTH_4_BYTES,
394					DMA_MEM_TO_DEV,
395					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
396	if (!dma->tx_desc) {
397		dev_err(dev, "Not able to get desc for DMA xfer\n");
398		return -EIO;
399	}
400
401	dma->tx_desc->callback = dspi_tx_dma_callback;
402	dma->tx_desc->callback_param = dspi;
403	if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
404		dev_err(dev, "DMA submit failed\n");
405		return -EINVAL;
406	}
407
408	dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
409					dma->rx_dma_phys,
410					dspi->words_in_flight *
411					DMA_SLAVE_BUSWIDTH_4_BYTES,
412					DMA_DEV_TO_MEM,
413					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
414	if (!dma->rx_desc) {
415		dev_err(dev, "Not able to get desc for DMA xfer\n");
416		return -EIO;
417	}
418
419	dma->rx_desc->callback = dspi_rx_dma_callback;
420	dma->rx_desc->callback_param = dspi;
421	if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
422		dev_err(dev, "DMA submit failed\n");
423		return -EINVAL;
424	}
425
426	reinit_completion(&dspi->dma->cmd_rx_complete);
427	reinit_completion(&dspi->dma->cmd_tx_complete);
428
429	dma_async_issue_pending(dma->chan_rx);
430	dma_async_issue_pending(dma->chan_tx);
431
432	if (spi_controller_is_slave(dspi->ctlr)) {
433		wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
434		return 0;
435	}
436
437	time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
438						DMA_COMPLETION_TIMEOUT);
439	if (time_left == 0) {
440		dev_err(dev, "DMA tx timeout\n");
441		dmaengine_terminate_all(dma->chan_tx);
442		dmaengine_terminate_all(dma->chan_rx);
443		return -ETIMEDOUT;
444	}
445
446	time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
447						DMA_COMPLETION_TIMEOUT);
448	if (time_left == 0) {
449		dev_err(dev, "DMA rx timeout\n");
450		dmaengine_terminate_all(dma->chan_tx);
451		dmaengine_terminate_all(dma->chan_rx);
452		return -ETIMEDOUT;
453	}
454
455	return 0;
456}
457
458static void dspi_setup_accel(struct fsl_dspi *dspi);
459
460static int dspi_dma_xfer(struct fsl_dspi *dspi)
461{
462	struct spi_message *message = dspi->cur_msg;
463	struct device *dev = &dspi->pdev->dev;
464	int ret = 0;
465
466	/*
467	 * dspi->len gets decremented by dspi_pop_tx_pushr in
468	 * dspi_next_xfer_dma_submit
469	 */
470	while (dspi->len) {
471		/* Figure out operational bits-per-word for this chunk */
472		dspi_setup_accel(dspi);
473
474		dspi->words_in_flight = dspi->len / dspi->oper_word_size;
475		if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
476			dspi->words_in_flight = dspi->devtype_data->fifo_size;
477
478		message->actual_length += dspi->words_in_flight *
479					  dspi->oper_word_size;
480
481		ret = dspi_next_xfer_dma_submit(dspi);
482		if (ret) {
483			dev_err(dev, "DMA transfer failed\n");
484			break;
485		}
486	}
487
488	return ret;
489}
490
491static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
492{
493	int dma_bufsize = dspi->devtype_data->fifo_size * 2;
494	struct device *dev = &dspi->pdev->dev;
495	struct dma_slave_config cfg;
496	struct fsl_dspi_dma *dma;
497	int ret;
498
499	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
500	if (!dma)
501		return -ENOMEM;
502
503	dma->chan_rx = dma_request_chan(dev, "rx");
504	if (IS_ERR(dma->chan_rx)) {
505		dev_err(dev, "rx dma channel not available\n");
506		ret = PTR_ERR(dma->chan_rx);
507		return ret;
508	}
509
510	dma->chan_tx = dma_request_chan(dev, "tx");
511	if (IS_ERR(dma->chan_tx)) {
512		dev_err(dev, "tx dma channel not available\n");
513		ret = PTR_ERR(dma->chan_tx);
514		goto err_tx_channel;
515	}
516
517	dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
518					     dma_bufsize, &dma->tx_dma_phys,
519					     GFP_KERNEL);
520	if (!dma->tx_dma_buf) {
521		ret = -ENOMEM;
522		goto err_tx_dma_buf;
523	}
524
525	dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
526					     dma_bufsize, &dma->rx_dma_phys,
527					     GFP_KERNEL);
528	if (!dma->rx_dma_buf) {
529		ret = -ENOMEM;
530		goto err_rx_dma_buf;
531	}
532
533	memset(&cfg, 0, sizeof(cfg));
534	cfg.src_addr = phy_addr + SPI_POPR;
535	cfg.dst_addr = phy_addr + SPI_PUSHR;
536	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
537	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
538	cfg.src_maxburst = 1;
539	cfg.dst_maxburst = 1;
540
541	cfg.direction = DMA_DEV_TO_MEM;
542	ret = dmaengine_slave_config(dma->chan_rx, &cfg);
543	if (ret) {
544		dev_err(dev, "can't configure rx dma channel\n");
545		ret = -EINVAL;
546		goto err_slave_config;
547	}
548
549	cfg.direction = DMA_MEM_TO_DEV;
550	ret = dmaengine_slave_config(dma->chan_tx, &cfg);
551	if (ret) {
552		dev_err(dev, "can't configure tx dma channel\n");
553		ret = -EINVAL;
554		goto err_slave_config;
555	}
556
557	dspi->dma = dma;
558	init_completion(&dma->cmd_tx_complete);
559	init_completion(&dma->cmd_rx_complete);
560
561	return 0;
562
563err_slave_config:
564	dma_free_coherent(dma->chan_rx->device->dev,
565			  dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
566err_rx_dma_buf:
567	dma_free_coherent(dma->chan_tx->device->dev,
568			  dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
569err_tx_dma_buf:
570	dma_release_channel(dma->chan_tx);
571err_tx_channel:
572	dma_release_channel(dma->chan_rx);
573
574	devm_kfree(dev, dma);
575	dspi->dma = NULL;
576
577	return ret;
578}
579
580static void dspi_release_dma(struct fsl_dspi *dspi)
581{
582	int dma_bufsize = dspi->devtype_data->fifo_size * 2;
583	struct fsl_dspi_dma *dma = dspi->dma;
584
585	if (!dma)
586		return;
587
588	if (dma->chan_tx) {
589		dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
590				  dma->tx_dma_buf, dma->tx_dma_phys);
591		dma_release_channel(dma->chan_tx);
592	}
593
594	if (dma->chan_rx) {
595		dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
596				  dma->rx_dma_buf, dma->rx_dma_phys);
597		dma_release_channel(dma->chan_rx);
598	}
599}
600
601static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
602			   unsigned long clkrate)
603{
604	/* Valid baud rate pre-scaler values */
605	int pbr_tbl[4] = {2, 3, 5, 7};
606	int brs[16] = {	2,	4,	6,	8,
607			16,	32,	64,	128,
608			256,	512,	1024,	2048,
609			4096,	8192,	16384,	32768 };
610	int scale_needed, scale, minscale = INT_MAX;
611	int i, j;
612
613	scale_needed = clkrate / speed_hz;
614	if (clkrate % speed_hz)
615		scale_needed++;
616
617	for (i = 0; i < ARRAY_SIZE(brs); i++)
618		for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
619			scale = brs[i] * pbr_tbl[j];
620			if (scale >= scale_needed) {
621				if (scale < minscale) {
622					minscale = scale;
623					*br = i;
624					*pbr = j;
625				}
626				break;
627			}
628		}
629
630	if (minscale == INT_MAX) {
631		pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
632			speed_hz, clkrate);
633		*pbr = ARRAY_SIZE(pbr_tbl) - 1;
634		*br =  ARRAY_SIZE(brs) - 1;
635	}
636}
637
638static void ns_delay_scale(char *psc, char *sc, int delay_ns,
639			   unsigned long clkrate)
640{
641	int scale_needed, scale, minscale = INT_MAX;
642	int pscale_tbl[4] = {1, 3, 5, 7};
643	u32 remainder;
644	int i, j;
645
646	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
647				   &remainder);
648	if (remainder)
649		scale_needed++;
650
651	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
652		for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
653			scale = pscale_tbl[i] * (2 << j);
654			if (scale >= scale_needed) {
655				if (scale < minscale) {
656					minscale = scale;
657					*psc = i;
658					*sc = j;
659				}
660				break;
661			}
662		}
663
664	if (minscale == INT_MAX) {
665		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
666			delay_ns, clkrate);
667		*psc = ARRAY_SIZE(pscale_tbl) - 1;
668		*sc = SPI_CTAR_SCALE_BITS;
669	}
670}
671
672static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
673{
674	/*
675	 * The only time when the PCS doesn't need continuation after this word
676	 * is when it's last. We need to look ahead, because we actually call
677	 * dspi_pop_tx (the function that decrements dspi->len) _after_
678	 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
679	 * word is enough. If there's more to transmit than that,
680	 * dspi_xspi_write will know to split the FIFO writes in 2, and
681	 * generate a new PUSHR command with the final word that will have PCS
682	 * deasserted (not continued) here.
683	 */
684	if (dspi->len > dspi->oper_word_size)
685		cmd |= SPI_PUSHR_CMD_CONT;
686	regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
687}
688
689static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
690{
691	regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
692}
693
694static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
695{
696	int num_bytes = num_words * dspi->oper_word_size;
697	u16 tx_cmd = dspi->tx_cmd;
698
699	/*
700	 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
701	 * and cs_change does not want the PCS to stay on), then we need a new
702	 * PUSHR command, since this one (for the body of the buffer)
703	 * necessarily has the CONT bit set.
704	 * So send one word less during this go, to force a split and a command
705	 * with a single word next time, when CONT will be unset.
706	 */
707	if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
708		tx_cmd |= SPI_PUSHR_CMD_EOQ;
709
710	/* Update CTARE */
711	regmap_write(dspi->regmap, SPI_CTARE(0),
712		     SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
713		     SPI_CTARE_DTCP(num_words));
714
715	/*
716	 * Write the CMD FIFO entry first, and then the two
717	 * corresponding TX FIFO entries (or one...).
718	 */
719	dspi_pushr_cmd_write(dspi, tx_cmd);
720
721	/* Fill TX FIFO with as many transfers as possible */
722	while (num_words--) {
723		u32 data = dspi_pop_tx(dspi);
724
725		dspi_pushr_txdata_write(dspi, data & 0xFFFF);
726		if (dspi->oper_bits_per_word > 16)
727			dspi_pushr_txdata_write(dspi, data >> 16);
728	}
729}
730
731static u32 dspi_popr_read(struct fsl_dspi *dspi)
732{
733	u32 rxdata = 0;
734
735	regmap_read(dspi->regmap, SPI_POPR, &rxdata);
736	return rxdata;
737}
738
739static void dspi_fifo_read(struct fsl_dspi *dspi)
740{
741	int num_fifo_entries = dspi->words_in_flight;
742
743	/* Read one FIFO entry and push to rx buffer */
744	while (num_fifo_entries--)
745		dspi_push_rx(dspi, dspi_popr_read(dspi));
746}
747
748static void dspi_setup_accel(struct fsl_dspi *dspi)
749{
750	struct spi_transfer *xfer = dspi->cur_transfer;
751	bool odd = !!(dspi->len & 1);
752
753	/* No accel for frames not multiple of 8 bits at the moment */
754	if (xfer->bits_per_word % 8)
755		goto no_accel;
756
757	if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
758		dspi->oper_bits_per_word = 16;
759	} else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
760		dspi->oper_bits_per_word = 8;
761	} else {
762		/* Start off with maximum supported by hardware */
763		if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
764			dspi->oper_bits_per_word = 32;
765		else
766			dspi->oper_bits_per_word = 16;
767
768		/*
769		 * And go down only if the buffer can't be sent with
770		 * words this big
771		 */
772		do {
773			if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
774				break;
775
776			dspi->oper_bits_per_word /= 2;
777		} while (dspi->oper_bits_per_word > 8);
778	}
779
780	if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
781		dspi->dev_to_host = dspi_8on32_dev_to_host;
782		dspi->host_to_dev = dspi_8on32_host_to_dev;
783	} else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
784		dspi->dev_to_host = dspi_8on16_dev_to_host;
785		dspi->host_to_dev = dspi_8on16_host_to_dev;
786	} else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
787		dspi->dev_to_host = dspi_16on32_dev_to_host;
788		dspi->host_to_dev = dspi_16on32_host_to_dev;
789	} else {
790no_accel:
791		dspi->dev_to_host = dspi_native_dev_to_host;
792		dspi->host_to_dev = dspi_native_host_to_dev;
793		dspi->oper_bits_per_word = xfer->bits_per_word;
794	}
795
796	dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
797
798	/*
799	 * Update CTAR here (code is common for XSPI and DMA modes).
800	 * We will update CTARE in the portion specific to XSPI, when we
801	 * also know the preload value (DTCP).
802	 */
803	regmap_write(dspi->regmap, SPI_CTAR(0),
804		     dspi->cur_chip->ctar_val |
805		     SPI_FRAME_BITS(dspi->oper_bits_per_word));
806}
807
808static void dspi_fifo_write(struct fsl_dspi *dspi)
809{
810	int num_fifo_entries = dspi->devtype_data->fifo_size;
811	struct spi_transfer *xfer = dspi->cur_transfer;
812	struct spi_message *msg = dspi->cur_msg;
813	int num_words, num_bytes;
814
815	dspi_setup_accel(dspi);
816
817	/* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
818	if (dspi->oper_word_size == 4)
819		num_fifo_entries /= 2;
820
821	/*
822	 * Integer division intentionally trims off odd (or non-multiple of 4)
823	 * numbers of bytes at the end of the buffer, which will be sent next
824	 * time using a smaller oper_word_size.
825	 */
826	num_words = dspi->len / dspi->oper_word_size;
827	if (num_words > num_fifo_entries)
828		num_words = num_fifo_entries;
829
830	/* Update total number of bytes that were transferred */
831	num_bytes = num_words * dspi->oper_word_size;
832	msg->actual_length += num_bytes;
833	dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
834
835	/*
836	 * Update shared variable for use in the next interrupt (both in
837	 * dspi_fifo_read and in dspi_fifo_write).
838	 */
839	dspi->words_in_flight = num_words;
840
841	spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
842
843	dspi_xspi_fifo_write(dspi, num_words);
844	/*
845	 * Everything after this point is in a potential race with the next
846	 * interrupt, so we must never use dspi->words_in_flight again since it
847	 * might already be modified by the next dspi_fifo_write.
848	 */
849
850	spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
851				dspi->progress, !dspi->irq);
852}
853
854static int dspi_rxtx(struct fsl_dspi *dspi)
855{
856	dspi_fifo_read(dspi);
857
858	if (!dspi->len)
859		/* Success! */
860		return 0;
861
862	dspi_fifo_write(dspi);
863
864	return -EINPROGRESS;
865}
866
867static int dspi_poll(struct fsl_dspi *dspi)
868{
869	int tries = 1000;
870	u32 spi_sr;
871
872	do {
873		regmap_read(dspi->regmap, SPI_SR, &spi_sr);
874		regmap_write(dspi->regmap, SPI_SR, spi_sr);
875
876		if (spi_sr & SPI_SR_CMDTCF)
877			break;
878	} while (--tries);
879
880	if (!tries)
881		return -ETIMEDOUT;
882
883	return dspi_rxtx(dspi);
884}
885
886static irqreturn_t dspi_interrupt(int irq, void *dev_id)
887{
888	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
889	u32 spi_sr;
890
891	regmap_read(dspi->regmap, SPI_SR, &spi_sr);
892	regmap_write(dspi->regmap, SPI_SR, spi_sr);
893
894	if (!(spi_sr & SPI_SR_CMDTCF))
895		return IRQ_NONE;
896
897	if (dspi_rxtx(dspi) == 0)
898		complete(&dspi->xfer_done);
899
900	return IRQ_HANDLED;
901}
902
903static int dspi_transfer_one_message(struct spi_controller *ctlr,
904				     struct spi_message *message)
905{
906	struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
907	struct spi_device *spi = message->spi;
908	struct spi_transfer *transfer;
909	int status = 0;
910
911	message->actual_length = 0;
912
913	list_for_each_entry(transfer, &message->transfers, transfer_list) {
914		dspi->cur_transfer = transfer;
915		dspi->cur_msg = message;
916		dspi->cur_chip = spi_get_ctldata(spi);
917		/* Prepare command word for CMD FIFO */
918		dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
919			       SPI_PUSHR_CMD_PCS(spi->chip_select);
920		if (list_is_last(&dspi->cur_transfer->transfer_list,
921				 &dspi->cur_msg->transfers)) {
922			/* Leave PCS activated after last transfer when
923			 * cs_change is set.
924			 */
925			if (transfer->cs_change)
926				dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
927		} else {
928			/* Keep PCS active between transfers in same message
929			 * when cs_change is not set, and de-activate PCS
930			 * between transfers in the same message when
931			 * cs_change is set.
932			 */
933			if (!transfer->cs_change)
934				dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
935		}
936
937		dspi->tx = transfer->tx_buf;
938		dspi->rx = transfer->rx_buf;
939		dspi->len = transfer->len;
940		dspi->progress = 0;
941
942		regmap_update_bits(dspi->regmap, SPI_MCR,
943				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
944				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
945
946		spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
947				       dspi->progress, !dspi->irq);
948
949		if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
950			status = dspi_dma_xfer(dspi);
951		} else {
952			dspi_fifo_write(dspi);
953
954			if (dspi->irq) {
955				wait_for_completion(&dspi->xfer_done);
956				reinit_completion(&dspi->xfer_done);
957			} else {
958				do {
959					status = dspi_poll(dspi);
960				} while (status == -EINPROGRESS);
961			}
962		}
963		if (status)
964			break;
965
966		spi_transfer_delay_exec(transfer);
967	}
968
969	message->status = status;
970	spi_finalize_current_message(ctlr);
971
972	return status;
973}
974
975static int dspi_setup(struct spi_device *spi)
976{
977	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
978	u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);
979	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
980	u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);
981	u32 cs_sck_delay = 0, sck_cs_delay = 0;
982	struct fsl_dspi_platform_data *pdata;
983	unsigned char pasc = 0, asc = 0;
984	struct chip_data *chip;
985	unsigned long clkrate;
986
987	/* Only alloc on first setup */
988	chip = spi_get_ctldata(spi);
989	if (chip == NULL) {
990		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
991		if (!chip)
992			return -ENOMEM;
993	}
994
995	pdata = dev_get_platdata(&dspi->pdev->dev);
996
997	if (!pdata) {
998		of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
999				     &cs_sck_delay);
1000
1001		of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1002				     &sck_cs_delay);
1003	} else {
1004		cs_sck_delay = pdata->cs_sck_delay;
1005		sck_cs_delay = pdata->sck_cs_delay;
1006	}
1007
1008	/* Since tCSC and tASC apply to continuous transfers too, avoid SCK
1009	 * glitches of half a cycle by never allowing tCSC + tASC to go below
1010	 * half a SCK period.
1011	 */
1012	if (cs_sck_delay < quarter_period_ns)
1013		cs_sck_delay = quarter_period_ns;
1014	if (sck_cs_delay < quarter_period_ns)
1015		sck_cs_delay = quarter_period_ns;
1016
1017	dev_dbg(&spi->dev,
1018		"DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
1019		cs_sck_delay, sck_cs_delay);
1020
1021	clkrate = clk_get_rate(dspi->clk);
1022	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1023
1024	/* Set PCS to SCK delay scale values */
1025	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1026
1027	/* Set After SCK delay scale values */
1028	ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1029
1030	chip->ctar_val = 0;
1031	if (spi->mode & SPI_CPOL)
1032		chip->ctar_val |= SPI_CTAR_CPOL;
1033	if (spi->mode & SPI_CPHA)
1034		chip->ctar_val |= SPI_CTAR_CPHA;
1035
1036	if (!spi_controller_is_slave(dspi->ctlr)) {
1037		chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1038				  SPI_CTAR_CSSCK(cssck) |
1039				  SPI_CTAR_PASC(pasc) |
1040				  SPI_CTAR_ASC(asc) |
1041				  SPI_CTAR_PBR(pbr) |
1042				  SPI_CTAR_BR(br);
1043
1044		if (spi->mode & SPI_LSB_FIRST)
1045			chip->ctar_val |= SPI_CTAR_LSBFE;
1046	}
1047
1048	spi_set_ctldata(spi, chip);
1049
1050	return 0;
1051}
1052
1053static void dspi_cleanup(struct spi_device *spi)
1054{
1055	struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1056
1057	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1058		spi->controller->bus_num, spi->chip_select);
1059
1060	kfree(chip);
1061}
1062
1063static const struct of_device_id fsl_dspi_dt_ids[] = {
1064	{
1065		.compatible = "fsl,vf610-dspi",
1066		.data = &devtype_data[VF610],
1067	}, {
1068		.compatible = "fsl,ls1021a-v1.0-dspi",
1069		.data = &devtype_data[LS1021A],
1070	}, {
1071		.compatible = "fsl,ls1012a-dspi",
1072		.data = &devtype_data[LS1012A],
1073	}, {
1074		.compatible = "fsl,ls1028a-dspi",
1075		.data = &devtype_data[LS1028A],
1076	}, {
1077		.compatible = "fsl,ls1043a-dspi",
1078		.data = &devtype_data[LS1043A],
1079	}, {
1080		.compatible = "fsl,ls1046a-dspi",
1081		.data = &devtype_data[LS1046A],
1082	}, {
1083		.compatible = "fsl,ls2080a-dspi",
1084		.data = &devtype_data[LS2080A],
1085	}, {
1086		.compatible = "fsl,ls2085a-dspi",
1087		.data = &devtype_data[LS2085A],
1088	}, {
1089		.compatible = "fsl,lx2160a-dspi",
1090		.data = &devtype_data[LX2160A],
1091	},
1092	{ /* sentinel */ }
1093};
1094MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1095
1096#ifdef CONFIG_PM_SLEEP
1097static int dspi_suspend(struct device *dev)
1098{
1099	struct fsl_dspi *dspi = dev_get_drvdata(dev);
1100
1101	if (dspi->irq)
1102		disable_irq(dspi->irq);
1103	spi_controller_suspend(dspi->ctlr);
1104	clk_disable_unprepare(dspi->clk);
1105
1106	pinctrl_pm_select_sleep_state(dev);
1107
1108	return 0;
1109}
1110
1111static int dspi_resume(struct device *dev)
1112{
1113	struct fsl_dspi *dspi = dev_get_drvdata(dev);
1114	int ret;
1115
1116	pinctrl_pm_select_default_state(dev);
1117
1118	ret = clk_prepare_enable(dspi->clk);
1119	if (ret)
1120		return ret;
1121	spi_controller_resume(dspi->ctlr);
1122	if (dspi->irq)
1123		enable_irq(dspi->irq);
1124
1125	return 0;
1126}
1127#endif /* CONFIG_PM_SLEEP */
1128
1129static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1130
1131static const struct regmap_range dspi_volatile_ranges[] = {
1132	regmap_reg_range(SPI_MCR, SPI_TCR),
1133	regmap_reg_range(SPI_SR, SPI_SR),
1134	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1135};
1136
1137static const struct regmap_access_table dspi_volatile_table = {
1138	.yes_ranges	= dspi_volatile_ranges,
1139	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),
1140};
1141
1142static const struct regmap_config dspi_regmap_config = {
1143	.reg_bits	= 32,
1144	.val_bits	= 32,
1145	.reg_stride	= 4,
1146	.max_register	= 0x88,
1147	.volatile_table	= &dspi_volatile_table,
1148};
1149
1150static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1151	regmap_reg_range(SPI_MCR, SPI_TCR),
1152	regmap_reg_range(SPI_SR, SPI_SR),
1153	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1154	regmap_reg_range(SPI_SREX, SPI_SREX),
1155};
1156
1157static const struct regmap_access_table dspi_xspi_volatile_table = {
1158	.yes_ranges	= dspi_xspi_volatile_ranges,
1159	.n_yes_ranges	= ARRAY_SIZE(dspi_xspi_volatile_ranges),
1160};
1161
1162static const struct regmap_config dspi_xspi_regmap_config[] = {
1163	{
1164		.reg_bits	= 32,
1165		.val_bits	= 32,
1166		.reg_stride	= 4,
1167		.max_register	= 0x13c,
1168		.volatile_table	= &dspi_xspi_volatile_table,
1169	},
1170	{
1171		.name		= "pushr",
1172		.reg_bits	= 16,
1173		.val_bits	= 16,
1174		.reg_stride	= 2,
1175		.max_register	= 0x2,
1176	},
1177};
1178
1179static int dspi_init(struct fsl_dspi *dspi)
1180{
1181	unsigned int mcr;
1182
1183	/* Set idle states for all chip select signals to high */
1184	mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1185
1186	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1187		mcr |= SPI_MCR_XSPI;
1188	if (!spi_controller_is_slave(dspi->ctlr))
1189		mcr |= SPI_MCR_MASTER;
1190
1191	regmap_write(dspi->regmap, SPI_MCR, mcr);
1192	regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1193
1194	switch (dspi->devtype_data->trans_mode) {
1195	case DSPI_XSPI_MODE:
1196		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1197		break;
1198	case DSPI_DMA_MODE:
1199		regmap_write(dspi->regmap, SPI_RSER,
1200			     SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1201			     SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1202		break;
1203	default:
1204		dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1205			dspi->devtype_data->trans_mode);
1206		return -EINVAL;
1207	}
1208
1209	return 0;
1210}
1211
1212static int dspi_slave_abort(struct spi_master *master)
1213{
1214	struct fsl_dspi *dspi = spi_master_get_devdata(master);
1215
1216	/*
1217	 * Terminate all pending DMA transactions for the SPI working
1218	 * in SLAVE mode.
1219	 */
1220	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1221		dmaengine_terminate_sync(dspi->dma->chan_rx);
1222		dmaengine_terminate_sync(dspi->dma->chan_tx);
1223	}
1224
1225	/* Clear the internal DSPI RX and TX FIFO buffers */
1226	regmap_update_bits(dspi->regmap, SPI_MCR,
1227			   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1228			   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1229
1230	return 0;
1231}
1232
1233static int dspi_probe(struct platform_device *pdev)
1234{
1235	struct device_node *np = pdev->dev.of_node;
1236	const struct regmap_config *regmap_config;
1237	struct fsl_dspi_platform_data *pdata;
1238	struct spi_controller *ctlr;
1239	int ret, cs_num, bus_num = -1;
1240	struct fsl_dspi *dspi;
1241	struct resource *res;
1242	void __iomem *base;
1243	bool big_endian;
1244
1245	dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1246	if (!dspi)
1247		return -ENOMEM;
1248
1249	ctlr = spi_alloc_master(&pdev->dev, 0);
1250	if (!ctlr)
1251		return -ENOMEM;
1252
1253	spi_controller_set_devdata(ctlr, dspi);
1254	platform_set_drvdata(pdev, dspi);
1255
1256	dspi->pdev = pdev;
1257	dspi->ctlr = ctlr;
1258
1259	ctlr->setup = dspi_setup;
1260	ctlr->transfer_one_message = dspi_transfer_one_message;
1261	ctlr->dev.of_node = pdev->dev.of_node;
1262
1263	ctlr->cleanup = dspi_cleanup;
1264	ctlr->slave_abort = dspi_slave_abort;
1265	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1266
1267	pdata = dev_get_platdata(&pdev->dev);
1268	if (pdata) {
1269		ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1270		ctlr->bus_num = pdata->bus_num;
1271
1272		/* Only Coldfire uses platform data */
1273		dspi->devtype_data = &devtype_data[MCF5441X];
1274		big_endian = true;
1275	} else {
1276
1277		ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1278		if (ret < 0) {
1279			dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1280			goto out_ctlr_put;
1281		}
1282		ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1283
1284		of_property_read_u32(np, "bus-num", &bus_num);
1285		ctlr->bus_num = bus_num;
1286
1287		if (of_property_read_bool(np, "spi-slave"))
1288			ctlr->slave = true;
1289
1290		dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1291		if (!dspi->devtype_data) {
1292			dev_err(&pdev->dev, "can't get devtype_data\n");
1293			ret = -EFAULT;
1294			goto out_ctlr_put;
1295		}
1296
1297		big_endian = of_device_is_big_endian(np);
1298	}
1299	if (big_endian) {
1300		dspi->pushr_cmd = 0;
1301		dspi->pushr_tx = 2;
1302	} else {
1303		dspi->pushr_cmd = 2;
1304		dspi->pushr_tx = 0;
1305	}
1306
1307	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1308		ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1309	else
1310		ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1311
1312	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1313	base = devm_ioremap_resource(&pdev->dev, res);
1314	if (IS_ERR(base)) {
1315		ret = PTR_ERR(base);
1316		goto out_ctlr_put;
1317	}
1318
1319	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1320		regmap_config = &dspi_xspi_regmap_config[0];
1321	else
1322		regmap_config = &dspi_regmap_config;
1323	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1324	if (IS_ERR(dspi->regmap)) {
1325		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1326				PTR_ERR(dspi->regmap));
1327		ret = PTR_ERR(dspi->regmap);
1328		goto out_ctlr_put;
1329	}
1330
1331	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1332		dspi->regmap_pushr = devm_regmap_init_mmio(
1333			&pdev->dev, base + SPI_PUSHR,
1334			&dspi_xspi_regmap_config[1]);
1335		if (IS_ERR(dspi->regmap_pushr)) {
1336			dev_err(&pdev->dev,
1337				"failed to init pushr regmap: %ld\n",
1338				PTR_ERR(dspi->regmap_pushr));
1339			ret = PTR_ERR(dspi->regmap_pushr);
1340			goto out_ctlr_put;
1341		}
1342	}
1343
1344	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1345	if (IS_ERR(dspi->clk)) {
1346		ret = PTR_ERR(dspi->clk);
1347		dev_err(&pdev->dev, "unable to get clock\n");
1348		goto out_ctlr_put;
1349	}
1350	ret = clk_prepare_enable(dspi->clk);
1351	if (ret)
1352		goto out_ctlr_put;
1353
1354	ret = dspi_init(dspi);
1355	if (ret)
1356		goto out_clk_put;
1357
1358	dspi->irq = platform_get_irq(pdev, 0);
1359	if (dspi->irq <= 0) {
1360		dev_info(&pdev->dev,
1361			 "can't get platform irq, using poll mode\n");
1362		dspi->irq = 0;
1363		goto poll_mode;
1364	}
1365
1366	init_completion(&dspi->xfer_done);
1367
1368	ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1369				   IRQF_SHARED, pdev->name, dspi);
1370	if (ret < 0) {
1371		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1372		goto out_clk_put;
1373	}
1374
1375poll_mode:
1376
1377	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1378		ret = dspi_request_dma(dspi, res->start);
1379		if (ret < 0) {
1380			dev_err(&pdev->dev, "can't get dma channels\n");
1381			goto out_free_irq;
1382		}
1383	}
1384
1385	ctlr->max_speed_hz =
1386		clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1387
1388	if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1389		ctlr->ptp_sts_supported = true;
1390
1391	ret = spi_register_controller(ctlr);
1392	if (ret != 0) {
1393		dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1394		goto out_release_dma;
1395	}
1396
1397	return ret;
1398
1399out_release_dma:
1400	dspi_release_dma(dspi);
1401out_free_irq:
1402	if (dspi->irq)
1403		free_irq(dspi->irq, dspi);
1404out_clk_put:
1405	clk_disable_unprepare(dspi->clk);
1406out_ctlr_put:
1407	spi_controller_put(ctlr);
1408
1409	return ret;
1410}
1411
1412static int dspi_remove(struct platform_device *pdev)
1413{
1414	struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1415
1416	/* Disconnect from the SPI framework */
1417	spi_unregister_controller(dspi->ctlr);
1418
1419	/* Disable RX and TX */
1420	regmap_update_bits(dspi->regmap, SPI_MCR,
1421			   SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1422			   SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1423
1424	/* Stop Running */
1425	regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1426
1427	dspi_release_dma(dspi);
1428	if (dspi->irq)
1429		free_irq(dspi->irq, dspi);
1430	clk_disable_unprepare(dspi->clk);
1431
1432	return 0;
1433}
1434
1435static void dspi_shutdown(struct platform_device *pdev)
1436{
1437	dspi_remove(pdev);
1438}
1439
1440static struct platform_driver fsl_dspi_driver = {
1441	.driver.name		= DRIVER_NAME,
1442	.driver.of_match_table	= fsl_dspi_dt_ids,
1443	.driver.owner		= THIS_MODULE,
1444	.driver.pm		= &dspi_pm,
1445	.probe			= dspi_probe,
1446	.remove			= dspi_remove,
1447	.shutdown		= dspi_shutdown,
1448};
1449module_platform_driver(fsl_dspi_driver);
1450
1451MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1452MODULE_LICENSE("GPL");
1453MODULE_ALIAS("platform:" DRIVER_NAME);
1454