1/* 2 * Broadcom BCM63XX High Speed SPI Controller driver 3 * 4 * Copyright 2000-2010 Broadcom Corporation 5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Licensed under the GNU/GPL. See COPYING for details. 8 */ 9 10#include <linux/kernel.h> 11#include <linux/init.h> 12#include <linux/io.h> 13#include <linux/clk.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/delay.h> 17#include <linux/dma-mapping.h> 18#include <linux/err.h> 19#include <linux/interrupt.h> 20#include <linux/spi/spi.h> 21#include <linux/mutex.h> 22#include <linux/of.h> 23#include <linux/reset.h> 24#include <linux/pm_runtime.h> 25 26#define HSSPI_GLOBAL_CTRL_REG 0x0 27#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 28#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff 29#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8 30#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00 31#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16) 32#define GLOBAL_CTRL_CLK_POLARITY BIT(17) 33#define GLOBAL_CTRL_MOSI_IDLE BIT(18) 34 35#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4 36 37#define HSSPI_INT_STATUS_REG 0x8 38#define HSSPI_INT_STATUS_MASKED_REG 0xc 39#define HSSPI_INT_MASK_REG 0x10 40 41#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0) 42#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1) 43#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2) 44#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3) 45#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4) 46 47#define HSSPI_INT_CLEAR_ALL 0xff001f1f 48 49#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40) 50#define PINGPONG_CMD_COMMAND_MASK 0xf 51#define PINGPONG_COMMAND_NOOP 0 52#define PINGPONG_COMMAND_START_NOW 1 53#define PINGPONG_COMMAND_START_TRIGGER 2 54#define PINGPONG_COMMAND_HALT 3 55#define PINGPONG_COMMAND_FLUSH 4 56#define PINGPONG_CMD_PROFILE_SHIFT 8 57#define PINGPONG_CMD_SS_SHIFT 12 58 59#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) 60 61#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) 62#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff 63#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) 64#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) 65 66#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20) 67#define SIGNAL_CTRL_LATCH_RISING BIT(12) 68#define SIGNAL_CTRL_LAUNCH_RISING BIT(13) 69#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16) 70 71#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20) 72#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8 73#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12 74#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16 75#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18 76#define MODE_CTRL_MODE_3WIRE BIT(20) 77#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24 78 79#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) 80 81 82#define HSSPI_OP_MULTIBIT BIT(11) 83#define HSSPI_OP_CODE_SHIFT 13 84#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) 85#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) 86#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT) 87#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT) 88#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT) 89 90#define HSSPI_BUFFER_LEN 512 91#define HSSPI_OPCODE_LEN 2 92 93#define HSSPI_MAX_PREPEND_LEN 15 94 95#define HSSPI_MAX_SYNC_CLOCK 30000000 96 97#define HSSPI_SPI_MAX_CS 8 98#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */ 99 100struct bcm63xx_hsspi { 101 struct completion done; 102 struct mutex bus_mutex; 103 104 struct platform_device *pdev; 105 struct clk *clk; 106 struct clk *pll_clk; 107 void __iomem *regs; 108 u8 __iomem *fifo; 109 110 u32 speed_hz; 111 u8 cs_polarity; 112}; 113 114static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, 115 bool active) 116{ 117 u32 reg; 118 119 mutex_lock(&bs->bus_mutex); 120 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 121 122 reg &= ~BIT(cs); 123 if (active == !(bs->cs_polarity & BIT(cs))) 124 reg |= BIT(cs); 125 126 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 127 mutex_unlock(&bs->bus_mutex); 128} 129 130static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, 131 struct spi_device *spi, int hz) 132{ 133 unsigned int profile = spi->chip_select; 134 u32 reg; 135 136 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); 137 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, 138 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); 139 140 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); 141 if (hz > HSSPI_MAX_SYNC_CLOCK) 142 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; 143 else 144 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; 145 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); 146 147 mutex_lock(&bs->bus_mutex); 148 /* setup clock polarity */ 149 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 150 reg &= ~GLOBAL_CTRL_CLK_POLARITY; 151 if (spi->mode & SPI_CPOL) 152 reg |= GLOBAL_CTRL_CLK_POLARITY; 153 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 154 mutex_unlock(&bs->bus_mutex); 155} 156 157static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) 158{ 159 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); 160 unsigned int chip_select = spi->chip_select; 161 u16 opcode = 0; 162 int pending = t->len; 163 int step_size = HSSPI_BUFFER_LEN; 164 const u8 *tx = t->tx_buf; 165 u8 *rx = t->rx_buf; 166 u32 val = 0; 167 168 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); 169 bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); 170 171 if (tx && rx) 172 opcode = HSSPI_OP_READ_WRITE; 173 else if (tx) 174 opcode = HSSPI_OP_WRITE; 175 else if (rx) 176 opcode = HSSPI_OP_READ; 177 178 if (opcode != HSSPI_OP_READ) 179 step_size -= HSSPI_OPCODE_LEN; 180 181 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || 182 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { 183 opcode |= HSSPI_OP_MULTIBIT; 184 185 if (t->rx_nbits == SPI_NBITS_DUAL) 186 val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; 187 if (t->tx_nbits == SPI_NBITS_DUAL) 188 val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; 189 } 190 191 __raw_writel(val | 0xff, 192 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); 193 194 while (pending > 0) { 195 int curr_step = min_t(int, step_size, pending); 196 197 reinit_completion(&bs->done); 198 if (tx) { 199 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step); 200 tx += curr_step; 201 } 202 203 __raw_writew(opcode | curr_step, bs->fifo); 204 205 /* enable interrupt */ 206 __raw_writel(HSSPI_PINGx_CMD_DONE(0), 207 bs->regs + HSSPI_INT_MASK_REG); 208 209 /* start the transfer */ 210 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | 211 chip_select << PINGPONG_CMD_PROFILE_SHIFT | 212 PINGPONG_COMMAND_START_NOW, 213 bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); 214 215 if (wait_for_completion_timeout(&bs->done, HZ) == 0) { 216 dev_err(&bs->pdev->dev, "transfer timed out!\n"); 217 return -ETIMEDOUT; 218 } 219 220 if (rx) { 221 memcpy_fromio(rx, bs->fifo, curr_step); 222 rx += curr_step; 223 } 224 225 pending -= curr_step; 226 } 227 228 return 0; 229} 230 231static int bcm63xx_hsspi_setup(struct spi_device *spi) 232{ 233 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); 234 u32 reg; 235 236 reg = __raw_readl(bs->regs + 237 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); 238 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); 239 if (spi->mode & SPI_CPHA) 240 reg |= SIGNAL_CTRL_LAUNCH_RISING; 241 else 242 reg |= SIGNAL_CTRL_LATCH_RISING; 243 __raw_writel(reg, bs->regs + 244 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select)); 245 246 mutex_lock(&bs->bus_mutex); 247 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 248 249 /* only change actual polarities if there is no transfer */ 250 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { 251 if (spi->mode & SPI_CS_HIGH) 252 reg |= BIT(spi->chip_select); 253 else 254 reg &= ~BIT(spi->chip_select); 255 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 256 } 257 258 if (spi->mode & SPI_CS_HIGH) 259 bs->cs_polarity |= BIT(spi->chip_select); 260 else 261 bs->cs_polarity &= ~BIT(spi->chip_select); 262 263 mutex_unlock(&bs->bus_mutex); 264 265 return 0; 266} 267 268static int bcm63xx_hsspi_transfer_one(struct spi_master *master, 269 struct spi_message *msg) 270{ 271 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 272 struct spi_transfer *t; 273 struct spi_device *spi = msg->spi; 274 int status = -EINVAL; 275 int dummy_cs; 276 u32 reg; 277 278 /* This controller does not support keeping CS active during idle. 279 * To work around this, we use the following ugly hack: 280 * 281 * a. Invert the target chip select's polarity so it will be active. 282 * b. Select a "dummy" chip select to use as the hardware target. 283 * c. Invert the dummy chip select's polarity so it will be inactive 284 * during the actual transfers. 285 * d. Tell the hardware to send to the dummy chip select. Thanks to 286 * the multiplexed nature of SPI the actual target will receive 287 * the transfer and we see its response. 288 * 289 * e. At the end restore the polarities again to their default values. 290 */ 291 292 dummy_cs = !spi->chip_select; 293 bcm63xx_hsspi_set_cs(bs, dummy_cs, true); 294 295 list_for_each_entry(t, &msg->transfers, transfer_list) { 296 status = bcm63xx_hsspi_do_txrx(spi, t); 297 if (status) 298 break; 299 300 msg->actual_length += t->len; 301 302 spi_transfer_delay_exec(t); 303 304 if (t->cs_change) 305 bcm63xx_hsspi_set_cs(bs, spi->chip_select, false); 306 } 307 308 mutex_lock(&bs->bus_mutex); 309 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 310 reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; 311 reg |= bs->cs_polarity; 312 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); 313 mutex_unlock(&bs->bus_mutex); 314 315 msg->status = status; 316 spi_finalize_current_message(master); 317 318 return 0; 319} 320 321static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id) 322{ 323 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id; 324 325 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) 326 return IRQ_NONE; 327 328 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); 329 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 330 331 complete(&bs->done); 332 333 return IRQ_HANDLED; 334} 335 336static int bcm63xx_hsspi_probe(struct platform_device *pdev) 337{ 338 struct spi_master *master; 339 struct bcm63xx_hsspi *bs; 340 void __iomem *regs; 341 struct device *dev = &pdev->dev; 342 struct clk *clk, *pll_clk = NULL; 343 int irq, ret; 344 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; 345 struct reset_control *reset; 346 347 irq = platform_get_irq(pdev, 0); 348 if (irq < 0) 349 return irq; 350 351 regs = devm_platform_ioremap_resource(pdev, 0); 352 if (IS_ERR(regs)) 353 return PTR_ERR(regs); 354 355 clk = devm_clk_get(dev, "hsspi"); 356 357 if (IS_ERR(clk)) 358 return PTR_ERR(clk); 359 360 reset = devm_reset_control_get_optional_exclusive(dev, NULL); 361 if (IS_ERR(reset)) 362 return PTR_ERR(reset); 363 364 ret = clk_prepare_enable(clk); 365 if (ret) 366 return ret; 367 368 ret = reset_control_reset(reset); 369 if (ret) { 370 dev_err(dev, "unable to reset device: %d\n", ret); 371 goto out_disable_clk; 372 } 373 374 rate = clk_get_rate(clk); 375 if (!rate) { 376 pll_clk = devm_clk_get(dev, "pll"); 377 378 if (IS_ERR(pll_clk)) { 379 ret = PTR_ERR(pll_clk); 380 goto out_disable_clk; 381 } 382 383 ret = clk_prepare_enable(pll_clk); 384 if (ret) 385 goto out_disable_clk; 386 387 rate = clk_get_rate(pll_clk); 388 if (!rate) { 389 ret = -EINVAL; 390 goto out_disable_pll_clk; 391 } 392 } 393 394 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 395 if (!master) { 396 ret = -ENOMEM; 397 goto out_disable_pll_clk; 398 } 399 400 bs = spi_master_get_devdata(master); 401 bs->pdev = pdev; 402 bs->clk = clk; 403 bs->pll_clk = pll_clk; 404 bs->regs = regs; 405 bs->speed_hz = rate; 406 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); 407 408 mutex_init(&bs->bus_mutex); 409 init_completion(&bs->done); 410 411 master->dev.of_node = dev->of_node; 412 if (!dev->of_node) 413 master->bus_num = HSSPI_BUS_NUM; 414 415 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 416 if (num_cs > 8) { 417 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", 418 num_cs); 419 num_cs = HSSPI_SPI_MAX_CS; 420 } 421 master->num_chipselect = num_cs; 422 master->setup = bcm63xx_hsspi_setup; 423 master->transfer_one_message = bcm63xx_hsspi_transfer_one; 424 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | 425 SPI_RX_DUAL | SPI_TX_DUAL; 426 master->bits_per_word_mask = SPI_BPW_MASK(8); 427 master->auto_runtime_pm = true; 428 429 platform_set_drvdata(pdev, master); 430 431 /* Initialize the hardware */ 432 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 433 434 /* clean up any pending interrupts */ 435 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG); 436 437 /* read out default CS polarities */ 438 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); 439 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; 440 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, 441 bs->regs + HSSPI_GLOBAL_CTRL_REG); 442 443 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED, 444 pdev->name, bs); 445 446 if (ret) 447 goto out_put_master; 448 449 pm_runtime_enable(&pdev->dev); 450 451 /* register and we are done */ 452 ret = devm_spi_register_master(dev, master); 453 if (ret) 454 goto out_pm_disable; 455 456 return 0; 457 458out_pm_disable: 459 pm_runtime_disable(&pdev->dev); 460out_put_master: 461 spi_master_put(master); 462out_disable_pll_clk: 463 clk_disable_unprepare(pll_clk); 464out_disable_clk: 465 clk_disable_unprepare(clk); 466 return ret; 467} 468 469 470static int bcm63xx_hsspi_remove(struct platform_device *pdev) 471{ 472 struct spi_master *master = platform_get_drvdata(pdev); 473 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 474 475 /* reset the hardware and block queue progress */ 476 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG); 477 clk_disable_unprepare(bs->pll_clk); 478 clk_disable_unprepare(bs->clk); 479 480 return 0; 481} 482 483#ifdef CONFIG_PM_SLEEP 484static int bcm63xx_hsspi_suspend(struct device *dev) 485{ 486 struct spi_master *master = dev_get_drvdata(dev); 487 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 488 489 spi_master_suspend(master); 490 clk_disable_unprepare(bs->pll_clk); 491 clk_disable_unprepare(bs->clk); 492 493 return 0; 494} 495 496static int bcm63xx_hsspi_resume(struct device *dev) 497{ 498 struct spi_master *master = dev_get_drvdata(dev); 499 struct bcm63xx_hsspi *bs = spi_master_get_devdata(master); 500 int ret; 501 502 ret = clk_prepare_enable(bs->clk); 503 if (ret) 504 return ret; 505 506 if (bs->pll_clk) { 507 ret = clk_prepare_enable(bs->pll_clk); 508 if (ret) { 509 clk_disable_unprepare(bs->clk); 510 return ret; 511 } 512 } 513 514 spi_master_resume(master); 515 516 return 0; 517} 518#endif 519 520static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend, 521 bcm63xx_hsspi_resume); 522 523static const struct of_device_id bcm63xx_hsspi_of_match[] = { 524 { .compatible = "brcm,bcm6328-hsspi", }, 525 { }, 526}; 527MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match); 528 529static struct platform_driver bcm63xx_hsspi_driver = { 530 .driver = { 531 .name = "bcm63xx-hsspi", 532 .pm = &bcm63xx_hsspi_pm_ops, 533 .of_match_table = bcm63xx_hsspi_of_match, 534 }, 535 .probe = bcm63xx_hsspi_probe, 536 .remove = bcm63xx_hsspi_remove, 537}; 538 539module_platform_driver(bcm63xx_hsspi_driver); 540 541MODULE_ALIAS("platform:bcm63xx_hsspi"); 542MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver"); 543MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 544MODULE_LICENSE("GPL"); 545