1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Driver for Atmel AT32 and AT91 SPI Controllers 4 * 5 * Copyright (C) 2006 Atmel Corporation 6 */ 7 8#include <linux/kernel.h> 9#include <linux/clk.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <linux/delay.h> 13#include <linux/dma-mapping.h> 14#include <linux/dmaengine.h> 15#include <linux/err.h> 16#include <linux/interrupt.h> 17#include <linux/spi/spi.h> 18#include <linux/slab.h> 19#include <linux/of.h> 20 21#include <linux/io.h> 22#include <linux/gpio/consumer.h> 23#include <linux/pinctrl/consumer.h> 24#include <linux/pm_runtime.h> 25#include <trace/events/spi.h> 26 27/* SPI register offsets */ 28#define SPI_CR 0x0000 29#define SPI_MR 0x0004 30#define SPI_RDR 0x0008 31#define SPI_TDR 0x000c 32#define SPI_SR 0x0010 33#define SPI_IER 0x0014 34#define SPI_IDR 0x0018 35#define SPI_IMR 0x001c 36#define SPI_CSR0 0x0030 37#define SPI_CSR1 0x0034 38#define SPI_CSR2 0x0038 39#define SPI_CSR3 0x003c 40#define SPI_FMR 0x0040 41#define SPI_FLR 0x0044 42#define SPI_VERSION 0x00fc 43#define SPI_RPR 0x0100 44#define SPI_RCR 0x0104 45#define SPI_TPR 0x0108 46#define SPI_TCR 0x010c 47#define SPI_RNPR 0x0110 48#define SPI_RNCR 0x0114 49#define SPI_TNPR 0x0118 50#define SPI_TNCR 0x011c 51#define SPI_PTCR 0x0120 52#define SPI_PTSR 0x0124 53 54/* Bitfields in CR */ 55#define SPI_SPIEN_OFFSET 0 56#define SPI_SPIEN_SIZE 1 57#define SPI_SPIDIS_OFFSET 1 58#define SPI_SPIDIS_SIZE 1 59#define SPI_SWRST_OFFSET 7 60#define SPI_SWRST_SIZE 1 61#define SPI_LASTXFER_OFFSET 24 62#define SPI_LASTXFER_SIZE 1 63#define SPI_TXFCLR_OFFSET 16 64#define SPI_TXFCLR_SIZE 1 65#define SPI_RXFCLR_OFFSET 17 66#define SPI_RXFCLR_SIZE 1 67#define SPI_FIFOEN_OFFSET 30 68#define SPI_FIFOEN_SIZE 1 69#define SPI_FIFODIS_OFFSET 31 70#define SPI_FIFODIS_SIZE 1 71 72/* Bitfields in MR */ 73#define SPI_MSTR_OFFSET 0 74#define SPI_MSTR_SIZE 1 75#define SPI_PS_OFFSET 1 76#define SPI_PS_SIZE 1 77#define SPI_PCSDEC_OFFSET 2 78#define SPI_PCSDEC_SIZE 1 79#define SPI_FDIV_OFFSET 3 80#define SPI_FDIV_SIZE 1 81#define SPI_MODFDIS_OFFSET 4 82#define SPI_MODFDIS_SIZE 1 83#define SPI_WDRBT_OFFSET 5 84#define SPI_WDRBT_SIZE 1 85#define SPI_LLB_OFFSET 7 86#define SPI_LLB_SIZE 1 87#define SPI_PCS_OFFSET 16 88#define SPI_PCS_SIZE 4 89#define SPI_DLYBCS_OFFSET 24 90#define SPI_DLYBCS_SIZE 8 91 92/* Bitfields in RDR */ 93#define SPI_RD_OFFSET 0 94#define SPI_RD_SIZE 16 95 96/* Bitfields in TDR */ 97#define SPI_TD_OFFSET 0 98#define SPI_TD_SIZE 16 99 100/* Bitfields in SR */ 101#define SPI_RDRF_OFFSET 0 102#define SPI_RDRF_SIZE 1 103#define SPI_TDRE_OFFSET 1 104#define SPI_TDRE_SIZE 1 105#define SPI_MODF_OFFSET 2 106#define SPI_MODF_SIZE 1 107#define SPI_OVRES_OFFSET 3 108#define SPI_OVRES_SIZE 1 109#define SPI_ENDRX_OFFSET 4 110#define SPI_ENDRX_SIZE 1 111#define SPI_ENDTX_OFFSET 5 112#define SPI_ENDTX_SIZE 1 113#define SPI_RXBUFF_OFFSET 6 114#define SPI_RXBUFF_SIZE 1 115#define SPI_TXBUFE_OFFSET 7 116#define SPI_TXBUFE_SIZE 1 117#define SPI_NSSR_OFFSET 8 118#define SPI_NSSR_SIZE 1 119#define SPI_TXEMPTY_OFFSET 9 120#define SPI_TXEMPTY_SIZE 1 121#define SPI_SPIENS_OFFSET 16 122#define SPI_SPIENS_SIZE 1 123#define SPI_TXFEF_OFFSET 24 124#define SPI_TXFEF_SIZE 1 125#define SPI_TXFFF_OFFSET 25 126#define SPI_TXFFF_SIZE 1 127#define SPI_TXFTHF_OFFSET 26 128#define SPI_TXFTHF_SIZE 1 129#define SPI_RXFEF_OFFSET 27 130#define SPI_RXFEF_SIZE 1 131#define SPI_RXFFF_OFFSET 28 132#define SPI_RXFFF_SIZE 1 133#define SPI_RXFTHF_OFFSET 29 134#define SPI_RXFTHF_SIZE 1 135#define SPI_TXFPTEF_OFFSET 30 136#define SPI_TXFPTEF_SIZE 1 137#define SPI_RXFPTEF_OFFSET 31 138#define SPI_RXFPTEF_SIZE 1 139 140/* Bitfields in CSR0 */ 141#define SPI_CPOL_OFFSET 0 142#define SPI_CPOL_SIZE 1 143#define SPI_NCPHA_OFFSET 1 144#define SPI_NCPHA_SIZE 1 145#define SPI_CSAAT_OFFSET 3 146#define SPI_CSAAT_SIZE 1 147#define SPI_BITS_OFFSET 4 148#define SPI_BITS_SIZE 4 149#define SPI_SCBR_OFFSET 8 150#define SPI_SCBR_SIZE 8 151#define SPI_DLYBS_OFFSET 16 152#define SPI_DLYBS_SIZE 8 153#define SPI_DLYBCT_OFFSET 24 154#define SPI_DLYBCT_SIZE 8 155 156/* Bitfields in RCR */ 157#define SPI_RXCTR_OFFSET 0 158#define SPI_RXCTR_SIZE 16 159 160/* Bitfields in TCR */ 161#define SPI_TXCTR_OFFSET 0 162#define SPI_TXCTR_SIZE 16 163 164/* Bitfields in RNCR */ 165#define SPI_RXNCR_OFFSET 0 166#define SPI_RXNCR_SIZE 16 167 168/* Bitfields in TNCR */ 169#define SPI_TXNCR_OFFSET 0 170#define SPI_TXNCR_SIZE 16 171 172/* Bitfields in PTCR */ 173#define SPI_RXTEN_OFFSET 0 174#define SPI_RXTEN_SIZE 1 175#define SPI_RXTDIS_OFFSET 1 176#define SPI_RXTDIS_SIZE 1 177#define SPI_TXTEN_OFFSET 8 178#define SPI_TXTEN_SIZE 1 179#define SPI_TXTDIS_OFFSET 9 180#define SPI_TXTDIS_SIZE 1 181 182/* Bitfields in FMR */ 183#define SPI_TXRDYM_OFFSET 0 184#define SPI_TXRDYM_SIZE 2 185#define SPI_RXRDYM_OFFSET 4 186#define SPI_RXRDYM_SIZE 2 187#define SPI_TXFTHRES_OFFSET 16 188#define SPI_TXFTHRES_SIZE 6 189#define SPI_RXFTHRES_OFFSET 24 190#define SPI_RXFTHRES_SIZE 6 191 192/* Bitfields in FLR */ 193#define SPI_TXFL_OFFSET 0 194#define SPI_TXFL_SIZE 6 195#define SPI_RXFL_OFFSET 16 196#define SPI_RXFL_SIZE 6 197 198/* Constants for BITS */ 199#define SPI_BITS_8_BPT 0 200#define SPI_BITS_9_BPT 1 201#define SPI_BITS_10_BPT 2 202#define SPI_BITS_11_BPT 3 203#define SPI_BITS_12_BPT 4 204#define SPI_BITS_13_BPT 5 205#define SPI_BITS_14_BPT 6 206#define SPI_BITS_15_BPT 7 207#define SPI_BITS_16_BPT 8 208#define SPI_ONE_DATA 0 209#define SPI_TWO_DATA 1 210#define SPI_FOUR_DATA 2 211 212/* Bit manipulation macros */ 213#define SPI_BIT(name) \ 214 (1 << SPI_##name##_OFFSET) 215#define SPI_BF(name, value) \ 216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 217#define SPI_BFEXT(name, value) \ 218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 219#define SPI_BFINS(name, value, old) \ 220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 221 | SPI_BF(name, value)) 222 223/* Register access macros */ 224#define spi_readl(port, reg) \ 225 readl_relaxed((port)->regs + SPI_##reg) 226#define spi_writel(port, reg, value) \ 227 writel_relaxed((value), (port)->regs + SPI_##reg) 228#define spi_writew(port, reg, value) \ 229 writew_relaxed((value), (port)->regs + SPI_##reg) 230 231/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 232 * cache operations; better heuristics consider wordsize and bitrate. 233 */ 234#define DMA_MIN_BYTES 16 235 236#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 237 238#define AUTOSUSPEND_TIMEOUT 2000 239 240struct atmel_spi_caps { 241 bool is_spi2; 242 bool has_wdrbt; 243 bool has_dma_support; 244 bool has_pdc_support; 245}; 246 247/* 248 * The core SPI transfer engine just talks to a register bank to set up 249 * DMA transfers; transfer queue progress is driven by IRQs. The clock 250 * framework provides the base clock, subdivided for each spi_device. 251 */ 252struct atmel_spi { 253 spinlock_t lock; 254 unsigned long flags; 255 256 phys_addr_t phybase; 257 void __iomem *regs; 258 int irq; 259 struct clk *clk; 260 struct platform_device *pdev; 261 unsigned long spi_clk; 262 263 struct spi_transfer *current_transfer; 264 int current_remaining_bytes; 265 int done_status; 266 dma_addr_t dma_addr_rx_bbuf; 267 dma_addr_t dma_addr_tx_bbuf; 268 void *addr_rx_bbuf; 269 void *addr_tx_bbuf; 270 271 struct completion xfer_completion; 272 273 struct atmel_spi_caps caps; 274 275 bool use_dma; 276 bool use_pdc; 277 278 bool keep_cs; 279 280 u32 fifo_size; 281 u8 native_cs_free; 282 u8 native_cs_for_gpio; 283}; 284 285/* Controller-specific per-slave state */ 286struct atmel_spi_device { 287 u32 csr; 288}; 289 290#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */ 291#define INVALID_DMA_ADDRESS 0xffffffff 292 293/* 294 * Version 2 of the SPI controller has 295 * - CR.LASTXFER 296 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) 297 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) 298 * - SPI_CSRx.CSAAT 299 * - SPI_CSRx.SBCR allows faster clocking 300 */ 301static bool atmel_spi_is_v2(struct atmel_spi *as) 302{ 303 return as->caps.is_spi2; 304} 305 306/* 307 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby 308 * they assume that spi slave device state will not change on deselect, so 309 * that automagic deselection is OK. ("NPCSx rises if no data is to be 310 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer 311 * controllers have CSAAT and friends. 312 * 313 * Even controller newer than ar91rm9200, using GPIOs can make sens as 314 * it lets us support active-high chipselects despite the controller's 315 * belief that only active-low devices/systems exists. 316 * 317 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work 318 * right when driven with GPIO. ("Mode Fault does not allow more than one 319 * Master on Chip Select 0.") No workaround exists for that ... so for 320 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, 321 * and (c) will trigger that first erratum in some cases. 322 */ 323 324static void cs_activate(struct atmel_spi *as, struct spi_device *spi) 325{ 326 struct atmel_spi_device *asd = spi->controller_state; 327 int chip_select; 328 u32 mr; 329 330 if (spi->cs_gpiod) 331 chip_select = as->native_cs_for_gpio; 332 else 333 chip_select = spi->chip_select; 334 335 if (atmel_spi_is_v2(as)) { 336 spi_writel(as, CSR0 + 4 * chip_select, asd->csr); 337 /* For the low SPI version, there is a issue that PDC transfer 338 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 339 */ 340 spi_writel(as, CSR0, asd->csr); 341 if (as->caps.has_wdrbt) { 342 spi_writel(as, MR, 343 SPI_BF(PCS, ~(0x01 << chip_select)) 344 | SPI_BIT(WDRBT) 345 | SPI_BIT(MODFDIS) 346 | SPI_BIT(MSTR)); 347 } else { 348 spi_writel(as, MR, 349 SPI_BF(PCS, ~(0x01 << chip_select)) 350 | SPI_BIT(MODFDIS) 351 | SPI_BIT(MSTR)); 352 } 353 354 mr = spi_readl(as, MR); 355 } else { 356 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; 357 int i; 358 u32 csr; 359 360 /* Make sure clock polarity is correct */ 361 for (i = 0; i < spi->master->num_chipselect; i++) { 362 csr = spi_readl(as, CSR0 + 4 * i); 363 if ((csr ^ cpol) & SPI_BIT(CPOL)) 364 spi_writel(as, CSR0 + 4 * i, 365 csr ^ SPI_BIT(CPOL)); 366 } 367 368 mr = spi_readl(as, MR); 369 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); 370 spi_writel(as, MR, mr); 371 } 372 373 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr); 374} 375 376static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) 377{ 378 int chip_select; 379 u32 mr; 380 381 if (spi->cs_gpiod) 382 chip_select = as->native_cs_for_gpio; 383 else 384 chip_select = spi->chip_select; 385 386 /* only deactivate *this* device; sometimes transfers to 387 * another device may be active when this routine is called. 388 */ 389 mr = spi_readl(as, MR); 390 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { 391 mr = SPI_BFINS(PCS, 0xf, mr); 392 spi_writel(as, MR, mr); 393 } 394 395 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr); 396 397 if (!spi->cs_gpiod) 398 spi_writel(as, CR, SPI_BIT(LASTXFER)); 399} 400 401static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) 402{ 403 spin_lock_irqsave(&as->lock, as->flags); 404} 405 406static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) 407{ 408 spin_unlock_irqrestore(&as->lock, as->flags); 409} 410 411static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer) 412{ 413 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf); 414} 415 416static inline bool atmel_spi_use_dma(struct atmel_spi *as, 417 struct spi_transfer *xfer) 418{ 419 return as->use_dma && xfer->len >= DMA_MIN_BYTES; 420} 421 422static bool atmel_spi_can_dma(struct spi_master *master, 423 struct spi_device *spi, 424 struct spi_transfer *xfer) 425{ 426 struct atmel_spi *as = spi_master_get_devdata(master); 427 428 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) 429 return atmel_spi_use_dma(as, xfer) && 430 !atmel_spi_is_vmalloc_xfer(xfer); 431 else 432 return atmel_spi_use_dma(as, xfer); 433 434} 435 436static int atmel_spi_dma_slave_config(struct atmel_spi *as, 437 struct dma_slave_config *slave_config, 438 u8 bits_per_word) 439{ 440 struct spi_master *master = platform_get_drvdata(as->pdev); 441 int err = 0; 442 443 if (bits_per_word > 8) { 444 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 445 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 446 } else { 447 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 448 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 449 } 450 451 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; 452 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; 453 slave_config->src_maxburst = 1; 454 slave_config->dst_maxburst = 1; 455 slave_config->device_fc = false; 456 457 /* 458 * This driver uses fixed peripheral select mode (PS bit set to '0' in 459 * the Mode Register). 460 * So according to the datasheet, when FIFOs are available (and 461 * enabled), the Transmit FIFO operates in Multiple Data Mode. 462 * In this mode, up to 2 data, not 4, can be written into the Transmit 463 * Data Register in a single access. 464 * However, the first data has to be written into the lowest 16 bits and 465 * the second data into the highest 16 bits of the Transmit 466 * Data Register. For 8bit data (the most frequent case), it would 467 * require to rework tx_buf so each data would actualy fit 16 bits. 468 * So we'd rather write only one data at the time. Hence the transmit 469 * path works the same whether FIFOs are available (and enabled) or not. 470 */ 471 slave_config->direction = DMA_MEM_TO_DEV; 472 if (dmaengine_slave_config(master->dma_tx, slave_config)) { 473 dev_err(&as->pdev->dev, 474 "failed to configure tx dma channel\n"); 475 err = -EINVAL; 476 } 477 478 /* 479 * This driver configures the spi controller for master mode (MSTR bit 480 * set to '1' in the Mode Register). 481 * So according to the datasheet, when FIFOs are available (and 482 * enabled), the Receive FIFO operates in Single Data Mode. 483 * So the receive path works the same whether FIFOs are available (and 484 * enabled) or not. 485 */ 486 slave_config->direction = DMA_DEV_TO_MEM; 487 if (dmaengine_slave_config(master->dma_rx, slave_config)) { 488 dev_err(&as->pdev->dev, 489 "failed to configure rx dma channel\n"); 490 err = -EINVAL; 491 } 492 493 return err; 494} 495 496static int atmel_spi_configure_dma(struct spi_master *master, 497 struct atmel_spi *as) 498{ 499 struct dma_slave_config slave_config; 500 struct device *dev = &as->pdev->dev; 501 int err; 502 503 dma_cap_mask_t mask; 504 dma_cap_zero(mask); 505 dma_cap_set(DMA_SLAVE, mask); 506 507 master->dma_tx = dma_request_chan(dev, "tx"); 508 if (IS_ERR(master->dma_tx)) { 509 err = dev_err_probe(dev, PTR_ERR(master->dma_tx), 510 "No TX DMA channel, DMA is disabled\n"); 511 goto error_clear; 512 } 513 514 master->dma_rx = dma_request_chan(dev, "rx"); 515 if (IS_ERR(master->dma_rx)) { 516 err = PTR_ERR(master->dma_rx); 517 /* 518 * No reason to check EPROBE_DEFER here since we have already 519 * requested tx channel. 520 */ 521 dev_err(dev, "No RX DMA channel, DMA is disabled\n"); 522 goto error; 523 } 524 525 err = atmel_spi_dma_slave_config(as, &slave_config, 8); 526 if (err) 527 goto error; 528 529 dev_info(&as->pdev->dev, 530 "Using %s (tx) and %s (rx) for DMA transfers\n", 531 dma_chan_name(master->dma_tx), 532 dma_chan_name(master->dma_rx)); 533 534 return 0; 535error: 536 if (!IS_ERR(master->dma_rx)) 537 dma_release_channel(master->dma_rx); 538 if (!IS_ERR(master->dma_tx)) 539 dma_release_channel(master->dma_tx); 540error_clear: 541 master->dma_tx = master->dma_rx = NULL; 542 return err; 543} 544 545static void atmel_spi_stop_dma(struct spi_master *master) 546{ 547 if (master->dma_rx) 548 dmaengine_terminate_all(master->dma_rx); 549 if (master->dma_tx) 550 dmaengine_terminate_all(master->dma_tx); 551} 552 553static void atmel_spi_release_dma(struct spi_master *master) 554{ 555 if (master->dma_rx) { 556 dma_release_channel(master->dma_rx); 557 master->dma_rx = NULL; 558 } 559 if (master->dma_tx) { 560 dma_release_channel(master->dma_tx); 561 master->dma_tx = NULL; 562 } 563} 564 565/* This function is called by the DMA driver from tasklet context */ 566static void dma_callback(void *data) 567{ 568 struct spi_master *master = data; 569 struct atmel_spi *as = spi_master_get_devdata(master); 570 571 if (is_vmalloc_addr(as->current_transfer->rx_buf) && 572 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 573 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf, 574 as->current_transfer->len); 575 } 576 complete(&as->xfer_completion); 577} 578 579/* 580 * Next transfer using PIO without FIFO. 581 */ 582static void atmel_spi_next_xfer_single(struct spi_master *master, 583 struct spi_transfer *xfer) 584{ 585 struct atmel_spi *as = spi_master_get_devdata(master); 586 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 587 588 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); 589 590 /* Make sure data is not remaining in RDR */ 591 spi_readl(as, RDR); 592 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 593 spi_readl(as, RDR); 594 cpu_relax(); 595 } 596 597 if (xfer->bits_per_word > 8) 598 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); 599 else 600 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); 601 602 dev_dbg(master->dev.parent, 603 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 604 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 605 xfer->bits_per_word); 606 607 /* Enable relevant interrupts */ 608 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); 609} 610 611/* 612 * Next transfer using PIO with FIFO. 613 */ 614static void atmel_spi_next_xfer_fifo(struct spi_master *master, 615 struct spi_transfer *xfer) 616{ 617 struct atmel_spi *as = spi_master_get_devdata(master); 618 u32 current_remaining_data, num_data; 619 u32 offset = xfer->len - as->current_remaining_bytes; 620 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset); 621 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset); 622 u16 td0, td1; 623 u32 fifomr; 624 625 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n"); 626 627 /* Compute the number of data to transfer in the current iteration */ 628 current_remaining_data = ((xfer->bits_per_word > 8) ? 629 ((u32)as->current_remaining_bytes >> 1) : 630 (u32)as->current_remaining_bytes); 631 num_data = min(current_remaining_data, as->fifo_size); 632 633 /* Flush RX and TX FIFOs */ 634 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR)); 635 while (spi_readl(as, FLR)) 636 cpu_relax(); 637 638 /* Set RX FIFO Threshold to the number of data to transfer */ 639 fifomr = spi_readl(as, FMR); 640 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr)); 641 642 /* Clear FIFO flags in the Status Register, especially RXFTHF */ 643 (void)spi_readl(as, SR); 644 645 /* Fill TX FIFO */ 646 while (num_data >= 2) { 647 if (xfer->bits_per_word > 8) { 648 td0 = *words++; 649 td1 = *words++; 650 } else { 651 td0 = *bytes++; 652 td1 = *bytes++; 653 } 654 655 spi_writel(as, TDR, (td1 << 16) | td0); 656 num_data -= 2; 657 } 658 659 if (num_data) { 660 if (xfer->bits_per_word > 8) 661 td0 = *words++; 662 else 663 td0 = *bytes++; 664 665 spi_writew(as, TDR, td0); 666 num_data--; 667 } 668 669 dev_dbg(master->dev.parent, 670 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n", 671 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 672 xfer->bits_per_word); 673 674 /* 675 * Enable RX FIFO Threshold Flag interrupt to be notified about 676 * transfer completion. 677 */ 678 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES)); 679} 680 681/* 682 * Next transfer using PIO. 683 */ 684static void atmel_spi_next_xfer_pio(struct spi_master *master, 685 struct spi_transfer *xfer) 686{ 687 struct atmel_spi *as = spi_master_get_devdata(master); 688 689 if (as->fifo_size) 690 atmel_spi_next_xfer_fifo(master, xfer); 691 else 692 atmel_spi_next_xfer_single(master, xfer); 693} 694 695/* 696 * Submit next transfer for DMA. 697 */ 698static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, 699 struct spi_transfer *xfer, 700 u32 *plen) 701 __must_hold(&as->lock) 702{ 703 struct atmel_spi *as = spi_master_get_devdata(master); 704 struct dma_chan *rxchan = master->dma_rx; 705 struct dma_chan *txchan = master->dma_tx; 706 struct dma_async_tx_descriptor *rxdesc; 707 struct dma_async_tx_descriptor *txdesc; 708 struct dma_slave_config slave_config; 709 dma_cookie_t cookie; 710 711 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); 712 713 /* Check that the channels are available */ 714 if (!rxchan || !txchan) 715 return -ENODEV; 716 717 /* release lock for DMA operations */ 718 atmel_spi_unlock(as); 719 720 *plen = xfer->len; 721 722 if (atmel_spi_dma_slave_config(as, &slave_config, 723 xfer->bits_per_word)) 724 goto err_exit; 725 726 /* Send both scatterlists */ 727 if (atmel_spi_is_vmalloc_xfer(xfer) && 728 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 729 rxdesc = dmaengine_prep_slave_single(rxchan, 730 as->dma_addr_rx_bbuf, 731 xfer->len, 732 DMA_DEV_TO_MEM, 733 DMA_PREP_INTERRUPT | 734 DMA_CTRL_ACK); 735 } else { 736 rxdesc = dmaengine_prep_slave_sg(rxchan, 737 xfer->rx_sg.sgl, 738 xfer->rx_sg.nents, 739 DMA_DEV_TO_MEM, 740 DMA_PREP_INTERRUPT | 741 DMA_CTRL_ACK); 742 } 743 if (!rxdesc) 744 goto err_dma; 745 746 if (atmel_spi_is_vmalloc_xfer(xfer) && 747 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 748 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len); 749 txdesc = dmaengine_prep_slave_single(txchan, 750 as->dma_addr_tx_bbuf, 751 xfer->len, DMA_MEM_TO_DEV, 752 DMA_PREP_INTERRUPT | 753 DMA_CTRL_ACK); 754 } else { 755 txdesc = dmaengine_prep_slave_sg(txchan, 756 xfer->tx_sg.sgl, 757 xfer->tx_sg.nents, 758 DMA_MEM_TO_DEV, 759 DMA_PREP_INTERRUPT | 760 DMA_CTRL_ACK); 761 } 762 if (!txdesc) 763 goto err_dma; 764 765 dev_dbg(master->dev.parent, 766 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 767 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, 768 xfer->rx_buf, (unsigned long long)xfer->rx_dma); 769 770 /* Enable relevant interrupts */ 771 spi_writel(as, IER, SPI_BIT(OVRES)); 772 773 /* Put the callback on the RX transfer only, that should finish last */ 774 rxdesc->callback = dma_callback; 775 rxdesc->callback_param = master; 776 777 /* Submit and fire RX and TX with TX last so we're ready to read! */ 778 cookie = rxdesc->tx_submit(rxdesc); 779 if (dma_submit_error(cookie)) 780 goto err_dma; 781 cookie = txdesc->tx_submit(txdesc); 782 if (dma_submit_error(cookie)) 783 goto err_dma; 784 rxchan->device->device_issue_pending(rxchan); 785 txchan->device->device_issue_pending(txchan); 786 787 /* take back lock */ 788 atmel_spi_lock(as); 789 return 0; 790 791err_dma: 792 spi_writel(as, IDR, SPI_BIT(OVRES)); 793 atmel_spi_stop_dma(master); 794err_exit: 795 atmel_spi_lock(as); 796 return -ENOMEM; 797} 798 799static void atmel_spi_next_xfer_data(struct spi_master *master, 800 struct spi_transfer *xfer, 801 dma_addr_t *tx_dma, 802 dma_addr_t *rx_dma, 803 u32 *plen) 804{ 805 *rx_dma = xfer->rx_dma + xfer->len - *plen; 806 *tx_dma = xfer->tx_dma + xfer->len - *plen; 807 if (*plen > master->max_dma_len) 808 *plen = master->max_dma_len; 809} 810 811static int atmel_spi_set_xfer_speed(struct atmel_spi *as, 812 struct spi_device *spi, 813 struct spi_transfer *xfer) 814{ 815 u32 scbr, csr; 816 unsigned long bus_hz; 817 int chip_select; 818 819 if (spi->cs_gpiod) 820 chip_select = as->native_cs_for_gpio; 821 else 822 chip_select = spi->chip_select; 823 824 /* v1 chips start out at half the peripheral bus speed. */ 825 bus_hz = as->spi_clk; 826 if (!atmel_spi_is_v2(as)) 827 bus_hz /= 2; 828 829 /* 830 * Calculate the lowest divider that satisfies the 831 * constraint, assuming div32/fdiv/mbz == 0. 832 */ 833 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); 834 835 /* 836 * If the resulting divider doesn't fit into the 837 * register bitfield, we can't satisfy the constraint. 838 */ 839 if (scbr >= (1 << SPI_SCBR_SIZE)) { 840 dev_err(&spi->dev, 841 "setup: %d Hz too slow, scbr %u; min %ld Hz\n", 842 xfer->speed_hz, scbr, bus_hz/255); 843 return -EINVAL; 844 } 845 if (scbr == 0) { 846 dev_err(&spi->dev, 847 "setup: %d Hz too high, scbr %u; max %ld Hz\n", 848 xfer->speed_hz, scbr, bus_hz); 849 return -EINVAL; 850 } 851 csr = spi_readl(as, CSR0 + 4 * chip_select); 852 csr = SPI_BFINS(SCBR, scbr, csr); 853 spi_writel(as, CSR0 + 4 * chip_select, csr); 854 xfer->effective_speed_hz = bus_hz / scbr; 855 856 return 0; 857} 858 859/* 860 * Submit next transfer for PDC. 861 * lock is held, spi irq is blocked 862 */ 863static void atmel_spi_pdc_next_xfer(struct spi_master *master, 864 struct spi_transfer *xfer) 865{ 866 struct atmel_spi *as = spi_master_get_devdata(master); 867 u32 len; 868 dma_addr_t tx_dma, rx_dma; 869 870 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 871 872 len = as->current_remaining_bytes; 873 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 874 as->current_remaining_bytes -= len; 875 876 spi_writel(as, RPR, rx_dma); 877 spi_writel(as, TPR, tx_dma); 878 879 if (xfer->bits_per_word > 8) 880 len >>= 1; 881 spi_writel(as, RCR, len); 882 spi_writel(as, TCR, len); 883 884 dev_dbg(&master->dev, 885 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 886 xfer, xfer->len, xfer->tx_buf, 887 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 888 (unsigned long long)xfer->rx_dma); 889 890 if (as->current_remaining_bytes) { 891 len = as->current_remaining_bytes; 892 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 893 as->current_remaining_bytes -= len; 894 895 spi_writel(as, RNPR, rx_dma); 896 spi_writel(as, TNPR, tx_dma); 897 898 if (xfer->bits_per_word > 8) 899 len >>= 1; 900 spi_writel(as, RNCR, len); 901 spi_writel(as, TNCR, len); 902 903 dev_dbg(&master->dev, 904 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 905 xfer, xfer->len, xfer->tx_buf, 906 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 907 (unsigned long long)xfer->rx_dma); 908 } 909 910 /* REVISIT: We're waiting for RXBUFF before we start the next 911 * transfer because we need to handle some difficult timing 912 * issues otherwise. If we wait for TXBUFE in one transfer and 913 * then starts waiting for RXBUFF in the next, it's difficult 914 * to tell the difference between the RXBUFF interrupt we're 915 * actually waiting for and the RXBUFF interrupt of the 916 * previous transfer. 917 * 918 * It should be doable, though. Just not now... 919 */ 920 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); 921 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 922} 923 924/* 925 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 926 * - The buffer is either valid for CPU access, else NULL 927 * - If the buffer is valid, so is its DMA address 928 * 929 * This driver manages the dma address unless message->is_dma_mapped. 930 */ 931static int 932atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) 933{ 934 struct device *dev = &as->pdev->dev; 935 936 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; 937 if (xfer->tx_buf) { 938 /* tx_buf is a const void* where we need a void * for the dma 939 * mapping */ 940 void *nonconst_tx = (void *)xfer->tx_buf; 941 942 xfer->tx_dma = dma_map_single(dev, 943 nonconst_tx, xfer->len, 944 DMA_TO_DEVICE); 945 if (dma_mapping_error(dev, xfer->tx_dma)) 946 return -ENOMEM; 947 } 948 if (xfer->rx_buf) { 949 xfer->rx_dma = dma_map_single(dev, 950 xfer->rx_buf, xfer->len, 951 DMA_FROM_DEVICE); 952 if (dma_mapping_error(dev, xfer->rx_dma)) { 953 if (xfer->tx_buf) 954 dma_unmap_single(dev, 955 xfer->tx_dma, xfer->len, 956 DMA_TO_DEVICE); 957 return -ENOMEM; 958 } 959 } 960 return 0; 961} 962 963static void atmel_spi_dma_unmap_xfer(struct spi_master *master, 964 struct spi_transfer *xfer) 965{ 966 if (xfer->tx_dma != INVALID_DMA_ADDRESS) 967 dma_unmap_single(master->dev.parent, xfer->tx_dma, 968 xfer->len, DMA_TO_DEVICE); 969 if (xfer->rx_dma != INVALID_DMA_ADDRESS) 970 dma_unmap_single(master->dev.parent, xfer->rx_dma, 971 xfer->len, DMA_FROM_DEVICE); 972} 973 974static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) 975{ 976 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 977} 978 979static void 980atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) 981{ 982 u8 *rxp; 983 u16 *rxp16; 984 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 985 986 if (xfer->bits_per_word > 8) { 987 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); 988 *rxp16 = spi_readl(as, RDR); 989 } else { 990 rxp = ((u8 *)xfer->rx_buf) + xfer_pos; 991 *rxp = spi_readl(as, RDR); 992 } 993 if (xfer->bits_per_word > 8) { 994 if (as->current_remaining_bytes > 2) 995 as->current_remaining_bytes -= 2; 996 else 997 as->current_remaining_bytes = 0; 998 } else { 999 as->current_remaining_bytes--; 1000 } 1001} 1002 1003static void 1004atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) 1005{ 1006 u32 fifolr = spi_readl(as, FLR); 1007 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr); 1008 u32 offset = xfer->len - as->current_remaining_bytes; 1009 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset); 1010 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset); 1011 u16 rd; /* RD field is the lowest 16 bits of RDR */ 1012 1013 /* Update the number of remaining bytes to transfer */ 1014 num_bytes = ((xfer->bits_per_word > 8) ? 1015 (num_data << 1) : 1016 num_data); 1017 1018 if (as->current_remaining_bytes > num_bytes) 1019 as->current_remaining_bytes -= num_bytes; 1020 else 1021 as->current_remaining_bytes = 0; 1022 1023 /* Handle odd number of bytes when data are more than 8bit width */ 1024 if (xfer->bits_per_word > 8) 1025 as->current_remaining_bytes &= ~0x1; 1026 1027 /* Read data */ 1028 while (num_data) { 1029 rd = spi_readl(as, RDR); 1030 if (xfer->bits_per_word > 8) 1031 *words++ = rd; 1032 else 1033 *bytes++ = rd; 1034 num_data--; 1035 } 1036} 1037 1038/* Called from IRQ 1039 * 1040 * Must update "current_remaining_bytes" to keep track of data 1041 * to transfer. 1042 */ 1043static void 1044atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 1045{ 1046 if (as->fifo_size) 1047 atmel_spi_pump_fifo_data(as, xfer); 1048 else 1049 atmel_spi_pump_single_data(as, xfer); 1050} 1051 1052/* Interrupt 1053 * 1054 * No need for locking in this Interrupt handler: done_status is the 1055 * only information modified. 1056 */ 1057static irqreturn_t 1058atmel_spi_pio_interrupt(int irq, void *dev_id) 1059{ 1060 struct spi_master *master = dev_id; 1061 struct atmel_spi *as = spi_master_get_devdata(master); 1062 u32 status, pending, imr; 1063 struct spi_transfer *xfer; 1064 int ret = IRQ_NONE; 1065 1066 imr = spi_readl(as, IMR); 1067 status = spi_readl(as, SR); 1068 pending = status & imr; 1069 1070 if (pending & SPI_BIT(OVRES)) { 1071 ret = IRQ_HANDLED; 1072 spi_writel(as, IDR, SPI_BIT(OVRES)); 1073 dev_warn(master->dev.parent, "overrun\n"); 1074 1075 /* 1076 * When we get an overrun, we disregard the current 1077 * transfer. Data will not be copied back from any 1078 * bounce buffer and msg->actual_len will not be 1079 * updated with the last xfer. 1080 * 1081 * We will also not process any remaning transfers in 1082 * the message. 1083 */ 1084 as->done_status = -EIO; 1085 smp_wmb(); 1086 1087 /* Clear any overrun happening while cleaning up */ 1088 spi_readl(as, SR); 1089 1090 complete(&as->xfer_completion); 1091 1092 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) { 1093 atmel_spi_lock(as); 1094 1095 if (as->current_remaining_bytes) { 1096 ret = IRQ_HANDLED; 1097 xfer = as->current_transfer; 1098 atmel_spi_pump_pio_data(as, xfer); 1099 if (!as->current_remaining_bytes) 1100 spi_writel(as, IDR, pending); 1101 1102 complete(&as->xfer_completion); 1103 } 1104 1105 atmel_spi_unlock(as); 1106 } else { 1107 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); 1108 ret = IRQ_HANDLED; 1109 spi_writel(as, IDR, pending); 1110 } 1111 1112 return ret; 1113} 1114 1115static irqreturn_t 1116atmel_spi_pdc_interrupt(int irq, void *dev_id) 1117{ 1118 struct spi_master *master = dev_id; 1119 struct atmel_spi *as = spi_master_get_devdata(master); 1120 u32 status, pending, imr; 1121 int ret = IRQ_NONE; 1122 1123 imr = spi_readl(as, IMR); 1124 status = spi_readl(as, SR); 1125 pending = status & imr; 1126 1127 if (pending & SPI_BIT(OVRES)) { 1128 1129 ret = IRQ_HANDLED; 1130 1131 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 1132 | SPI_BIT(OVRES))); 1133 1134 /* Clear any overrun happening while cleaning up */ 1135 spi_readl(as, SR); 1136 1137 as->done_status = -EIO; 1138 1139 complete(&as->xfer_completion); 1140 1141 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 1142 ret = IRQ_HANDLED; 1143 1144 spi_writel(as, IDR, pending); 1145 1146 complete(&as->xfer_completion); 1147 } 1148 1149 return ret; 1150} 1151 1152static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as) 1153{ 1154 struct spi_delay *delay = &spi->word_delay; 1155 u32 value = delay->value; 1156 1157 switch (delay->unit) { 1158 case SPI_DELAY_UNIT_NSECS: 1159 value /= 1000; 1160 break; 1161 case SPI_DELAY_UNIT_USECS: 1162 break; 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 return (as->spi_clk / 1000000 * value) >> 5; 1168} 1169 1170static void initialize_native_cs_for_gpio(struct atmel_spi *as) 1171{ 1172 int i; 1173 struct spi_master *master = platform_get_drvdata(as->pdev); 1174 1175 if (!as->native_cs_free) 1176 return; /* already initialized */ 1177 1178 if (!master->cs_gpiods) 1179 return; /* No CS GPIO */ 1180 1181 /* 1182 * On the first version of the controller (AT91RM9200), CS0 1183 * can't be used associated with GPIO 1184 */ 1185 if (atmel_spi_is_v2(as)) 1186 i = 0; 1187 else 1188 i = 1; 1189 1190 for (; i < 4; i++) 1191 if (master->cs_gpiods[i]) 1192 as->native_cs_free |= BIT(i); 1193 1194 if (as->native_cs_free) 1195 as->native_cs_for_gpio = ffs(as->native_cs_free); 1196} 1197 1198static int atmel_spi_setup(struct spi_device *spi) 1199{ 1200 struct atmel_spi *as; 1201 struct atmel_spi_device *asd; 1202 u32 csr; 1203 unsigned int bits = spi->bits_per_word; 1204 int chip_select; 1205 int word_delay_csr; 1206 1207 as = spi_master_get_devdata(spi->master); 1208 1209 /* see notes above re chipselect */ 1210 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) { 1211 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 1212 return -EINVAL; 1213 } 1214 1215 /* Setup() is called during spi_register_controller(aka 1216 * spi_register_master) but after all membmers of the cs_gpiod 1217 * array have been filled, so we can looked for which native 1218 * CS will be free for using with GPIO 1219 */ 1220 initialize_native_cs_for_gpio(as); 1221 1222 if (spi->cs_gpiod && as->native_cs_free) { 1223 dev_err(&spi->dev, 1224 "No native CS available to support this GPIO CS\n"); 1225 return -EBUSY; 1226 } 1227 1228 if (spi->cs_gpiod) 1229 chip_select = as->native_cs_for_gpio; 1230 else 1231 chip_select = spi->chip_select; 1232 1233 csr = SPI_BF(BITS, bits - 8); 1234 if (spi->mode & SPI_CPOL) 1235 csr |= SPI_BIT(CPOL); 1236 if (!(spi->mode & SPI_CPHA)) 1237 csr |= SPI_BIT(NCPHA); 1238 1239 if (!spi->cs_gpiod) 1240 csr |= SPI_BIT(CSAAT); 1241 csr |= SPI_BF(DLYBS, 0); 1242 1243 word_delay_csr = atmel_word_delay_csr(spi, as); 1244 if (word_delay_csr < 0) 1245 return word_delay_csr; 1246 1247 /* DLYBCT adds delays between words. This is useful for slow devices 1248 * that need a bit of time to setup the next transfer. 1249 */ 1250 csr |= SPI_BF(DLYBCT, word_delay_csr); 1251 1252 asd = spi->controller_state; 1253 if (!asd) { 1254 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); 1255 if (!asd) 1256 return -ENOMEM; 1257 1258 spi->controller_state = asd; 1259 } 1260 1261 asd->csr = csr; 1262 1263 dev_dbg(&spi->dev, 1264 "setup: bpw %u mode 0x%x -> csr%d %08x\n", 1265 bits, spi->mode, spi->chip_select, csr); 1266 1267 if (!atmel_spi_is_v2(as)) 1268 spi_writel(as, CSR0 + 4 * chip_select, csr); 1269 1270 return 0; 1271} 1272 1273static void atmel_spi_set_cs(struct spi_device *spi, bool enable) 1274{ 1275 struct atmel_spi *as = spi_master_get_devdata(spi->master); 1276 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW 1277 * since we already have routines for activate/deactivate translate 1278 * high/low to active/inactive 1279 */ 1280 enable = (!!(spi->mode & SPI_CS_HIGH) == enable); 1281 1282 if (enable) { 1283 cs_activate(as, spi); 1284 } else { 1285 cs_deactivate(as, spi); 1286 } 1287 1288} 1289 1290static int atmel_spi_one_transfer(struct spi_master *master, 1291 struct spi_device *spi, 1292 struct spi_transfer *xfer) 1293{ 1294 struct atmel_spi *as; 1295 u8 bits; 1296 u32 len; 1297 struct atmel_spi_device *asd; 1298 int timeout; 1299 int ret; 1300 unsigned long dma_timeout; 1301 1302 as = spi_master_get_devdata(master); 1303 /* This lock was orignally taken in atmel_spi_trasfer_one_message */ 1304 atmel_spi_lock(as); 1305 1306 asd = spi->controller_state; 1307 bits = (asd->csr >> 4) & 0xf; 1308 if (bits != xfer->bits_per_word - 8) { 1309 dev_dbg(&spi->dev, 1310 "you can't yet change bits_per_word in transfers\n"); 1311 return -ENOPROTOOPT; 1312 } 1313 1314 /* 1315 * DMA map early, for performance (empties dcache ASAP) and 1316 * better fault reporting. 1317 */ 1318 if ((!master->cur_msg->is_dma_mapped) 1319 && as->use_pdc) { 1320 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1321 return -ENOMEM; 1322 } 1323 1324 atmel_spi_set_xfer_speed(as, spi, xfer); 1325 1326 as->done_status = 0; 1327 as->current_transfer = xfer; 1328 as->current_remaining_bytes = xfer->len; 1329 while (as->current_remaining_bytes) { 1330 reinit_completion(&as->xfer_completion); 1331 1332 if (as->use_pdc) { 1333 atmel_spi_pdc_next_xfer(master, xfer); 1334 } else if (atmel_spi_use_dma(as, xfer)) { 1335 len = as->current_remaining_bytes; 1336 ret = atmel_spi_next_xfer_dma_submit(master, 1337 xfer, &len); 1338 if (ret) { 1339 dev_err(&spi->dev, 1340 "unable to use DMA, fallback to PIO\n"); 1341 as->done_status = ret; 1342 break; 1343 } else { 1344 as->current_remaining_bytes -= len; 1345 if (as->current_remaining_bytes < 0) 1346 as->current_remaining_bytes = 0; 1347 } 1348 } else { 1349 atmel_spi_next_xfer_pio(master, xfer); 1350 } 1351 1352 /* interrupts are disabled, so free the lock for schedule */ 1353 atmel_spi_unlock(as); 1354 dma_timeout = wait_for_completion_timeout(&as->xfer_completion, 1355 SPI_DMA_TIMEOUT); 1356 atmel_spi_lock(as); 1357 if (WARN_ON(dma_timeout == 0)) { 1358 dev_err(&spi->dev, "spi transfer timeout\n"); 1359 as->done_status = -EIO; 1360 } 1361 1362 if (as->done_status) 1363 break; 1364 } 1365 1366 if (as->done_status) { 1367 if (as->use_pdc) { 1368 dev_warn(master->dev.parent, 1369 "overrun (%u/%u remaining)\n", 1370 spi_readl(as, TCR), spi_readl(as, RCR)); 1371 1372 /* 1373 * Clean up DMA registers and make sure the data 1374 * registers are empty. 1375 */ 1376 spi_writel(as, RNCR, 0); 1377 spi_writel(as, TNCR, 0); 1378 spi_writel(as, RCR, 0); 1379 spi_writel(as, TCR, 0); 1380 for (timeout = 1000; timeout; timeout--) 1381 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) 1382 break; 1383 if (!timeout) 1384 dev_warn(master->dev.parent, 1385 "timeout waiting for TXEMPTY"); 1386 while (spi_readl(as, SR) & SPI_BIT(RDRF)) 1387 spi_readl(as, RDR); 1388 1389 /* Clear any overrun happening while cleaning up */ 1390 spi_readl(as, SR); 1391 1392 } else if (atmel_spi_use_dma(as, xfer)) { 1393 atmel_spi_stop_dma(master); 1394 } 1395 } 1396 1397 if (!master->cur_msg->is_dma_mapped 1398 && as->use_pdc) 1399 atmel_spi_dma_unmap_xfer(master, xfer); 1400 1401 if (as->use_pdc) 1402 atmel_spi_disable_pdc_transfer(as); 1403 1404 atmel_spi_unlock(as); 1405 1406 return as->done_status; 1407} 1408 1409static void atmel_spi_cleanup(struct spi_device *spi) 1410{ 1411 struct atmel_spi_device *asd = spi->controller_state; 1412 1413 if (!asd) 1414 return; 1415 1416 spi->controller_state = NULL; 1417 kfree(asd); 1418} 1419 1420static inline unsigned int atmel_get_version(struct atmel_spi *as) 1421{ 1422 return spi_readl(as, VERSION) & 0x00000fff; 1423} 1424 1425static void atmel_get_caps(struct atmel_spi *as) 1426{ 1427 unsigned int version; 1428 1429 version = atmel_get_version(as); 1430 1431 as->caps.is_spi2 = version > 0x121; 1432 as->caps.has_wdrbt = version >= 0x210; 1433 as->caps.has_dma_support = version >= 0x212; 1434 as->caps.has_pdc_support = version < 0x212; 1435} 1436 1437static void atmel_spi_init(struct atmel_spi *as) 1438{ 1439 spi_writel(as, CR, SPI_BIT(SWRST)); 1440 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1441 1442 /* It is recommended to enable FIFOs first thing after reset */ 1443 if (as->fifo_size) 1444 spi_writel(as, CR, SPI_BIT(FIFOEN)); 1445 1446 if (as->caps.has_wdrbt) { 1447 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1448 | SPI_BIT(MSTR)); 1449 } else { 1450 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1451 } 1452 1453 if (as->use_pdc) 1454 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1455 spi_writel(as, CR, SPI_BIT(SPIEN)); 1456} 1457 1458static int atmel_spi_probe(struct platform_device *pdev) 1459{ 1460 struct resource *regs; 1461 int irq; 1462 struct clk *clk; 1463 int ret; 1464 struct spi_master *master; 1465 struct atmel_spi *as; 1466 1467 /* Select default pin state */ 1468 pinctrl_pm_select_default_state(&pdev->dev); 1469 1470 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1471 if (!regs) 1472 return -ENXIO; 1473 1474 irq = platform_get_irq(pdev, 0); 1475 if (irq < 0) 1476 return irq; 1477 1478 clk = devm_clk_get(&pdev->dev, "spi_clk"); 1479 if (IS_ERR(clk)) 1480 return PTR_ERR(clk); 1481 1482 /* setup spi core then atmel-specific driver state */ 1483 master = spi_alloc_master(&pdev->dev, sizeof(*as)); 1484 if (!master) 1485 return -ENOMEM; 1486 1487 /* the spi->mode bits understood by this driver: */ 1488 master->use_gpio_descriptors = true; 1489 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1490 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 1491 master->dev.of_node = pdev->dev.of_node; 1492 master->bus_num = pdev->id; 1493 master->num_chipselect = 4; 1494 master->setup = atmel_spi_setup; 1495 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX | 1496 SPI_MASTER_GPIO_SS); 1497 master->transfer_one = atmel_spi_one_transfer; 1498 master->set_cs = atmel_spi_set_cs; 1499 master->cleanup = atmel_spi_cleanup; 1500 master->auto_runtime_pm = true; 1501 master->max_dma_len = SPI_MAX_DMA_XFER; 1502 master->can_dma = atmel_spi_can_dma; 1503 platform_set_drvdata(pdev, master); 1504 1505 as = spi_master_get_devdata(master); 1506 1507 spin_lock_init(&as->lock); 1508 1509 as->pdev = pdev; 1510 as->regs = devm_ioremap_resource(&pdev->dev, regs); 1511 if (IS_ERR(as->regs)) { 1512 ret = PTR_ERR(as->regs); 1513 goto out_unmap_regs; 1514 } 1515 as->phybase = regs->start; 1516 as->irq = irq; 1517 as->clk = clk; 1518 1519 init_completion(&as->xfer_completion); 1520 1521 atmel_get_caps(as); 1522 1523 as->use_dma = false; 1524 as->use_pdc = false; 1525 if (as->caps.has_dma_support) { 1526 ret = atmel_spi_configure_dma(master, as); 1527 if (ret == 0) { 1528 as->use_dma = true; 1529 } else if (ret == -EPROBE_DEFER) { 1530 goto out_unmap_regs; 1531 } 1532 } else if (as->caps.has_pdc_support) { 1533 as->use_pdc = true; 1534 } 1535 1536 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1537 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev, 1538 SPI_MAX_DMA_XFER, 1539 &as->dma_addr_rx_bbuf, 1540 GFP_KERNEL | GFP_DMA); 1541 if (!as->addr_rx_bbuf) { 1542 as->use_dma = false; 1543 } else { 1544 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev, 1545 SPI_MAX_DMA_XFER, 1546 &as->dma_addr_tx_bbuf, 1547 GFP_KERNEL | GFP_DMA); 1548 if (!as->addr_tx_bbuf) { 1549 as->use_dma = false; 1550 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1551 as->addr_rx_bbuf, 1552 as->dma_addr_rx_bbuf); 1553 } 1554 } 1555 if (!as->use_dma) 1556 dev_info(master->dev.parent, 1557 " can not allocate dma coherent memory\n"); 1558 } 1559 1560 if (as->caps.has_dma_support && !as->use_dma) 1561 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1562 1563 if (as->use_pdc) { 1564 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, 1565 0, dev_name(&pdev->dev), master); 1566 } else { 1567 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, 1568 0, dev_name(&pdev->dev), master); 1569 } 1570 if (ret) 1571 goto out_unmap_regs; 1572 1573 /* Initialize the hardware */ 1574 ret = clk_prepare_enable(clk); 1575 if (ret) 1576 goto out_free_irq; 1577 1578 as->spi_clk = clk_get_rate(clk); 1579 1580 as->fifo_size = 0; 1581 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", 1582 &as->fifo_size)) { 1583 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); 1584 } 1585 1586 atmel_spi_init(as); 1587 1588 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1589 pm_runtime_use_autosuspend(&pdev->dev); 1590 pm_runtime_set_active(&pdev->dev); 1591 pm_runtime_enable(&pdev->dev); 1592 1593 ret = devm_spi_register_master(&pdev->dev, master); 1594 if (ret) 1595 goto out_free_dma; 1596 1597 /* go! */ 1598 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n", 1599 atmel_get_version(as), (unsigned long)regs->start, 1600 irq); 1601 1602 return 0; 1603 1604out_free_dma: 1605 pm_runtime_disable(&pdev->dev); 1606 pm_runtime_set_suspended(&pdev->dev); 1607 1608 if (as->use_dma) 1609 atmel_spi_release_dma(master); 1610 1611 spi_writel(as, CR, SPI_BIT(SWRST)); 1612 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1613 clk_disable_unprepare(clk); 1614out_free_irq: 1615out_unmap_regs: 1616 spi_master_put(master); 1617 return ret; 1618} 1619 1620static int atmel_spi_remove(struct platform_device *pdev) 1621{ 1622 struct spi_master *master = platform_get_drvdata(pdev); 1623 struct atmel_spi *as = spi_master_get_devdata(master); 1624 1625 pm_runtime_get_sync(&pdev->dev); 1626 1627 /* reset the hardware and block queue progress */ 1628 if (as->use_dma) { 1629 atmel_spi_stop_dma(master); 1630 atmel_spi_release_dma(master); 1631 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1632 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1633 as->addr_tx_bbuf, 1634 as->dma_addr_tx_bbuf); 1635 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1636 as->addr_rx_bbuf, 1637 as->dma_addr_rx_bbuf); 1638 } 1639 } 1640 1641 spin_lock_irq(&as->lock); 1642 spi_writel(as, CR, SPI_BIT(SWRST)); 1643 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1644 spi_readl(as, SR); 1645 spin_unlock_irq(&as->lock); 1646 1647 clk_disable_unprepare(as->clk); 1648 1649 pm_runtime_put_noidle(&pdev->dev); 1650 pm_runtime_disable(&pdev->dev); 1651 1652 return 0; 1653} 1654 1655#ifdef CONFIG_PM 1656static int atmel_spi_runtime_suspend(struct device *dev) 1657{ 1658 struct spi_master *master = dev_get_drvdata(dev); 1659 struct atmel_spi *as = spi_master_get_devdata(master); 1660 1661 clk_disable_unprepare(as->clk); 1662 pinctrl_pm_select_sleep_state(dev); 1663 1664 return 0; 1665} 1666 1667static int atmel_spi_runtime_resume(struct device *dev) 1668{ 1669 struct spi_master *master = dev_get_drvdata(dev); 1670 struct atmel_spi *as = spi_master_get_devdata(master); 1671 1672 pinctrl_pm_select_default_state(dev); 1673 1674 return clk_prepare_enable(as->clk); 1675} 1676 1677#ifdef CONFIG_PM_SLEEP 1678static int atmel_spi_suspend(struct device *dev) 1679{ 1680 struct spi_master *master = dev_get_drvdata(dev); 1681 int ret; 1682 1683 /* Stop the queue running */ 1684 ret = spi_master_suspend(master); 1685 if (ret) 1686 return ret; 1687 1688 if (!pm_runtime_suspended(dev)) 1689 atmel_spi_runtime_suspend(dev); 1690 1691 return 0; 1692} 1693 1694static int atmel_spi_resume(struct device *dev) 1695{ 1696 struct spi_master *master = dev_get_drvdata(dev); 1697 struct atmel_spi *as = spi_master_get_devdata(master); 1698 int ret; 1699 1700 ret = clk_prepare_enable(as->clk); 1701 if (ret) 1702 return ret; 1703 1704 atmel_spi_init(as); 1705 1706 clk_disable_unprepare(as->clk); 1707 1708 if (!pm_runtime_suspended(dev)) { 1709 ret = atmel_spi_runtime_resume(dev); 1710 if (ret) 1711 return ret; 1712 } 1713 1714 /* Start the queue running */ 1715 return spi_master_resume(master); 1716} 1717#endif 1718 1719static const struct dev_pm_ops atmel_spi_pm_ops = { 1720 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume) 1721 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend, 1722 atmel_spi_runtime_resume, NULL) 1723}; 1724#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) 1725#else 1726#define ATMEL_SPI_PM_OPS NULL 1727#endif 1728 1729static const struct of_device_id atmel_spi_dt_ids[] = { 1730 { .compatible = "atmel,at91rm9200-spi" }, 1731 { /* sentinel */ } 1732}; 1733 1734MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); 1735 1736static struct platform_driver atmel_spi_driver = { 1737 .driver = { 1738 .name = "atmel_spi", 1739 .pm = ATMEL_SPI_PM_OPS, 1740 .of_match_table = atmel_spi_dt_ids, 1741 }, 1742 .probe = atmel_spi_probe, 1743 .remove = atmel_spi_remove, 1744}; 1745module_platform_driver(atmel_spi_driver); 1746 1747MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); 1748MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1749MODULE_LICENSE("GPL"); 1750MODULE_ALIAS("platform:atmel_spi"); 1751