1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2// Copyright(c) 2015-17 Intel Corporation. 3 4/* 5 * Soundwire Intel Master Driver 6 */ 7 8#include <linux/acpi.h> 9#include <linux/debugfs.h> 10#include <linux/delay.h> 11#include <linux/module.h> 12#include <linux/interrupt.h> 13#include <linux/io.h> 14#include <linux/platform_device.h> 15#include <sound/pcm_params.h> 16#include <linux/pm_runtime.h> 17#include <sound/soc.h> 18#include <linux/soundwire/sdw_registers.h> 19#include <linux/soundwire/sdw.h> 20#include <linux/soundwire/sdw_intel.h> 21#include "cadence_master.h" 22#include "bus.h" 23#include "intel.h" 24 25#define INTEL_MASTER_SUSPEND_DELAY_MS 3000 26 27/* 28 * debug/config flags for the Intel SoundWire Master. 29 * 30 * Since we may have multiple masters active, we can have up to 8 31 * flags reused in each byte, with master0 using the ls-byte, etc. 32 */ 33 34#define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0) 35#define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1) 36#define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2) 37#define SDW_INTEL_MASTER_DISABLE_MULTI_LINK BIT(3) 38 39static int md_flags; 40module_param_named(sdw_md_flags, md_flags, int, 0444); 41MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)"); 42 43/* Intel SHIM Registers Definition */ 44#define SDW_SHIM_LCAP 0x0 45#define SDW_SHIM_LCTL 0x4 46#define SDW_SHIM_IPPTR 0x8 47#define SDW_SHIM_SYNC 0xC 48 49#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 50#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 51#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 52#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 53#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 54#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 55 56#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 57#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 58#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 59#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 60#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 61 62#define SDW_SHIM_WAKEEN 0x190 63#define SDW_SHIM_WAKESTS 0x192 64 65#define SDW_SHIM_LCTL_SPA BIT(0) 66#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) 67#define SDW_SHIM_LCTL_CPA BIT(8) 68#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) 69 70#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 71#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) 72#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 73#define SDW_SHIM_SYNC_SYNCCPU BIT(15) 74#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 75#define SDW_SHIM_SYNC_CMDSYNC BIT(16) 76#define SDW_SHIM_SYNC_SYNCGO BIT(24) 77 78#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 79#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 80#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 81 82#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 83#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 84#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 85#define SDW_SHIM_PCMSYCM_DIR BIT(15) 86 87#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 88#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 89#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 90#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 91 92#define SDW_SHIM_IOCTL_MIF BIT(0) 93#define SDW_SHIM_IOCTL_CO BIT(1) 94#define SDW_SHIM_IOCTL_COE BIT(2) 95#define SDW_SHIM_IOCTL_DO BIT(3) 96#define SDW_SHIM_IOCTL_DOE BIT(4) 97#define SDW_SHIM_IOCTL_BKE BIT(5) 98#define SDW_SHIM_IOCTL_WPDD BIT(6) 99#define SDW_SHIM_IOCTL_CIBD BIT(8) 100#define SDW_SHIM_IOCTL_DIBD BIT(9) 101 102#define SDW_SHIM_CTMCTL_DACTQE BIT(0) 103#define SDW_SHIM_CTMCTL_DODS BIT(1) 104#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 105 106#define SDW_SHIM_WAKEEN_ENABLE BIT(0) 107#define SDW_SHIM_WAKESTS_STATUS BIT(0) 108 109/* Intel ALH Register definitions */ 110#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 111#define SDW_ALH_NUM_STREAMS 64 112 113#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 114#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 115#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 116 117enum intel_pdi_type { 118 INTEL_PDI_IN = 0, 119 INTEL_PDI_OUT = 1, 120 INTEL_PDI_BD = 2, 121}; 122 123#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 124 125/* 126 * Read, write helpers for HW registers 127 */ 128static inline int intel_readl(void __iomem *base, int offset) 129{ 130 return readl(base + offset); 131} 132 133static inline void intel_writel(void __iomem *base, int offset, int value) 134{ 135 writel(value, base + offset); 136} 137 138static inline u16 intel_readw(void __iomem *base, int offset) 139{ 140 return readw(base + offset); 141} 142 143static inline void intel_writew(void __iomem *base, int offset, u16 value) 144{ 145 writew(value, base + offset); 146} 147 148static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) 149{ 150 int timeout = 10; 151 u32 reg_read; 152 153 do { 154 reg_read = readl(base + offset); 155 if ((reg_read & mask) == target) 156 return 0; 157 158 timeout--; 159 usleep_range(50, 100); 160 } while (timeout != 0); 161 162 return -EAGAIN; 163} 164 165static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) 166{ 167 writel(value, base + offset); 168 return intel_wait_bit(base, offset, mask, 0); 169} 170 171static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) 172{ 173 writel(value, base + offset); 174 return intel_wait_bit(base, offset, mask, mask); 175} 176 177/* 178 * debugfs 179 */ 180#ifdef CONFIG_DEBUG_FS 181 182#define RD_BUF (2 * PAGE_SIZE) 183 184static ssize_t intel_sprintf(void __iomem *mem, bool l, 185 char *buf, size_t pos, unsigned int reg) 186{ 187 int value; 188 189 if (l) 190 value = intel_readl(mem, reg); 191 else 192 value = intel_readw(mem, reg); 193 194 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); 195} 196 197static int intel_reg_show(struct seq_file *s_file, void *data) 198{ 199 struct sdw_intel *sdw = s_file->private; 200 void __iomem *s = sdw->link_res->shim; 201 void __iomem *a = sdw->link_res->alh; 202 char *buf; 203 ssize_t ret; 204 int i, j; 205 unsigned int links, reg; 206 207 buf = kzalloc(RD_BUF, GFP_KERNEL); 208 if (!buf) 209 return -ENOMEM; 210 211 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); 212 213 ret = scnprintf(buf, RD_BUF, "Register Value\n"); 214 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); 215 216 for (i = 0; i < links; i++) { 217 reg = SDW_SHIM_LCAP + i * 4; 218 ret += intel_sprintf(s, true, buf, ret, reg); 219 } 220 221 for (i = 0; i < links; i++) { 222 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); 223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); 224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); 225 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); 226 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); 227 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); 228 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); 229 230 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); 231 232 /* 233 * the value 10 is the number of PDIs. We will need a 234 * cleanup to remove hard-coded Intel configurations 235 * from cadence_master.c 236 */ 237 for (j = 0; j < 10; j++) { 238 ret += intel_sprintf(s, false, buf, ret, 239 SDW_SHIM_PCMSYCHM(i, j)); 240 ret += intel_sprintf(s, false, buf, ret, 241 SDW_SHIM_PCMSYCHC(i, j)); 242 } 243 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); 244 245 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); 246 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); 247 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); 248 } 249 250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); 251 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); 252 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); 253 254 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); 255 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) 256 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); 257 258 seq_printf(s_file, "%s", buf); 259 kfree(buf); 260 261 return 0; 262} 263DEFINE_SHOW_ATTRIBUTE(intel_reg); 264 265static int intel_set_m_datamode(void *data, u64 value) 266{ 267 struct sdw_intel *sdw = data; 268 struct sdw_bus *bus = &sdw->cdns.bus; 269 270 if (value > SDW_PORT_DATA_MODE_STATIC_1) 271 return -EINVAL; 272 273 /* Userspace changed the hardware state behind the kernel's back */ 274 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 275 276 bus->params.m_data_mode = value; 277 278 return 0; 279} 280DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL, 281 intel_set_m_datamode, "%llu\n"); 282 283static int intel_set_s_datamode(void *data, u64 value) 284{ 285 struct sdw_intel *sdw = data; 286 struct sdw_bus *bus = &sdw->cdns.bus; 287 288 if (value > SDW_PORT_DATA_MODE_STATIC_1) 289 return -EINVAL; 290 291 /* Userspace changed the hardware state behind the kernel's back */ 292 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 293 294 bus->params.s_data_mode = value; 295 296 return 0; 297} 298DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL, 299 intel_set_s_datamode, "%llu\n"); 300 301static void intel_debugfs_init(struct sdw_intel *sdw) 302{ 303 struct dentry *root = sdw->cdns.bus.debugfs; 304 305 if (!root) 306 return; 307 308 sdw->debugfs = debugfs_create_dir("intel-sdw", root); 309 310 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, 311 &intel_reg_fops); 312 313 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw, 314 &intel_set_m_datamode_fops); 315 316 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw, 317 &intel_set_s_datamode_fops); 318 319 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); 320} 321 322static void intel_debugfs_exit(struct sdw_intel *sdw) 323{ 324 debugfs_remove_recursive(sdw->debugfs); 325} 326#else 327static void intel_debugfs_init(struct sdw_intel *sdw) {} 328static void intel_debugfs_exit(struct sdw_intel *sdw) {} 329#endif /* CONFIG_DEBUG_FS */ 330 331/* 332 * shim ops 333 */ 334 335static int intel_link_power_up(struct sdw_intel *sdw) 336{ 337 unsigned int link_id = sdw->instance; 338 void __iomem *shim = sdw->link_res->shim; 339 u32 *shim_mask = sdw->link_res->shim_mask; 340 struct sdw_bus *bus = &sdw->cdns.bus; 341 struct sdw_master_prop *prop = &bus->prop; 342 u32 spa_mask, cpa_mask; 343 u32 link_control; 344 int ret = 0; 345 u32 syncprd; 346 u32 sync_reg; 347 348 mutex_lock(sdw->link_res->shim_lock); 349 350 /* 351 * The hardware relies on an internal counter, typically 4kHz, 352 * to generate the SoundWire SSP - which defines a 'safe' 353 * synchronization point between commands and audio transport 354 * and allows for multi link synchronization. The SYNCPRD value 355 * is only dependent on the oscillator clock provided to 356 * the IP, so adjust based on _DSD properties reported in DSDT 357 * tables. The values reported are based on either 24MHz 358 * (CNL/CML) or 38.4 MHz (ICL/TGL+). 359 */ 360 if (prop->mclk_freq % 6000000) 361 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 362 else 363 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 364 365 if (!*shim_mask) { 366 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); 367 368 /* we first need to program the SyncPRD/CPU registers */ 369 dev_dbg(sdw->cdns.dev, 370 "%s: first link up, programming SYNCPRD\n", __func__); 371 372 /* set SyncPRD period */ 373 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 374 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD); 375 376 /* Set SyncCPU bit */ 377 sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 378 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 379 380 /* Link power up sequence */ 381 link_control = intel_readl(shim, SDW_SHIM_LCTL); 382 383 /* only power-up enabled links */ 384 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); 385 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 386 387 link_control |= spa_mask; 388 389 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 390 if (ret < 0) { 391 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); 392 goto out; 393 } 394 395 /* SyncCPU will change once link is active */ 396 ret = intel_wait_bit(shim, SDW_SHIM_SYNC, 397 SDW_SHIM_SYNC_SYNCCPU, 0); 398 if (ret < 0) { 399 dev_err(sdw->cdns.dev, 400 "Failed to set SHIM_SYNC: %d\n", ret); 401 goto out; 402 } 403 } 404 405 *shim_mask |= BIT(link_id); 406 407 sdw->cdns.link_up = true; 408out: 409 mutex_unlock(sdw->link_res->shim_lock); 410 411 return ret; 412} 413 414/* this needs to be called with shim_lock */ 415static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw) 416{ 417 void __iomem *shim = sdw->link_res->shim; 418 unsigned int link_id = sdw->instance; 419 u16 ioctl; 420 421 /* Switch to MIP from Glue logic */ 422 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 423 424 ioctl &= ~(SDW_SHIM_IOCTL_DOE); 425 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 426 usleep_range(10, 15); 427 428 ioctl &= ~(SDW_SHIM_IOCTL_DO); 429 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 430 usleep_range(10, 15); 431 432 ioctl |= (SDW_SHIM_IOCTL_MIF); 433 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 434 usleep_range(10, 15); 435 436 ioctl &= ~(SDW_SHIM_IOCTL_BKE); 437 ioctl &= ~(SDW_SHIM_IOCTL_COE); 438 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 439 usleep_range(10, 15); 440 441 /* at this point Master IP has full control of the I/Os */ 442} 443 444/* this needs to be called with shim_lock */ 445static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw) 446{ 447 unsigned int link_id = sdw->instance; 448 void __iomem *shim = sdw->link_res->shim; 449 u16 ioctl; 450 451 /* Glue logic */ 452 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 453 ioctl |= SDW_SHIM_IOCTL_BKE; 454 ioctl |= SDW_SHIM_IOCTL_COE; 455 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 456 usleep_range(10, 15); 457 458 ioctl &= ~(SDW_SHIM_IOCTL_MIF); 459 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 460 usleep_range(10, 15); 461 462 /* at this point Integration Glue has full control of the I/Os */ 463} 464 465static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop) 466{ 467 void __iomem *shim = sdw->link_res->shim; 468 unsigned int link_id = sdw->instance; 469 int ret = 0; 470 u16 ioctl = 0, act = 0; 471 472 mutex_lock(sdw->link_res->shim_lock); 473 474 /* Initialize Shim */ 475 ioctl |= SDW_SHIM_IOCTL_BKE; 476 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 477 usleep_range(10, 15); 478 479 ioctl |= SDW_SHIM_IOCTL_WPDD; 480 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 481 usleep_range(10, 15); 482 483 ioctl |= SDW_SHIM_IOCTL_DO; 484 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 485 usleep_range(10, 15); 486 487 ioctl |= SDW_SHIM_IOCTL_DOE; 488 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 489 usleep_range(10, 15); 490 491 intel_shim_glue_to_master_ip(sdw); 492 493 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); 494 act |= SDW_SHIM_CTMCTL_DACTQE; 495 act |= SDW_SHIM_CTMCTL_DODS; 496 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 497 usleep_range(10, 15); 498 499 mutex_unlock(sdw->link_res->shim_lock); 500 501 return ret; 502} 503 504static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 505{ 506 void __iomem *shim = sdw->link_res->shim; 507 unsigned int link_id = sdw->instance; 508 u16 wake_en, wake_sts; 509 510 mutex_lock(sdw->link_res->shim_lock); 511 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN); 512 513 if (wake_enable) { 514 /* Enable the wakeup */ 515 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id); 516 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 517 } else { 518 /* Disable the wake up interrupt */ 519 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id); 520 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 521 522 /* Clear wake status */ 523 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 524 wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id); 525 intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts); 526 } 527 mutex_unlock(sdw->link_res->shim_lock); 528} 529 530static int intel_link_power_down(struct sdw_intel *sdw) 531{ 532 u32 link_control, spa_mask, cpa_mask; 533 unsigned int link_id = sdw->instance; 534 void __iomem *shim = sdw->link_res->shim; 535 u32 *shim_mask = sdw->link_res->shim_mask; 536 int ret = 0; 537 538 mutex_lock(sdw->link_res->shim_lock); 539 540 if (!(*shim_mask & BIT(link_id))) 541 dev_err(sdw->cdns.dev, 542 "%s: Unbalanced power-up/down calls\n", __func__); 543 544 sdw->cdns.link_up = false; 545 546 intel_shim_master_ip_to_glue(sdw); 547 548 *shim_mask &= ~BIT(link_id); 549 550 if (!*shim_mask) { 551 552 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__); 553 554 /* Link power down sequence */ 555 link_control = intel_readl(shim, SDW_SHIM_LCTL); 556 557 /* only power-down enabled links */ 558 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask); 559 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 560 561 link_control &= spa_mask; 562 563 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 564 if (ret < 0) { 565 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__); 566 567 /* 568 * we leave the sdw->cdns.link_up flag as false since we've disabled 569 * the link at this point and cannot handle interrupts any longer. 570 */ 571 } 572 } 573 574 link_control = intel_readl(shim, SDW_SHIM_LCTL); 575 576 mutex_unlock(sdw->link_res->shim_lock); 577 578 return ret; 579} 580 581static void intel_shim_sync_arm(struct sdw_intel *sdw) 582{ 583 void __iomem *shim = sdw->link_res->shim; 584 u32 sync_reg; 585 586 mutex_lock(sdw->link_res->shim_lock); 587 588 /* update SYNC register */ 589 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 590 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance); 591 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 592 593 mutex_unlock(sdw->link_res->shim_lock); 594} 595 596static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw) 597{ 598 void __iomem *shim = sdw->link_res->shim; 599 u32 sync_reg; 600 int ret; 601 602 /* Read SYNC register */ 603 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 604 605 /* 606 * Set SyncGO bit to synchronously trigger a bank switch for 607 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all 608 * the Masters. 609 */ 610 sync_reg |= SDW_SHIM_SYNC_SYNCGO; 611 612 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 613 SDW_SHIM_SYNC_SYNCGO); 614 615 if (ret < 0) 616 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret); 617 618 return ret; 619} 620 621static int intel_shim_sync_go(struct sdw_intel *sdw) 622{ 623 int ret; 624 625 mutex_lock(sdw->link_res->shim_lock); 626 627 ret = intel_shim_sync_go_unlocked(sdw); 628 629 mutex_unlock(sdw->link_res->shim_lock); 630 631 return ret; 632} 633 634/* 635 * PDI routines 636 */ 637static void intel_pdi_init(struct sdw_intel *sdw, 638 struct sdw_cdns_stream_config *config) 639{ 640 void __iomem *shim = sdw->link_res->shim; 641 unsigned int link_id = sdw->instance; 642 int pcm_cap, pdm_cap; 643 644 /* PCM Stream Capability */ 645 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); 646 647 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap); 648 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap); 649 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap); 650 651 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 652 config->pcm_bd, config->pcm_in, config->pcm_out); 653 654 /* PDM Stream Capability */ 655 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 656 657 config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap); 658 config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap); 659 config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap); 660 661 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", 662 config->pdm_bd, config->pdm_in, config->pdm_out); 663} 664 665static int 666intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) 667{ 668 void __iomem *shim = sdw->link_res->shim; 669 unsigned int link_id = sdw->instance; 670 int count; 671 672 if (pcm) { 673 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); 674 675 /* 676 * WORKAROUND: on all existing Intel controllers, pdi 677 * number 2 reports channel count as 1 even though it 678 * supports 8 channels. Performing hardcoding for pdi 679 * number 2. 680 */ 681 if (pdi_num == 2) 682 count = 7; 683 684 } else { 685 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 686 count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count); 687 } 688 689 /* zero based values for channel count in register */ 690 count++; 691 692 return count; 693} 694 695static int intel_pdi_get_ch_update(struct sdw_intel *sdw, 696 struct sdw_cdns_pdi *pdi, 697 unsigned int num_pdi, 698 unsigned int *num_ch, bool pcm) 699{ 700 int i, ch_count = 0; 701 702 for (i = 0; i < num_pdi; i++) { 703 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); 704 ch_count += pdi->ch_count; 705 pdi++; 706 } 707 708 *num_ch = ch_count; 709 return 0; 710} 711 712static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, 713 struct sdw_cdns_streams *stream, bool pcm) 714{ 715 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 716 &stream->num_ch_bd, pcm); 717 718 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 719 &stream->num_ch_in, pcm); 720 721 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 722 &stream->num_ch_out, pcm); 723 724 return 0; 725} 726 727static int intel_pdi_ch_update(struct sdw_intel *sdw) 728{ 729 /* First update PCM streams followed by PDM streams */ 730 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); 731 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); 732 733 return 0; 734} 735 736static void 737intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 738{ 739 void __iomem *shim = sdw->link_res->shim; 740 unsigned int link_id = sdw->instance; 741 int pdi_conf = 0; 742 743 /* the Bulk and PCM streams are not contiguous */ 744 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 745 if (pdi->num >= 2) 746 pdi->intel_alh_id += 2; 747 748 /* 749 * Program stream parameters to stream SHIM register 750 * This is applicable for PCM stream only. 751 */ 752 if (pdi->type != SDW_STREAM_PCM) 753 return; 754 755 if (pdi->dir == SDW_DATA_DIR_RX) 756 pdi_conf |= SDW_SHIM_PCMSYCM_DIR; 757 else 758 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); 759 760 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM); 761 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN); 762 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN); 763 764 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); 765} 766 767static void 768intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 769{ 770 void __iomem *alh = sdw->link_res->alh; 771 unsigned int link_id = sdw->instance; 772 unsigned int conf; 773 774 /* the Bulk and PCM streams are not contiguous */ 775 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 776 if (pdi->num >= 2) 777 pdi->intel_alh_id += 2; 778 779 /* Program Stream config ALH register */ 780 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); 781 782 u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT); 783 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN); 784 785 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); 786} 787 788static int intel_params_stream(struct sdw_intel *sdw, 789 struct snd_pcm_substream *substream, 790 struct snd_soc_dai *dai, 791 struct snd_pcm_hw_params *hw_params, 792 int link_id, int alh_stream_id) 793{ 794 struct sdw_intel_link_res *res = sdw->link_res; 795 struct sdw_intel_stream_params_data params_data; 796 797 params_data.substream = substream; 798 params_data.dai = dai; 799 params_data.hw_params = hw_params; 800 params_data.link_id = link_id; 801 params_data.alh_stream_id = alh_stream_id; 802 803 if (res->ops && res->ops->params_stream && res->dev) 804 return res->ops->params_stream(res->dev, 805 ¶ms_data); 806 return -EIO; 807} 808 809static int intel_free_stream(struct sdw_intel *sdw, 810 struct snd_pcm_substream *substream, 811 struct snd_soc_dai *dai, 812 int link_id) 813{ 814 struct sdw_intel_link_res *res = sdw->link_res; 815 struct sdw_intel_stream_free_data free_data; 816 817 free_data.substream = substream; 818 free_data.dai = dai; 819 free_data.link_id = link_id; 820 821 if (res->ops && res->ops->free_stream && res->dev) 822 return res->ops->free_stream(res->dev, 823 &free_data); 824 825 return 0; 826} 827 828/* 829 * bank switch routines 830 */ 831 832static int intel_pre_bank_switch(struct sdw_bus *bus) 833{ 834 struct sdw_cdns *cdns = bus_to_cdns(bus); 835 struct sdw_intel *sdw = cdns_to_intel(cdns); 836 837 /* Write to register only for multi-link */ 838 if (!bus->multi_link) 839 return 0; 840 841 intel_shim_sync_arm(sdw); 842 843 return 0; 844} 845 846static int intel_post_bank_switch(struct sdw_bus *bus) 847{ 848 struct sdw_cdns *cdns = bus_to_cdns(bus); 849 struct sdw_intel *sdw = cdns_to_intel(cdns); 850 void __iomem *shim = sdw->link_res->shim; 851 int sync_reg, ret; 852 853 /* Write to register only for multi-link */ 854 if (!bus->multi_link) 855 return 0; 856 857 mutex_lock(sdw->link_res->shim_lock); 858 859 /* Read SYNC register */ 860 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 861 862 /* 863 * post_bank_switch() ops is called from the bus in loop for 864 * all the Masters in the steam with the expectation that 865 * we trigger the bankswitch for the only first Master in the list 866 * and do nothing for the other Masters 867 * 868 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. 869 */ 870 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) { 871 ret = 0; 872 goto unlock; 873 } 874 875 ret = intel_shim_sync_go_unlocked(sdw); 876unlock: 877 mutex_unlock(sdw->link_res->shim_lock); 878 879 if (ret < 0) 880 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); 881 882 return ret; 883} 884 885/* 886 * DAI routines 887 */ 888 889static int intel_startup(struct snd_pcm_substream *substream, 890 struct snd_soc_dai *dai) 891{ 892 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 893 int ret; 894 895 ret = pm_runtime_get_sync(cdns->dev); 896 if (ret < 0 && ret != -EACCES) { 897 dev_err_ratelimited(cdns->dev, 898 "pm_runtime_get_sync failed in %s, ret %d\n", 899 __func__, ret); 900 pm_runtime_put_noidle(cdns->dev); 901 return ret; 902 } 903 return 0; 904} 905 906static int intel_hw_params(struct snd_pcm_substream *substream, 907 struct snd_pcm_hw_params *params, 908 struct snd_soc_dai *dai) 909{ 910 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 911 struct sdw_intel *sdw = cdns_to_intel(cdns); 912 struct sdw_cdns_dma_data *dma; 913 struct sdw_cdns_pdi *pdi; 914 struct sdw_stream_config sconfig; 915 struct sdw_port_config *pconfig; 916 int ch, dir; 917 int ret; 918 bool pcm = true; 919 920 dma = snd_soc_dai_get_dma_data(dai, substream); 921 if (!dma) 922 return -EIO; 923 924 ch = params_channels(params); 925 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 926 dir = SDW_DATA_DIR_RX; 927 else 928 dir = SDW_DATA_DIR_TX; 929 930 if (dma->stream_type == SDW_STREAM_PDM) 931 pcm = false; 932 933 if (pcm) 934 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 935 else 936 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); 937 938 if (!pdi) { 939 ret = -EINVAL; 940 goto error; 941 } 942 943 /* do run-time configurations for SHIM, ALH and PDI/PORT */ 944 intel_pdi_shim_configure(sdw, pdi); 945 intel_pdi_alh_configure(sdw, pdi); 946 sdw_cdns_config_stream(cdns, ch, dir, pdi); 947 948 /* store pdi and hw_params, may be needed in prepare step */ 949 dma->suspended = false; 950 dma->pdi = pdi; 951 dma->hw_params = params; 952 953 /* Inform DSP about PDI stream number */ 954 ret = intel_params_stream(sdw, substream, dai, params, 955 sdw->instance, 956 pdi->intel_alh_id); 957 if (ret) 958 goto error; 959 960 sconfig.direction = dir; 961 sconfig.ch_count = ch; 962 sconfig.frame_rate = params_rate(params); 963 sconfig.type = dma->stream_type; 964 965 if (dma->stream_type == SDW_STREAM_PDM) { 966 sconfig.frame_rate *= 50; 967 sconfig.bps = 1; 968 } else { 969 sconfig.bps = snd_pcm_format_width(params_format(params)); 970 } 971 972 /* Port configuration */ 973 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL); 974 if (!pconfig) { 975 ret = -ENOMEM; 976 goto error; 977 } 978 979 pconfig->num = pdi->num; 980 pconfig->ch_mask = (1 << ch) - 1; 981 982 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 983 pconfig, 1, dma->stream); 984 if (ret) 985 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 986 987 kfree(pconfig); 988error: 989 return ret; 990} 991 992static int intel_prepare(struct snd_pcm_substream *substream, 993 struct snd_soc_dai *dai) 994{ 995 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 996 struct sdw_intel *sdw = cdns_to_intel(cdns); 997 struct sdw_cdns_dma_data *dma; 998 int ch, dir; 999 int ret = 0; 1000 1001 dma = snd_soc_dai_get_dma_data(dai, substream); 1002 if (!dma) { 1003 dev_err(dai->dev, "failed to get dma data in %s", 1004 __func__); 1005 return -EIO; 1006 } 1007 1008 if (dma->suspended) { 1009 dma->suspended = false; 1010 1011 /* 1012 * .prepare() is called after system resume, where we 1013 * need to reinitialize the SHIM/ALH/Cadence IP. 1014 * .prepare() is also called to deal with underflows, 1015 * but in those cases we cannot touch ALH/SHIM 1016 * registers 1017 */ 1018 1019 /* configure stream */ 1020 ch = params_channels(dma->hw_params); 1021 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1022 dir = SDW_DATA_DIR_RX; 1023 else 1024 dir = SDW_DATA_DIR_TX; 1025 1026 intel_pdi_shim_configure(sdw, dma->pdi); 1027 intel_pdi_alh_configure(sdw, dma->pdi); 1028 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi); 1029 1030 /* Inform DSP about PDI stream number */ 1031 ret = intel_params_stream(sdw, substream, dai, 1032 dma->hw_params, 1033 sdw->instance, 1034 dma->pdi->intel_alh_id); 1035 } 1036 1037 return ret; 1038} 1039 1040static int 1041intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 1042{ 1043 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 1044 struct sdw_intel *sdw = cdns_to_intel(cdns); 1045 struct sdw_cdns_dma_data *dma; 1046 int ret; 1047 1048 dma = snd_soc_dai_get_dma_data(dai, substream); 1049 if (!dma) 1050 return -EIO; 1051 1052 /* 1053 * The sdw stream state will transition to RELEASED when stream-> 1054 * master_list is empty. So the stream state will transition to 1055 * DEPREPARED for the first cpu-dai and to RELEASED for the last 1056 * cpu-dai. 1057 */ 1058 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); 1059 if (ret < 0) { 1060 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 1061 dma->stream->name, ret); 1062 return ret; 1063 } 1064 1065 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 1066 if (ret < 0) { 1067 dev_err(dai->dev, "intel_free_stream: failed %d", ret); 1068 return ret; 1069 } 1070 1071 dma->hw_params = NULL; 1072 dma->pdi = NULL; 1073 1074 return 0; 1075} 1076 1077static void intel_shutdown(struct snd_pcm_substream *substream, 1078 struct snd_soc_dai *dai) 1079{ 1080 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 1081 1082 pm_runtime_mark_last_busy(cdns->dev); 1083 pm_runtime_put_autosuspend(cdns->dev); 1084} 1085 1086static int intel_component_dais_suspend(struct snd_soc_component *component) 1087{ 1088 struct sdw_cdns_dma_data *dma; 1089 struct snd_soc_dai *dai; 1090 1091 for_each_component_dais(component, dai) { 1092 /* 1093 * we don't have a .suspend dai_ops, and we don't have access 1094 * to the substream, so let's mark both capture and playback 1095 * DMA contexts as suspended 1096 */ 1097 dma = dai->playback_dma_data; 1098 if (dma) 1099 dma->suspended = true; 1100 1101 dma = dai->capture_dma_data; 1102 if (dma) 1103 dma->suspended = true; 1104 } 1105 1106 return 0; 1107} 1108 1109static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 1110 void *stream, int direction) 1111{ 1112 return cdns_set_sdw_stream(dai, stream, true, direction); 1113} 1114 1115static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, 1116 void *stream, int direction) 1117{ 1118 return cdns_set_sdw_stream(dai, stream, false, direction); 1119} 1120 1121static void *intel_get_sdw_stream(struct snd_soc_dai *dai, 1122 int direction) 1123{ 1124 struct sdw_cdns_dma_data *dma; 1125 1126 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1127 dma = dai->playback_dma_data; 1128 else 1129 dma = dai->capture_dma_data; 1130 1131 if (!dma) 1132 return ERR_PTR(-EINVAL); 1133 1134 return dma->stream; 1135} 1136 1137static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 1138 .startup = intel_startup, 1139 .hw_params = intel_hw_params, 1140 .prepare = intel_prepare, 1141 .hw_free = intel_hw_free, 1142 .shutdown = intel_shutdown, 1143 .set_stream = intel_pcm_set_sdw_stream, 1144 .get_stream = intel_get_sdw_stream, 1145}; 1146 1147static const struct snd_soc_dai_ops intel_pdm_dai_ops = { 1148 .startup = intel_startup, 1149 .hw_params = intel_hw_params, 1150 .prepare = intel_prepare, 1151 .hw_free = intel_hw_free, 1152 .shutdown = intel_shutdown, 1153 .set_stream = intel_pdm_set_sdw_stream, 1154 .get_stream = intel_get_sdw_stream, 1155}; 1156 1157static const struct snd_soc_component_driver dai_component = { 1158 .name = "soundwire", 1159 .suspend = intel_component_dais_suspend 1160}; 1161 1162static int intel_create_dai(struct sdw_cdns *cdns, 1163 struct snd_soc_dai_driver *dais, 1164 enum intel_pdi_type type, 1165 u32 num, u32 off, u32 max_ch, bool pcm) 1166{ 1167 int i; 1168 1169 if (num == 0) 1170 return 0; 1171 1172 /* TODO: Read supported rates/formats from hardware */ 1173 for (i = off; i < (off + num); i++) { 1174 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 1175 "SDW%d Pin%d", 1176 cdns->instance, i); 1177 if (!dais[i].name) 1178 return -ENOMEM; 1179 1180 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 1181 dais[i].playback.channels_min = 1; 1182 dais[i].playback.channels_max = max_ch; 1183 dais[i].playback.rates = SNDRV_PCM_RATE_48000; 1184 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1185 } 1186 1187 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 1188 dais[i].capture.channels_min = 1; 1189 dais[i].capture.channels_max = max_ch; 1190 dais[i].capture.rates = SNDRV_PCM_RATE_48000; 1191 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1192 } 1193 1194 if (pcm) 1195 dais[i].ops = &intel_pcm_dai_ops; 1196 else 1197 dais[i].ops = &intel_pdm_dai_ops; 1198 } 1199 1200 return 0; 1201} 1202 1203static int intel_register_dai(struct sdw_intel *sdw) 1204{ 1205 struct sdw_cdns *cdns = &sdw->cdns; 1206 struct sdw_cdns_streams *stream; 1207 struct snd_soc_dai_driver *dais; 1208 int num_dai, ret, off = 0; 1209 1210 /* DAIs are created based on total number of PDIs supported */ 1211 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; 1212 1213 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 1214 if (!dais) 1215 return -ENOMEM; 1216 1217 /* Create PCM DAIs */ 1218 stream = &cdns->pcm; 1219 1220 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 1221 off, stream->num_ch_in, true); 1222 if (ret) 1223 return ret; 1224 1225 off += cdns->pcm.num_in; 1226 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 1227 off, stream->num_ch_out, true); 1228 if (ret) 1229 return ret; 1230 1231 off += cdns->pcm.num_out; 1232 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 1233 off, stream->num_ch_bd, true); 1234 if (ret) 1235 return ret; 1236 1237 /* Create PDM DAIs */ 1238 stream = &cdns->pdm; 1239 off += cdns->pcm.num_bd; 1240 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, 1241 off, stream->num_ch_in, false); 1242 if (ret) 1243 return ret; 1244 1245 off += cdns->pdm.num_in; 1246 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, 1247 off, stream->num_ch_out, false); 1248 if (ret) 1249 return ret; 1250 1251 off += cdns->pdm.num_out; 1252 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, 1253 off, stream->num_ch_bd, false); 1254 if (ret) 1255 return ret; 1256 1257 return snd_soc_register_component(cdns->dev, &dai_component, 1258 dais, num_dai); 1259} 1260 1261static int sdw_master_read_intel_prop(struct sdw_bus *bus) 1262{ 1263 struct sdw_master_prop *prop = &bus->prop; 1264 struct fwnode_handle *link; 1265 char name[32]; 1266 u32 quirk_mask; 1267 1268 /* Find master handle */ 1269 snprintf(name, sizeof(name), 1270 "mipi-sdw-link-%d-subproperties", bus->link_id); 1271 1272 link = device_get_named_child_node(bus->dev, name); 1273 if (!link) { 1274 dev_err(bus->dev, "Master node %s not found\n", name); 1275 return -EIO; 1276 } 1277 1278 fwnode_property_read_u32(link, 1279 "intel-sdw-ip-clock", 1280 &prop->mclk_freq); 1281 1282 /* the values reported by BIOS are the 2x clock, not the bus clock */ 1283 prop->mclk_freq /= 2; 1284 1285 fwnode_property_read_u32(link, 1286 "intel-quirk-mask", 1287 &quirk_mask); 1288 1289 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) 1290 prop->hw_disabled = true; 1291 1292 return 0; 1293} 1294 1295static int intel_prop_read(struct sdw_bus *bus) 1296{ 1297 /* Initialize with default handler to read all DisCo properties */ 1298 sdw_master_read_prop(bus); 1299 1300 /* read Intel-specific properties */ 1301 sdw_master_read_intel_prop(bus); 1302 1303 return 0; 1304} 1305 1306static struct sdw_master_ops sdw_intel_ops = { 1307 .read_prop = sdw_master_read_prop, 1308 .xfer_msg = cdns_xfer_msg, 1309 .xfer_msg_defer = cdns_xfer_msg_defer, 1310 .reset_page_addr = cdns_reset_page_addr, 1311 .set_bus_conf = cdns_bus_conf, 1312 .pre_bank_switch = intel_pre_bank_switch, 1313 .post_bank_switch = intel_post_bank_switch, 1314}; 1315 1316static int intel_init(struct sdw_intel *sdw) 1317{ 1318 bool clock_stop; 1319 1320 /* Initialize shim and controller */ 1321 intel_link_power_up(sdw); 1322 1323 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); 1324 1325 intel_shim_init(sdw, clock_stop); 1326 1327 return 0; 1328} 1329 1330/* 1331 * probe and init 1332 */ 1333static int intel_master_probe(struct platform_device *pdev) 1334{ 1335 struct device *dev = &pdev->dev; 1336 struct sdw_intel *sdw; 1337 struct sdw_cdns *cdns; 1338 struct sdw_bus *bus; 1339 int ret; 1340 1341 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL); 1342 if (!sdw) 1343 return -ENOMEM; 1344 1345 cdns = &sdw->cdns; 1346 bus = &cdns->bus; 1347 1348 sdw->instance = pdev->id; 1349 sdw->link_res = dev_get_platdata(dev); 1350 cdns->dev = dev; 1351 cdns->registers = sdw->link_res->registers; 1352 cdns->instance = sdw->instance; 1353 cdns->msg_count = 0; 1354 1355 bus->link_id = pdev->id; 1356 1357 sdw_cdns_probe(cdns); 1358 1359 /* Set property read ops */ 1360 sdw_intel_ops.read_prop = intel_prop_read; 1361 bus->ops = &sdw_intel_ops; 1362 1363 /* set driver data, accessed by snd_soc_dai_get_drvdata() */ 1364 dev_set_drvdata(dev, cdns); 1365 1366 /* use generic bandwidth allocation algorithm */ 1367 sdw->cdns.bus.compute_params = sdw_compute_params; 1368 1369 ret = sdw_bus_master_add(bus, dev, dev->fwnode); 1370 if (ret) { 1371 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret); 1372 return ret; 1373 } 1374 1375 if (bus->prop.hw_disabled) 1376 dev_info(dev, 1377 "SoundWire master %d is disabled, will be ignored\n", 1378 bus->link_id); 1379 /* 1380 * Ignore BIOS err_threshold, it's a really bad idea when dealing 1381 * with multiple hardware synchronized links 1382 */ 1383 bus->prop.err_threshold = 0; 1384 1385 return 0; 1386} 1387 1388int intel_master_startup(struct platform_device *pdev) 1389{ 1390 struct sdw_cdns_stream_config config; 1391 struct device *dev = &pdev->dev; 1392 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1393 struct sdw_intel *sdw = cdns_to_intel(cdns); 1394 struct sdw_bus *bus = &cdns->bus; 1395 int link_flags; 1396 bool multi_link; 1397 u32 clock_stop_quirks; 1398 int ret; 1399 1400 if (bus->prop.hw_disabled) { 1401 dev_info(dev, 1402 "SoundWire master %d is disabled, ignoring\n", 1403 sdw->instance); 1404 return 0; 1405 } 1406 1407 link_flags = md_flags >> (bus->link_id * 8); 1408 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1409 if (!multi_link) { 1410 dev_dbg(dev, "Multi-link is disabled\n"); 1411 bus->multi_link = false; 1412 } else { 1413 /* 1414 * hardware-based synchronization is required regardless 1415 * of the number of segments used by a stream: SSP-based 1416 * synchronization is gated by gsync when the multi-master 1417 * mode is set. 1418 */ 1419 bus->multi_link = true; 1420 bus->hw_sync_min_links = 1; 1421 } 1422 1423 /* Initialize shim, controller */ 1424 ret = intel_init(sdw); 1425 if (ret) 1426 goto err_init; 1427 1428 /* Read the PDI config and initialize cadence PDI */ 1429 intel_pdi_init(sdw, &config); 1430 ret = sdw_cdns_pdi_init(cdns, config); 1431 if (ret) 1432 goto err_init; 1433 1434 intel_pdi_ch_update(sdw); 1435 1436 ret = sdw_cdns_enable_interrupt(cdns, true); 1437 if (ret < 0) { 1438 dev_err(dev, "cannot enable interrupts\n"); 1439 goto err_init; 1440 } 1441 1442 /* 1443 * follow recommended programming flows to avoid timeouts when 1444 * gsync is enabled 1445 */ 1446 if (multi_link) 1447 intel_shim_sync_arm(sdw); 1448 1449 ret = sdw_cdns_init(cdns); 1450 if (ret < 0) { 1451 dev_err(dev, "unable to initialize Cadence IP\n"); 1452 goto err_interrupt; 1453 } 1454 1455 ret = sdw_cdns_exit_reset(cdns); 1456 if (ret < 0) { 1457 dev_err(dev, "unable to exit bus reset sequence\n"); 1458 goto err_interrupt; 1459 } 1460 1461 if (multi_link) { 1462 ret = intel_shim_sync_go(sdw); 1463 if (ret < 0) { 1464 dev_err(dev, "sync go failed: %d\n", ret); 1465 goto err_interrupt; 1466 } 1467 } 1468 1469 /* Register DAIs */ 1470 ret = intel_register_dai(sdw); 1471 if (ret) { 1472 dev_err(dev, "DAI registration failed: %d\n", ret); 1473 goto err_interrupt; 1474 } 1475 1476 intel_debugfs_init(sdw); 1477 1478 /* Enable runtime PM */ 1479 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) { 1480 pm_runtime_set_autosuspend_delay(dev, 1481 INTEL_MASTER_SUSPEND_DELAY_MS); 1482 pm_runtime_use_autosuspend(dev); 1483 pm_runtime_mark_last_busy(dev); 1484 1485 pm_runtime_set_active(dev); 1486 pm_runtime_enable(dev); 1487 } 1488 1489 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1490 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) { 1491 /* 1492 * To keep the clock running we need to prevent 1493 * pm_runtime suspend from happening by increasing the 1494 * reference count. 1495 * This quirk is specified by the parent PCI device in 1496 * case of specific latency requirements. It will have 1497 * no effect if pm_runtime is disabled by the user via 1498 * a module parameter for testing purposes. 1499 */ 1500 pm_runtime_get_noresume(dev); 1501 } 1502 1503 /* 1504 * The runtime PM status of Slave devices is "Unsupported" 1505 * until they report as ATTACHED. If they don't, e.g. because 1506 * there are no Slave devices populated or if the power-on is 1507 * delayed or dependent on a power switch, the Master will 1508 * remain active and prevent its parent from suspending. 1509 * 1510 * Conditionally force the pm_runtime core to re-evaluate the 1511 * Master status in the absence of any Slave activity. A quirk 1512 * is provided to e.g. deal with Slaves that may be powered on 1513 * with a delay. A more complete solution would require the 1514 * definition of Master properties. 1515 */ 1516 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) 1517 pm_runtime_idle(dev); 1518 1519 return 0; 1520 1521err_interrupt: 1522 sdw_cdns_enable_interrupt(cdns, false); 1523err_init: 1524 return ret; 1525} 1526 1527static int intel_master_remove(struct platform_device *pdev) 1528{ 1529 struct device *dev = &pdev->dev; 1530 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1531 struct sdw_intel *sdw = cdns_to_intel(cdns); 1532 struct sdw_bus *bus = &cdns->bus; 1533 1534 /* 1535 * Since pm_runtime is already disabled, we don't decrease 1536 * the refcount when the clock_stop_quirk is 1537 * SDW_INTEL_CLK_STOP_NOT_ALLOWED 1538 */ 1539 if (!bus->prop.hw_disabled) { 1540 intel_debugfs_exit(sdw); 1541 sdw_cdns_enable_interrupt(cdns, false); 1542 snd_soc_unregister_component(dev); 1543 } 1544 sdw_bus_master_delete(bus); 1545 1546 return 0; 1547} 1548 1549int intel_master_process_wakeen_event(struct platform_device *pdev) 1550{ 1551 struct device *dev = &pdev->dev; 1552 struct sdw_intel *sdw; 1553 struct sdw_bus *bus; 1554 void __iomem *shim; 1555 u16 wake_sts; 1556 1557 sdw = platform_get_drvdata(pdev); 1558 bus = &sdw->cdns.bus; 1559 1560 if (bus->prop.hw_disabled) { 1561 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id); 1562 return 0; 1563 } 1564 1565 shim = sdw->link_res->shim; 1566 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 1567 1568 if (!(wake_sts & BIT(sdw->instance))) 1569 return 0; 1570 1571 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */ 1572 intel_shim_wake(sdw, false); 1573 1574 /* 1575 * resume the Master, which will generate a bus reset and result in 1576 * Slaves re-attaching and be re-enumerated. The SoundWire physical 1577 * device which generated the wake will trigger an interrupt, which 1578 * will in turn cause the corresponding Linux Slave device to be 1579 * resumed and the Slave codec driver to check the status. 1580 */ 1581 pm_request_resume(dev); 1582 1583 return 0; 1584} 1585 1586/* 1587 * PM calls 1588 */ 1589 1590#ifdef CONFIG_PM 1591 1592static int __maybe_unused intel_suspend(struct device *dev) 1593{ 1594 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1595 struct sdw_intel *sdw = cdns_to_intel(cdns); 1596 struct sdw_bus *bus = &cdns->bus; 1597 u32 clock_stop_quirks; 1598 int ret; 1599 1600 if (bus->prop.hw_disabled) { 1601 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1602 bus->link_id); 1603 return 0; 1604 } 1605 1606 if (pm_runtime_suspended(dev)) { 1607 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__); 1608 1609 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1610 1611 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || 1612 !clock_stop_quirks) && 1613 !pm_runtime_suspended(dev->parent)) { 1614 1615 /* 1616 * if we've enabled clock stop, and the parent 1617 * is still active, disable shim wake. The 1618 * SHIM registers are not accessible if the 1619 * parent is already pm_runtime suspended so 1620 * it's too late to change that configuration 1621 */ 1622 1623 intel_shim_wake(sdw, false); 1624 } 1625 1626 return 0; 1627 } 1628 1629 ret = sdw_cdns_enable_interrupt(cdns, false); 1630 if (ret < 0) { 1631 dev_err(dev, "cannot disable interrupts on suspend\n"); 1632 return ret; 1633 } 1634 1635 ret = intel_link_power_down(sdw); 1636 if (ret) { 1637 dev_err(dev, "Link power down failed: %d", ret); 1638 return ret; 1639 } 1640 1641 intel_shim_wake(sdw, false); 1642 1643 return 0; 1644} 1645 1646static int intel_suspend_runtime(struct device *dev) 1647{ 1648 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1649 struct sdw_intel *sdw = cdns_to_intel(cdns); 1650 struct sdw_bus *bus = &cdns->bus; 1651 u32 clock_stop_quirks; 1652 int ret; 1653 1654 if (bus->prop.hw_disabled) { 1655 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1656 bus->link_id); 1657 return 0; 1658 } 1659 1660 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1661 1662 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1663 1664 ret = sdw_cdns_enable_interrupt(cdns, false); 1665 if (ret < 0) { 1666 dev_err(dev, "cannot disable interrupts on suspend\n"); 1667 return ret; 1668 } 1669 1670 ret = intel_link_power_down(sdw); 1671 if (ret) { 1672 dev_err(dev, "Link power down failed: %d", ret); 1673 return ret; 1674 } 1675 1676 intel_shim_wake(sdw, false); 1677 1678 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || 1679 !clock_stop_quirks) { 1680 ret = sdw_cdns_clock_stop(cdns, true); 1681 if (ret < 0) { 1682 dev_err(dev, "cannot enable clock stop on suspend\n"); 1683 return ret; 1684 } 1685 1686 ret = sdw_cdns_enable_interrupt(cdns, false); 1687 if (ret < 0) { 1688 dev_err(dev, "cannot disable interrupts on suspend\n"); 1689 return ret; 1690 } 1691 1692 ret = intel_link_power_down(sdw); 1693 if (ret) { 1694 dev_err(dev, "Link power down failed: %d", ret); 1695 return ret; 1696 } 1697 1698 intel_shim_wake(sdw, true); 1699 } else { 1700 dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1701 __func__, clock_stop_quirks); 1702 ret = -EINVAL; 1703 } 1704 1705 return ret; 1706} 1707 1708static int __maybe_unused intel_resume(struct device *dev) 1709{ 1710 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1711 struct sdw_intel *sdw = cdns_to_intel(cdns); 1712 struct sdw_bus *bus = &cdns->bus; 1713 int link_flags; 1714 bool multi_link; 1715 int ret; 1716 1717 if (bus->prop.hw_disabled) { 1718 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1719 bus->link_id); 1720 return 0; 1721 } 1722 1723 link_flags = md_flags >> (bus->link_id * 8); 1724 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1725 1726 if (pm_runtime_suspended(dev)) { 1727 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__); 1728 1729 /* follow required sequence from runtime_pm.rst */ 1730 pm_runtime_disable(dev); 1731 pm_runtime_set_active(dev); 1732 pm_runtime_mark_last_busy(dev); 1733 pm_runtime_enable(dev); 1734 1735 link_flags = md_flags >> (bus->link_id * 8); 1736 1737 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) 1738 pm_runtime_idle(dev); 1739 } 1740 1741 ret = intel_init(sdw); 1742 if (ret) { 1743 dev_err(dev, "%s failed: %d", __func__, ret); 1744 return ret; 1745 } 1746 1747 /* 1748 * make sure all Slaves are tagged as UNATTACHED and provide 1749 * reason for reinitialization 1750 */ 1751 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1752 1753 ret = sdw_cdns_enable_interrupt(cdns, true); 1754 if (ret < 0) { 1755 dev_err(dev, "cannot enable interrupts during resume\n"); 1756 return ret; 1757 } 1758 1759 /* 1760 * follow recommended programming flows to avoid timeouts when 1761 * gsync is enabled 1762 */ 1763 if (multi_link) 1764 intel_shim_sync_arm(sdw); 1765 1766 ret = sdw_cdns_init(&sdw->cdns); 1767 if (ret < 0) { 1768 dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1769 return ret; 1770 } 1771 1772 ret = sdw_cdns_exit_reset(cdns); 1773 if (ret < 0) { 1774 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1775 return ret; 1776 } 1777 1778 if (multi_link) { 1779 ret = intel_shim_sync_go(sdw); 1780 if (ret < 0) { 1781 dev_err(dev, "sync go failed during resume\n"); 1782 return ret; 1783 } 1784 } 1785 1786 /* 1787 * after system resume, the pm_runtime suspend() may kick in 1788 * during the enumeration, before any children device force the 1789 * master device to remain active. Using pm_runtime_get() 1790 * routines is not really possible, since it'd prevent the 1791 * master from suspending. 1792 * A reasonable compromise is to update the pm_runtime 1793 * counters and delay the pm_runtime suspend by several 1794 * seconds, by when all enumeration should be complete. 1795 */ 1796 pm_runtime_mark_last_busy(dev); 1797 1798 return ret; 1799} 1800 1801static int intel_resume_runtime(struct device *dev) 1802{ 1803 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1804 struct sdw_intel *sdw = cdns_to_intel(cdns); 1805 struct sdw_bus *bus = &cdns->bus; 1806 u32 clock_stop_quirks; 1807 bool clock_stop0; 1808 int link_flags; 1809 bool multi_link; 1810 int status; 1811 int ret; 1812 1813 if (bus->prop.hw_disabled) { 1814 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1815 bus->link_id); 1816 return 0; 1817 } 1818 1819 link_flags = md_flags >> (bus->link_id * 8); 1820 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1821 1822 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1823 1824 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1825 ret = intel_init(sdw); 1826 if (ret) { 1827 dev_err(dev, "%s failed: %d", __func__, ret); 1828 return ret; 1829 } 1830 1831 /* 1832 * make sure all Slaves are tagged as UNATTACHED and provide 1833 * reason for reinitialization 1834 */ 1835 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1836 1837 ret = sdw_cdns_enable_interrupt(cdns, true); 1838 if (ret < 0) { 1839 dev_err(dev, "cannot enable interrupts during resume\n"); 1840 return ret; 1841 } 1842 1843 /* 1844 * follow recommended programming flows to avoid 1845 * timeouts when gsync is enabled 1846 */ 1847 if (multi_link) 1848 intel_shim_sync_arm(sdw); 1849 1850 ret = sdw_cdns_init(&sdw->cdns); 1851 if (ret < 0) { 1852 dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1853 return ret; 1854 } 1855 1856 ret = sdw_cdns_exit_reset(cdns); 1857 if (ret < 0) { 1858 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1859 return ret; 1860 } 1861 1862 if (multi_link) { 1863 ret = intel_shim_sync_go(sdw); 1864 if (ret < 0) { 1865 dev_err(dev, "sync go failed during resume\n"); 1866 return ret; 1867 } 1868 } 1869 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) { 1870 ret = intel_init(sdw); 1871 if (ret) { 1872 dev_err(dev, "%s failed: %d", __func__, ret); 1873 return ret; 1874 } 1875 1876 /* 1877 * An exception condition occurs for the CLK_STOP_BUS_RESET 1878 * case if one or more masters remain active. In this condition, 1879 * all the masters are powered on for they are in the same power 1880 * domain. Master can preserve its context for clock stop0, so 1881 * there is no need to clear slave status and reset bus. 1882 */ 1883 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1884 1885 if (!clock_stop0) { 1886 1887 /* 1888 * make sure all Slaves are tagged as UNATTACHED and 1889 * provide reason for reinitialization 1890 */ 1891 1892 status = SDW_UNATTACH_REQUEST_MASTER_RESET; 1893 sdw_clear_slave_status(bus, status); 1894 1895 ret = sdw_cdns_enable_interrupt(cdns, true); 1896 if (ret < 0) { 1897 dev_err(dev, "cannot enable interrupts during resume\n"); 1898 return ret; 1899 } 1900 1901 /* 1902 * follow recommended programming flows to avoid 1903 * timeouts when gsync is enabled 1904 */ 1905 if (multi_link) 1906 intel_shim_sync_arm(sdw); 1907 1908 /* 1909 * Re-initialize the IP since it was powered-off 1910 */ 1911 sdw_cdns_init(&sdw->cdns); 1912 1913 } else { 1914 ret = sdw_cdns_enable_interrupt(cdns, true); 1915 if (ret < 0) { 1916 dev_err(dev, "cannot enable interrupts during resume\n"); 1917 return ret; 1918 } 1919 } 1920 1921 ret = sdw_cdns_clock_restart(cdns, !clock_stop0); 1922 if (ret < 0) { 1923 dev_err(dev, "unable to restart clock during resume\n"); 1924 return ret; 1925 } 1926 1927 if (!clock_stop0) { 1928 ret = sdw_cdns_exit_reset(cdns); 1929 if (ret < 0) { 1930 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1931 return ret; 1932 } 1933 1934 if (multi_link) { 1935 ret = intel_shim_sync_go(sdw); 1936 if (ret < 0) { 1937 dev_err(sdw->cdns.dev, "sync go failed during resume\n"); 1938 return ret; 1939 } 1940 } 1941 } 1942 } else if (!clock_stop_quirks) { 1943 1944 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1945 if (!clock_stop0) 1946 dev_err(dev, "%s invalid configuration, clock was not stopped", __func__); 1947 1948 ret = intel_init(sdw); 1949 if (ret) { 1950 dev_err(dev, "%s failed: %d", __func__, ret); 1951 return ret; 1952 } 1953 1954 ret = sdw_cdns_enable_interrupt(cdns, true); 1955 if (ret < 0) { 1956 dev_err(dev, "cannot enable interrupts during resume\n"); 1957 return ret; 1958 } 1959 1960 ret = sdw_cdns_clock_restart(cdns, false); 1961 if (ret < 0) { 1962 dev_err(dev, "unable to resume master during resume\n"); 1963 return ret; 1964 } 1965 } else { 1966 dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1967 __func__, clock_stop_quirks); 1968 ret = -EINVAL; 1969 } 1970 1971 return ret; 1972} 1973 1974#endif 1975 1976static const struct dev_pm_ops intel_pm = { 1977 SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume) 1978 SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL) 1979}; 1980 1981static struct platform_driver sdw_intel_drv = { 1982 .probe = intel_master_probe, 1983 .remove = intel_master_remove, 1984 .driver = { 1985 .name = "intel-sdw", 1986 .pm = &intel_pm, 1987 } 1988}; 1989 1990module_platform_driver(sdw_intel_drv); 1991 1992MODULE_LICENSE("Dual BSD/GPL"); 1993MODULE_ALIAS("platform:intel-sdw"); 1994MODULE_DESCRIPTION("Intel Soundwire Master Driver"); 1995