1/*
2 * Allwinner SoCs SRAM Controller Driver
3 *
4 * Copyright (C) 2015 Maxime Ripard
5 *
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/debugfs.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21
22#include <linux/soc/sunxi/sunxi_sram.h>
23
24struct sunxi_sram_func {
25	char	*func;
26	u8	val;
27	u32	reg_val;
28};
29
30struct sunxi_sram_data {
31	char			*name;
32	u8			reg;
33	u8			offset;
34	u8			width;
35	struct sunxi_sram_func	*func;
36	struct list_head	list;
37};
38
39struct sunxi_sram_desc {
40	struct sunxi_sram_data	data;
41	bool			claimed;
42};
43
44#define SUNXI_SRAM_MAP(_reg_val, _val, _func)			\
45	{							\
46		.func = _func,					\
47		.val = _val,					\
48		.reg_val = _reg_val,				\
49	}
50
51#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...)		\
52	{							\
53		.name = _name,					\
54		.reg = _reg,					\
55		.offset = _off,					\
56		.width = _width,				\
57		.func = (struct sunxi_sram_func[]){		\
58			__VA_ARGS__, { } },			\
59	}
60
61static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
62	.data	= SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
63				  SUNXI_SRAM_MAP(0, 0, "cpu"),
64				  SUNXI_SRAM_MAP(1, 1, "emac")),
65};
66
67static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
68	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
69				  SUNXI_SRAM_MAP(0, 0, "cpu"),
70				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
71};
72
73static struct sunxi_sram_desc sun4i_a10_sram_d = {
74	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
75				  SUNXI_SRAM_MAP(0, 0, "cpu"),
76				  SUNXI_SRAM_MAP(1, 1, "usb-otg")),
77};
78
79static struct sunxi_sram_desc sun50i_a64_sram_c = {
80	.data	= SUNXI_SRAM_DATA("C", 0x4, 24, 1,
81				  SUNXI_SRAM_MAP(1, 0, "cpu"),
82				  SUNXI_SRAM_MAP(0, 1, "de2")),
83};
84
85static const struct of_device_id sunxi_sram_dt_ids[] = {
86	{
87		.compatible	= "allwinner,sun4i-a10-sram-a3-a4",
88		.data		= &sun4i_a10_sram_a3_a4.data,
89	},
90	{
91		.compatible	= "allwinner,sun4i-a10-sram-c1",
92		.data		= &sun4i_a10_sram_c1.data,
93	},
94	{
95		.compatible	= "allwinner,sun4i-a10-sram-d",
96		.data		= &sun4i_a10_sram_d.data,
97	},
98	{
99		.compatible	= "allwinner,sun50i-a64-sram-c",
100		.data		= &sun50i_a64_sram_c.data,
101	},
102	{}
103};
104
105static struct device *sram_dev;
106static LIST_HEAD(claimed_sram);
107static DEFINE_SPINLOCK(sram_lock);
108static void __iomem *base;
109
110static int sunxi_sram_show(struct seq_file *s, void *data)
111{
112	struct device_node *sram_node, *section_node;
113	const struct sunxi_sram_data *sram_data;
114	const struct of_device_id *match;
115	struct sunxi_sram_func *func;
116	const __be32 *sram_addr_p, *section_addr_p;
117	u32 val;
118
119	seq_puts(s, "Allwinner sunXi SRAM\n");
120	seq_puts(s, "--------------------\n\n");
121
122	for_each_child_of_node(sram_dev->of_node, sram_node) {
123		sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
124
125		seq_printf(s, "sram@%08x\n",
126			   be32_to_cpu(*sram_addr_p));
127
128		for_each_child_of_node(sram_node, section_node) {
129			match = of_match_node(sunxi_sram_dt_ids, section_node);
130			if (!match)
131				continue;
132			sram_data = match->data;
133
134			section_addr_p = of_get_address(section_node, 0,
135							NULL, NULL);
136
137			seq_printf(s, "\tsection@%04x\t(%s)\n",
138				   be32_to_cpu(*section_addr_p),
139				   sram_data->name);
140
141			val = readl(base + sram_data->reg);
142			val >>= sram_data->offset;
143			val &= GENMASK(sram_data->width - 1, 0);
144
145			for (func = sram_data->func; func->func; func++) {
146				seq_printf(s, "\t\t%s%c\n", func->func,
147					   func->reg_val == val ?
148					   '*' : ' ');
149			}
150		}
151
152		seq_puts(s, "\n");
153	}
154
155	return 0;
156}
157
158DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
159
160static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
161{
162	return container_of(data, struct sunxi_sram_desc, data);
163}
164
165static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
166							 unsigned int *reg_value)
167{
168	const struct of_device_id *match;
169	const struct sunxi_sram_data *data;
170	struct sunxi_sram_func *func;
171	struct of_phandle_args args;
172	u8 val;
173	int ret;
174
175	ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
176					       &args);
177	if (ret)
178		return ERR_PTR(ret);
179
180	if (!of_device_is_available(args.np)) {
181		ret = -EBUSY;
182		goto err;
183	}
184
185	val = args.args[0];
186
187	match = of_match_node(sunxi_sram_dt_ids, args.np);
188	if (!match) {
189		ret = -EINVAL;
190		goto err;
191	}
192
193	data = match->data;
194	if (!data) {
195		ret = -EINVAL;
196		goto err;
197	}
198
199	for (func = data->func; func->func; func++) {
200		if (val == func->val) {
201			if (reg_value)
202				*reg_value = func->reg_val;
203
204			break;
205		}
206	}
207
208	if (!func->func) {
209		ret = -EINVAL;
210		goto err;
211	}
212
213	of_node_put(args.np);
214	return match->data;
215
216err:
217	of_node_put(args.np);
218	return ERR_PTR(ret);
219}
220
221int sunxi_sram_claim(struct device *dev)
222{
223	const struct sunxi_sram_data *sram_data;
224	struct sunxi_sram_desc *sram_desc;
225	unsigned int device;
226	u32 val, mask;
227
228	if (IS_ERR(base))
229		return PTR_ERR(base);
230
231	if (!base)
232		return -EPROBE_DEFER;
233
234	if (!dev || !dev->of_node)
235		return -EINVAL;
236
237	sram_data = sunxi_sram_of_parse(dev->of_node, &device);
238	if (IS_ERR(sram_data))
239		return PTR_ERR(sram_data);
240
241	sram_desc = to_sram_desc(sram_data);
242
243	spin_lock(&sram_lock);
244
245	if (sram_desc->claimed) {
246		spin_unlock(&sram_lock);
247		return -EBUSY;
248	}
249
250	mask = GENMASK(sram_data->offset + sram_data->width - 1,
251		       sram_data->offset);
252	val = readl(base + sram_data->reg);
253	val &= ~mask;
254	writel(val | ((device << sram_data->offset) & mask),
255	       base + sram_data->reg);
256
257	sram_desc->claimed = true;
258	spin_unlock(&sram_lock);
259
260	return 0;
261}
262EXPORT_SYMBOL(sunxi_sram_claim);
263
264int sunxi_sram_release(struct device *dev)
265{
266	const struct sunxi_sram_data *sram_data;
267	struct sunxi_sram_desc *sram_desc;
268
269	if (!dev || !dev->of_node)
270		return -EINVAL;
271
272	sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
273	if (IS_ERR(sram_data))
274		return -EINVAL;
275
276	sram_desc = to_sram_desc(sram_data);
277
278	spin_lock(&sram_lock);
279	sram_desc->claimed = false;
280	spin_unlock(&sram_lock);
281
282	return 0;
283}
284EXPORT_SYMBOL(sunxi_sram_release);
285
286struct sunxi_sramc_variant {
287	bool has_emac_clock;
288};
289
290static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
291	/* Nothing special */
292};
293
294static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
295	.has_emac_clock = true,
296};
297
298static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
299	.has_emac_clock = true,
300};
301
302#define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
303static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
304					     unsigned int reg)
305{
306	if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
307		return true;
308	return false;
309}
310
311static struct regmap_config sunxi_sram_emac_clock_regmap = {
312	.reg_bits       = 32,
313	.val_bits       = 32,
314	.reg_stride     = 4,
315	/* last defined register */
316	.max_register   = SUNXI_SRAM_EMAC_CLOCK_REG,
317	/* other devices have no business accessing other registers */
318	.readable_reg	= sunxi_sram_regmap_accessible_reg,
319	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
320};
321
322static int __init sunxi_sram_probe(struct platform_device *pdev)
323{
324	struct regmap *emac_clock;
325	const struct sunxi_sramc_variant *variant;
326	struct device *dev = &pdev->dev;
327
328	sram_dev = &pdev->dev;
329
330	variant = of_device_get_match_data(&pdev->dev);
331	if (!variant)
332		return -EINVAL;
333
334	base = devm_platform_ioremap_resource(pdev, 0);
335	if (IS_ERR(base))
336		return PTR_ERR(base);
337
338	if (variant->has_emac_clock) {
339		emac_clock = devm_regmap_init_mmio(&pdev->dev, base,
340						   &sunxi_sram_emac_clock_regmap);
341
342		if (IS_ERR(emac_clock))
343			return PTR_ERR(emac_clock);
344	}
345
346	of_platform_populate(dev->of_node, NULL, NULL, dev);
347
348	debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops);
349
350	return 0;
351}
352
353static const struct of_device_id sunxi_sram_dt_match[] = {
354	{
355		.compatible = "allwinner,sun4i-a10-sram-controller",
356		.data = &sun4i_a10_sramc_variant,
357	},
358	{
359		.compatible = "allwinner,sun4i-a10-system-control",
360		.data = &sun4i_a10_sramc_variant,
361	},
362	{
363		.compatible = "allwinner,sun5i-a13-system-control",
364		.data = &sun4i_a10_sramc_variant,
365	},
366	{
367		.compatible = "allwinner,sun8i-a23-system-control",
368		.data = &sun4i_a10_sramc_variant,
369	},
370	{
371		.compatible = "allwinner,sun8i-h3-system-control",
372		.data = &sun8i_h3_sramc_variant,
373	},
374	{
375		.compatible = "allwinner,sun50i-a64-sram-controller",
376		.data = &sun50i_a64_sramc_variant,
377	},
378	{
379		.compatible = "allwinner,sun50i-a64-system-control",
380		.data = &sun50i_a64_sramc_variant,
381	},
382	{
383		.compatible = "allwinner,sun50i-h5-system-control",
384		.data = &sun50i_a64_sramc_variant,
385	},
386	{ },
387};
388MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
389
390static struct platform_driver sunxi_sram_driver = {
391	.driver = {
392		.name		= "sunxi-sram",
393		.of_match_table	= sunxi_sram_dt_match,
394	},
395};
396builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe);
397
398MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
399MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
400MODULE_LICENSE("GPL");
401