1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SiFive L2 cache controller Driver
4 *
5 * Copyright (C) 2018-2019 SiFive, Inc.
6 *
7 */
8#include <linux/debugfs.h>
9#include <linux/interrupt.h>
10#include <linux/of_irq.h>
11#include <linux/of_address.h>
12#include <linux/device.h>
13#include <asm/cacheinfo.h>
14#include <soc/sifive/sifive_l2_cache.h>
15
16#define SIFIVE_L2_DIRECCFIX_LOW 0x100
17#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
18#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
19
20#define SIFIVE_L2_DATECCFIX_LOW 0x140
21#define SIFIVE_L2_DATECCFIX_HIGH 0x144
22#define SIFIVE_L2_DATECCFIX_COUNT 0x148
23
24#define SIFIVE_L2_DATECCFAIL_LOW 0x160
25#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
26#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
27
28#define SIFIVE_L2_CONFIG 0x00
29#define SIFIVE_L2_WAYENABLE 0x08
30#define SIFIVE_L2_ECCINJECTERR 0x40
31
32#define SIFIVE_L2_MAX_ECCINTR 3
33
34static void __iomem *l2_base;
35static int g_irq[SIFIVE_L2_MAX_ECCINTR];
36static struct riscv_cacheinfo_ops l2_cache_ops;
37
38enum {
39	DIR_CORR = 0,
40	DATA_CORR,
41	DATA_UNCORR,
42};
43
44#ifdef CONFIG_DEBUG_FS
45static struct dentry *sifive_test;
46
47static ssize_t l2_write(struct file *file, const char __user *data,
48			size_t count, loff_t *ppos)
49{
50	unsigned int val;
51
52	if (kstrtouint_from_user(data, count, 0, &val))
53		return -EINVAL;
54	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
55		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
56	else
57		return -EINVAL;
58	return count;
59}
60
61static const struct file_operations l2_fops = {
62	.owner = THIS_MODULE,
63	.open = simple_open,
64	.write = l2_write
65};
66
67static void setup_sifive_debug(void)
68{
69	sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
70
71	debugfs_create_file("sifive_debug_inject_error", 0200,
72			    sifive_test, NULL, &l2_fops);
73}
74#endif
75
76static void l2_config_read(void)
77{
78	u32 regval, val;
79
80	regval = readl(l2_base + SIFIVE_L2_CONFIG);
81	val = regval & 0xFF;
82	pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
83	val = (regval & 0xFF00) >> 8;
84	pr_info("L2CACHE: No. of ways per bank: %d\n", val);
85	val = (regval & 0xFF0000) >> 16;
86	pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
87	val = (regval & 0xFF000000) >> 24;
88	pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
89
90	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
91	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
92}
93
94static const struct of_device_id sifive_l2_ids[] = {
95	{ .compatible = "sifive,fu540-c000-ccache" },
96	{ /* end of table */ },
97};
98
99static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
100
101int register_sifive_l2_error_notifier(struct notifier_block *nb)
102{
103	return atomic_notifier_chain_register(&l2_err_chain, nb);
104}
105EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
106
107int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
108{
109	return atomic_notifier_chain_unregister(&l2_err_chain, nb);
110}
111EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
112
113static int l2_largest_wayenabled(void)
114{
115	return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
116}
117
118static ssize_t number_of_ways_enabled_show(struct device *dev,
119					   struct device_attribute *attr,
120					   char *buf)
121{
122	return sprintf(buf, "%u\n", l2_largest_wayenabled());
123}
124
125static DEVICE_ATTR_RO(number_of_ways_enabled);
126
127static struct attribute *priv_attrs[] = {
128	&dev_attr_number_of_ways_enabled.attr,
129	NULL,
130};
131
132static const struct attribute_group priv_attr_group = {
133	.attrs = priv_attrs,
134};
135
136static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
137{
138	/* We want to use private group for L2 cache only */
139	if (this_leaf->level == 2)
140		return &priv_attr_group;
141	else
142		return NULL;
143}
144
145static irqreturn_t l2_int_handler(int irq, void *device)
146{
147	unsigned int add_h, add_l;
148
149	if (irq == g_irq[DIR_CORR]) {
150		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
151		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
152		pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
153		/* Reading this register clears the DirError interrupt sig */
154		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
155		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
156					   "DirECCFix");
157	}
158	if (irq == g_irq[DATA_CORR]) {
159		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
160		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
161		pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
162		/* Reading this register clears the DataError interrupt sig */
163		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
164		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
165					   "DatECCFix");
166	}
167	if (irq == g_irq[DATA_UNCORR]) {
168		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
169		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
170		pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
171		/* Reading this register clears the DataFail interrupt sig */
172		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
173		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
174					   "DatECCFail");
175	}
176
177	return IRQ_HANDLED;
178}
179
180static int __init sifive_l2_init(void)
181{
182	struct device_node *np;
183	struct resource res;
184	int i, rc;
185
186	np = of_find_matching_node(NULL, sifive_l2_ids);
187	if (!np)
188		return -ENODEV;
189
190	if (of_address_to_resource(np, 0, &res))
191		return -ENODEV;
192
193	l2_base = ioremap(res.start, resource_size(&res));
194	if (!l2_base)
195		return -ENOMEM;
196
197	for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
198		g_irq[i] = irq_of_parse_and_map(np, i);
199		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
200		if (rc) {
201			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
202			return rc;
203		}
204	}
205
206	l2_config_read();
207
208	l2_cache_ops.get_priv_group = l2_get_priv_group;
209	riscv_set_cacheinfo_ops(&l2_cache_ops);
210
211#ifdef CONFIG_DEBUG_FS
212	setup_sifive_debug();
213#endif
214	return 0;
215}
216device_initcall(sifive_l2_init);
217