1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car SYSC Power management support
4 *
5 * Copyright (C) 2014  Magnus Damm
6 * Copyright (C) 2015-2017 Glider bvba
7 */
8
9#include <linux/clk/renesas.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/mm.h>
13#include <linux/of_address.h>
14#include <linux/pm_domain.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/io.h>
18#include <linux/soc/renesas/rcar-sysc.h>
19
20#include "rcar-sysc.h"
21
22/* SYSC Common */
23#define SYSCSR			0x00	/* SYSC Status Register */
24#define SYSCISR			0x04	/* Interrupt Status Register */
25#define SYSCISCR		0x08	/* Interrupt Status Clear Register */
26#define SYSCIER			0x0c	/* Interrupt Enable Register */
27#define SYSCIMR			0x10	/* Interrupt Mask Register */
28
29/* SYSC Status Register */
30#define SYSCSR_PONENB		1	/* Ready for power resume requests */
31#define SYSCSR_POFFENB		0	/* Ready for power shutoff requests */
32
33/*
34 * Power Control Register Offsets inside the register block for each domain
35 * Note: The "CR" registers for ARM cores exist on H1 only
36 *	 Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
37 *	 Use PSCI on R-Car Gen3
38 */
39#define PWRSR_OFFS		0x00	/* Power Status Register */
40#define PWROFFCR_OFFS		0x04	/* Power Shutoff Control Register */
41#define PWROFFSR_OFFS		0x08	/* Power Shutoff Status Register */
42#define PWRONCR_OFFS		0x0c	/* Power Resume Control Register */
43#define PWRONSR_OFFS		0x10	/* Power Resume Status Register */
44#define PWRER_OFFS		0x14	/* Power Shutoff/Resume Error */
45
46
47#define SYSCSR_RETRIES		100
48#define SYSCSR_DELAY_US		1
49
50#define PWRER_RETRIES		100
51#define PWRER_DELAY_US		1
52
53#define SYSCISR_RETRIES		1000
54#define SYSCISR_DELAY_US	1
55
56#define RCAR_PD_ALWAYS_ON	32	/* Always-on power area */
57
58struct rcar_sysc_ch {
59	u16 chan_offs;
60	u8 chan_bit;
61	u8 isr_bit;
62};
63
64static void __iomem *rcar_sysc_base;
65static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
66static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
67
68static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
69{
70	unsigned int sr_bit, reg_offs;
71	int k;
72
73	if (on) {
74		sr_bit = SYSCSR_PONENB;
75		reg_offs = PWRONCR_OFFS;
76	} else {
77		sr_bit = SYSCSR_POFFENB;
78		reg_offs = PWROFFCR_OFFS;
79	}
80
81	/* Wait until SYSC is ready to accept a power request */
82	for (k = 0; k < SYSCSR_RETRIES; k++) {
83		if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
84			break;
85		udelay(SYSCSR_DELAY_US);
86	}
87
88	if (k == SYSCSR_RETRIES)
89		return -EAGAIN;
90
91	/* Submit power shutoff or power resume request */
92	iowrite32(BIT(sysc_ch->chan_bit),
93		  rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
94
95	return 0;
96}
97
98static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
99{
100	unsigned int isr_mask = BIT(sysc_ch->isr_bit);
101	unsigned int chan_mask = BIT(sysc_ch->chan_bit);
102	unsigned int status;
103	unsigned long flags;
104	int ret = 0;
105	int k;
106
107	spin_lock_irqsave(&rcar_sysc_lock, flags);
108
109	/*
110	 * Mask external power requests for CPU or 3DG domains
111	 */
112	if (rcar_sysc_extmask_val) {
113		iowrite32(rcar_sysc_extmask_val,
114			  rcar_sysc_base + rcar_sysc_extmask_offs);
115	}
116
117	/*
118	 * The interrupt source needs to be enabled, but masked, to prevent the
119	 * CPU from receiving it.
120	 */
121	iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
122		  rcar_sysc_base + SYSCIMR);
123	iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
124		  rcar_sysc_base + SYSCIER);
125
126	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
127
128	/* Submit power shutoff or resume request until it was accepted */
129	for (k = 0; k < PWRER_RETRIES; k++) {
130		ret = rcar_sysc_pwr_on_off(sysc_ch, on);
131		if (ret)
132			goto out;
133
134		status = ioread32(rcar_sysc_base +
135				  sysc_ch->chan_offs + PWRER_OFFS);
136		if (!(status & chan_mask))
137			break;
138
139		udelay(PWRER_DELAY_US);
140	}
141
142	if (k == PWRER_RETRIES) {
143		ret = -EIO;
144		goto out;
145	}
146
147	/* Wait until the power shutoff or resume request has completed * */
148	for (k = 0; k < SYSCISR_RETRIES; k++) {
149		if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
150			break;
151		udelay(SYSCISR_DELAY_US);
152	}
153
154	if (k == SYSCISR_RETRIES)
155		ret = -EIO;
156
157	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
158
159 out:
160	if (rcar_sysc_extmask_val)
161		iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
162
163	spin_unlock_irqrestore(&rcar_sysc_lock, flags);
164
165	pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
166		 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
167	return ret;
168}
169
170static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
171{
172	unsigned int st;
173
174	st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
175	if (st & BIT(sysc_ch->chan_bit))
176		return true;
177
178	return false;
179}
180
181struct rcar_sysc_pd {
182	struct generic_pm_domain genpd;
183	struct rcar_sysc_ch ch;
184	unsigned int flags;
185	char name[];
186};
187
188static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
189{
190	return container_of(d, struct rcar_sysc_pd, genpd);
191}
192
193static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
194{
195	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
196
197	pr_debug("%s: %s\n", __func__, genpd->name);
198	return rcar_sysc_power(&pd->ch, false);
199}
200
201static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
202{
203	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
204
205	pr_debug("%s: %s\n", __func__, genpd->name);
206	return rcar_sysc_power(&pd->ch, true);
207}
208
209static bool has_cpg_mstp;
210
211static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
212{
213	struct generic_pm_domain *genpd = &pd->genpd;
214	const char *name = pd->genpd.name;
215	int error;
216
217	if (pd->flags & PD_CPU) {
218		/*
219		 * This domain contains a CPU core and therefore it should
220		 * only be turned off if the CPU is not in use.
221		 */
222		pr_debug("PM domain %s contains %s\n", name, "CPU");
223		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
224	} else if (pd->flags & PD_SCU) {
225		/*
226		 * This domain contains an SCU and cache-controller, and
227		 * therefore it should only be turned off if the CPU cores are
228		 * not in use.
229		 */
230		pr_debug("PM domain %s contains %s\n", name, "SCU");
231		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
232	} else if (pd->flags & PD_NO_CR) {
233		/*
234		 * This domain cannot be turned off.
235		 */
236		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
237	}
238
239	if (!(pd->flags & (PD_CPU | PD_SCU))) {
240		/* Enable Clock Domain for I/O devices */
241		genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
242		if (has_cpg_mstp) {
243			genpd->attach_dev = cpg_mstp_attach_dev;
244			genpd->detach_dev = cpg_mstp_detach_dev;
245		} else {
246			genpd->attach_dev = cpg_mssr_attach_dev;
247			genpd->detach_dev = cpg_mssr_detach_dev;
248		}
249	}
250
251	genpd->power_off = rcar_sysc_pd_power_off;
252	genpd->power_on = rcar_sysc_pd_power_on;
253
254	if (pd->flags & (PD_CPU | PD_NO_CR)) {
255		/* Skip CPUs (handled by SMP code) and areas without control */
256		pr_debug("%s: Not touching %s\n", __func__, genpd->name);
257		goto finalize;
258	}
259
260	if (!rcar_sysc_power_is_off(&pd->ch)) {
261		pr_debug("%s: %s is already powered\n", __func__, genpd->name);
262		goto finalize;
263	}
264
265	rcar_sysc_power(&pd->ch, true);
266
267finalize:
268	error = pm_genpd_init(genpd, &simple_qos_governor, false);
269	if (error)
270		pr_err("Failed to init PM domain %s: %d\n", name, error);
271
272	return error;
273}
274
275static const struct of_device_id rcar_sysc_matches[] __initconst = {
276#ifdef CONFIG_SYSC_R8A7742
277	{ .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
278#endif
279#ifdef CONFIG_SYSC_R8A7743
280	{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
281	/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
282	{ .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
283#endif
284#ifdef CONFIG_SYSC_R8A7745
285	{ .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
286#endif
287#ifdef CONFIG_SYSC_R8A77470
288	{ .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
289#endif
290#ifdef CONFIG_SYSC_R8A774A1
291	{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
292#endif
293#ifdef CONFIG_SYSC_R8A774B1
294	{ .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
295#endif
296#ifdef CONFIG_SYSC_R8A774C0
297	{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
298#endif
299#ifdef CONFIG_SYSC_R8A774E1
300	{ .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
301#endif
302#ifdef CONFIG_SYSC_R8A7779
303	{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
304#endif
305#ifdef CONFIG_SYSC_R8A7790
306	{ .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
307#endif
308#ifdef CONFIG_SYSC_R8A7791
309	{ .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
310	/* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
311	{ .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
312#endif
313#ifdef CONFIG_SYSC_R8A7792
314	{ .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
315#endif
316#ifdef CONFIG_SYSC_R8A7794
317	{ .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
318#endif
319#ifdef CONFIG_SYSC_R8A7795
320	{ .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
321#endif
322#ifdef CONFIG_SYSC_R8A77960
323	{ .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
324#endif
325#ifdef CONFIG_SYSC_R8A77961
326	{ .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
327#endif
328#ifdef CONFIG_SYSC_R8A77965
329	{ .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
330#endif
331#ifdef CONFIG_SYSC_R8A77970
332	{ .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
333#endif
334#ifdef CONFIG_SYSC_R8A77980
335	{ .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
336#endif
337#ifdef CONFIG_SYSC_R8A77990
338	{ .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
339#endif
340#ifdef CONFIG_SYSC_R8A77995
341	{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
342#endif
343	{ /* sentinel */ }
344};
345
346struct rcar_pm_domains {
347	struct genpd_onecell_data onecell_data;
348	struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
349};
350
351static struct genpd_onecell_data *rcar_sysc_onecell_data;
352
353static int __init rcar_sysc_pd_init(void)
354{
355	const struct rcar_sysc_info *info;
356	const struct of_device_id *match;
357	struct rcar_pm_domains *domains;
358	struct device_node *np;
359	void __iomem *base;
360	unsigned int i;
361	int error;
362
363	np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
364	if (!np)
365		return -ENODEV;
366
367	info = match->data;
368
369	if (info->init) {
370		error = info->init();
371		if (error)
372			goto out_put;
373	}
374
375	has_cpg_mstp = of_find_compatible_node(NULL, NULL,
376					       "renesas,cpg-mstp-clocks");
377
378	base = of_iomap(np, 0);
379	if (!base) {
380		pr_warn("%pOF: Cannot map regs\n", np);
381		error = -ENOMEM;
382		goto out_put;
383	}
384
385	rcar_sysc_base = base;
386
387	/* Optional External Request Mask Register */
388	rcar_sysc_extmask_offs = info->extmask_offs;
389	rcar_sysc_extmask_val = info->extmask_val;
390
391	domains = kzalloc(sizeof(*domains), GFP_KERNEL);
392	if (!domains) {
393		error = -ENOMEM;
394		goto out_put;
395	}
396
397	domains->onecell_data.domains = domains->domains;
398	domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
399	rcar_sysc_onecell_data = &domains->onecell_data;
400
401	for (i = 0; i < info->num_areas; i++) {
402		const struct rcar_sysc_area *area = &info->areas[i];
403		struct rcar_sysc_pd *pd;
404
405		if (!area->name) {
406			/* Skip NULLified area */
407			continue;
408		}
409
410		pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
411		if (!pd) {
412			error = -ENOMEM;
413			goto out_put;
414		}
415
416		strcpy(pd->name, area->name);
417		pd->genpd.name = pd->name;
418		pd->ch.chan_offs = area->chan_offs;
419		pd->ch.chan_bit = area->chan_bit;
420		pd->ch.isr_bit = area->isr_bit;
421		pd->flags = area->flags;
422
423		error = rcar_sysc_pd_setup(pd);
424		if (error)
425			goto out_put;
426
427		domains->domains[area->isr_bit] = &pd->genpd;
428
429		if (area->parent < 0)
430			continue;
431
432		error = pm_genpd_add_subdomain(domains->domains[area->parent],
433					       &pd->genpd);
434		if (error) {
435			pr_warn("Failed to add PM subdomain %s to parent %u\n",
436				area->name, area->parent);
437			goto out_put;
438		}
439	}
440
441	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
442
443out_put:
444	of_node_put(np);
445	return error;
446}
447early_initcall(rcar_sysc_pd_init);
448
449void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
450			      unsigned int num_areas, u8 id)
451{
452	unsigned int i;
453
454	for (i = 0; i < num_areas; i++)
455		if (areas[i].isr_bit == id) {
456			areas[i].name = NULL;
457			return;
458		}
459}
460
461#ifdef CONFIG_ARCH_R8A7779
462static int rcar_sysc_power_cpu(unsigned int idx, bool on)
463{
464	struct generic_pm_domain *genpd;
465	struct rcar_sysc_pd *pd;
466	unsigned int i;
467
468	if (!rcar_sysc_onecell_data)
469		return -ENODEV;
470
471	for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
472		genpd = rcar_sysc_onecell_data->domains[i];
473		if (!genpd)
474			continue;
475
476		pd = to_rcar_pd(genpd);
477		if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
478			continue;
479
480		return rcar_sysc_power(&pd->ch, on);
481	}
482
483	return -ENOENT;
484}
485
486int rcar_sysc_power_down_cpu(unsigned int cpu)
487{
488	return rcar_sysc_power_cpu(cpu, false);
489}
490
491int rcar_sysc_power_up_cpu(unsigned int cpu)
492{
493	return rcar_sysc_power_cpu(cpu, true);
494}
495#endif /* CONFIG_ARCH_R8A7779 */
496