1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/slab.h> 7#include <linux/dma-mapping.h> 8#include <linux/io.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/of_platform.h> 12#include <linux/pinctrl/consumer.h> 13#include <linux/platform_device.h> 14#include <linux/qcom-geni-se.h> 15 16/** 17 * DOC: Overview 18 * 19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced 20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper 21 * controller. QUP Wrapper is designed to support various serial bus protocols 22 * like UART, SPI, I2C, I3C, etc. 23 */ 24 25/** 26 * DOC: Hardware description 27 * 28 * GENI based QUP is a highly-flexible and programmable module for supporting 29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single 30 * QUP module can provide upto 8 serial interfaces, using its internal 31 * serial engines. The actual configuration is determined by the target 32 * platform configuration. The protocol supported by each interface is 33 * determined by the firmware loaded to the serial engine. Each SE consists 34 * of a DMA Engine and GENI sub modules which enable serial engines to 35 * support FIFO and DMA modes of operation. 36 * 37 * 38 * +-----------------------------------------+ 39 * |QUP Wrapper | 40 * | +----------------------------+ | 41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------> 42 * | | ... | | Interface 43 * <---Clock Perf.----+ +----+-----------------------+ | | 44 * State Interface | | Serial Engine 1 | | | 45 * | | | | | 46 * | | | | | 47 * <--------AHB-------> | | | | 48 * | | +----+ | 49 * | | | | 50 * | | | | 51 * <------SE IRQ------+ +----------------------------+ | 52 * | | 53 * +-----------------------------------------+ 54 * 55 * Figure 1: GENI based QUP Wrapper 56 * 57 * The GENI submodules include primary and secondary sequencers which are 58 * used to drive TX & RX operations. On serial interfaces that operate using 59 * master-slave model, primary sequencer drives both TX & RX operations. On 60 * serial interfaces that operate using peer-to-peer model, primary sequencer 61 * drives TX operation and secondary sequencer drives RX operation. 62 */ 63 64/** 65 * DOC: Software description 66 * 67 * GENI SE Wrapper driver is structured into 2 parts: 68 * 69 * geni_wrapper represents QUP Wrapper controller. This part of the driver 70 * manages QUP Wrapper information such as hardware version, clock 71 * performance table that is common to all the internal serial engines. 72 * 73 * geni_se represents serial engine. This part of the driver manages serial 74 * engine information such as clocks, containing QUP Wrapper, etc. This part 75 * of driver also supports operations (eg. initialize the concerned serial 76 * engine, select between FIFO and DMA mode of operation etc.) that are 77 * common to all the serial engines and are independent of serial interfaces. 78 */ 79 80#define MAX_CLK_PERF_LEVEL 32 81#define NUM_AHB_CLKS 2 82 83/** 84 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core 85 * @dev: Device pointer of the QUP wrapper core 86 * @base: Base address of this instance of QUP wrapper core 87 * @ahb_clks: Handle to the primary & secondary AHB clocks 88 */ 89struct geni_wrapper { 90 struct device *dev; 91 void __iomem *base; 92 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS]; 93}; 94 95static const char * const icc_path_names[] = {"qup-core", "qup-config", 96 "qup-memory"}; 97 98#define QUP_HW_VER_REG 0x4 99 100/* Common SE registers */ 101#define GENI_INIT_CFG_REVISION 0x0 102#define GENI_S_INIT_CFG_REVISION 0x4 103#define GENI_OUTPUT_CTRL 0x24 104#define GENI_CGC_CTRL 0x28 105#define GENI_CLK_CTRL_RO 0x60 106#define GENI_IF_DISABLE_RO 0x64 107#define GENI_FW_S_REVISION_RO 0x6c 108#define SE_GENI_BYTE_GRAN 0x254 109#define SE_GENI_TX_PACKING_CFG0 0x260 110#define SE_GENI_TX_PACKING_CFG1 0x264 111#define SE_GENI_RX_PACKING_CFG0 0x284 112#define SE_GENI_RX_PACKING_CFG1 0x288 113#define SE_GENI_M_GP_LENGTH 0x910 114#define SE_GENI_S_GP_LENGTH 0x914 115#define SE_DMA_TX_PTR_L 0xc30 116#define SE_DMA_TX_PTR_H 0xc34 117#define SE_DMA_TX_ATTR 0xc38 118#define SE_DMA_TX_LEN 0xc3c 119#define SE_DMA_TX_IRQ_EN 0xc48 120#define SE_DMA_TX_IRQ_EN_SET 0xc4c 121#define SE_DMA_TX_IRQ_EN_CLR 0xc50 122#define SE_DMA_TX_LEN_IN 0xc54 123#define SE_DMA_TX_MAX_BURST 0xc5c 124#define SE_DMA_RX_PTR_L 0xd30 125#define SE_DMA_RX_PTR_H 0xd34 126#define SE_DMA_RX_ATTR 0xd38 127#define SE_DMA_RX_LEN 0xd3c 128#define SE_DMA_RX_IRQ_EN 0xd48 129#define SE_DMA_RX_IRQ_EN_SET 0xd4c 130#define SE_DMA_RX_IRQ_EN_CLR 0xd50 131#define SE_DMA_RX_LEN_IN 0xd54 132#define SE_DMA_RX_MAX_BURST 0xd5c 133#define SE_DMA_RX_FLUSH 0xd60 134#define SE_GSI_EVENT_EN 0xe18 135#define SE_IRQ_EN 0xe1c 136#define SE_DMA_GENERAL_CFG 0xe30 137 138/* GENI_OUTPUT_CTRL fields */ 139#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 140 141/* GENI_CGC_CTRL fields */ 142#define CFG_AHB_CLK_CGC_ON BIT(0) 143#define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 144#define DATA_AHB_CLK_CGC_ON BIT(2) 145#define SCLK_CGC_ON BIT(3) 146#define TX_CLK_CGC_ON BIT(4) 147#define RX_CLK_CGC_ON BIT(5) 148#define EXT_CLK_CGC_ON BIT(6) 149#define PROG_RAM_HCLK_OFF BIT(8) 150#define PROG_RAM_SCLK_OFF BIT(9) 151#define DEFAULT_CGC_EN GENMASK(6, 0) 152 153/* SE_GSI_EVENT_EN fields */ 154#define DMA_RX_EVENT_EN BIT(0) 155#define DMA_TX_EVENT_EN BIT(1) 156#define GENI_M_EVENT_EN BIT(2) 157#define GENI_S_EVENT_EN BIT(3) 158 159/* SE_IRQ_EN fields */ 160#define DMA_RX_IRQ_EN BIT(0) 161#define DMA_TX_IRQ_EN BIT(1) 162#define GENI_M_IRQ_EN BIT(2) 163#define GENI_S_IRQ_EN BIT(3) 164 165/* SE_DMA_GENERAL_CFG */ 166#define DMA_RX_CLK_CGC_ON BIT(0) 167#define DMA_TX_CLK_CGC_ON BIT(1) 168#define DMA_AHB_SLV_CFG_ON BIT(2) 169#define AHB_SEC_SLV_CLK_CGC_ON BIT(3) 170#define DUMMY_RX_NON_BUFFERABLE BIT(4) 171#define RX_DMA_ZERO_PADDING_EN BIT(5) 172#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) 173#define RX_DMA_IRQ_DELAY_SHFT 6 174 175/** 176 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version 177 * @se: Pointer to the corresponding serial engine. 178 * 179 * Return: Hardware Version of the wrapper. 180 */ 181u32 geni_se_get_qup_hw_version(struct geni_se *se) 182{ 183 struct geni_wrapper *wrapper = se->wrapper; 184 185 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); 186} 187EXPORT_SYMBOL(geni_se_get_qup_hw_version); 188 189static void geni_se_io_set_mode(void __iomem *base) 190{ 191 u32 val; 192 193 val = readl_relaxed(base + SE_IRQ_EN); 194 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN; 195 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN; 196 writel_relaxed(val, base + SE_IRQ_EN); 197 198 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 199 val &= ~GENI_DMA_MODE_EN; 200 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); 201 202 writel_relaxed(0, base + SE_GSI_EVENT_EN); 203} 204 205static void geni_se_io_init(void __iomem *base) 206{ 207 u32 val; 208 209 val = readl_relaxed(base + GENI_CGC_CTRL); 210 val |= DEFAULT_CGC_EN; 211 writel_relaxed(val, base + GENI_CGC_CTRL); 212 213 val = readl_relaxed(base + SE_DMA_GENERAL_CFG); 214 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; 215 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; 216 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); 217 218 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); 219 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); 220} 221 222static void geni_se_irq_clear(struct geni_se *se) 223{ 224 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); 225 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); 226 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); 227 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); 228 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); 229 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); 230} 231 232/** 233 * geni_se_init() - Initialize the GENI serial engine 234 * @se: Pointer to the concerned serial engine. 235 * @rx_wm: Receive watermark, in units of FIFO words. 236 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words. 237 * 238 * This function is used to initialize the GENI serial engine, configure 239 * receive watermark and ready-for-receive watermarks. 240 */ 241void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) 242{ 243 u32 val; 244 245 geni_se_irq_clear(se); 246 geni_se_io_init(se->base); 247 geni_se_io_set_mode(se->base); 248 249 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); 250 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); 251 252 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 253 val |= M_COMMON_GENI_M_IRQ_EN; 254 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 255 256 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 257 val |= S_COMMON_GENI_S_IRQ_EN; 258 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 259} 260EXPORT_SYMBOL(geni_se_init); 261 262static void geni_se_select_fifo_mode(struct geni_se *se) 263{ 264 u32 proto = geni_se_read_proto(se); 265 u32 val; 266 267 geni_se_irq_clear(se); 268 269 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 270 if (proto != GENI_SE_UART) { 271 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 272 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 273 } 274 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 275 276 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 277 if (proto != GENI_SE_UART) 278 val |= S_CMD_DONE_EN; 279 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 280 281 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 282 val &= ~GENI_DMA_MODE_EN; 283 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 284} 285 286static void geni_se_select_dma_mode(struct geni_se *se) 287{ 288 u32 proto = geni_se_read_proto(se); 289 u32 val; 290 291 geni_se_irq_clear(se); 292 293 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 294 if (proto != GENI_SE_UART) { 295 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 296 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 297 } 298 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 299 300 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 301 if (proto != GENI_SE_UART) 302 val &= ~S_CMD_DONE_EN; 303 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 304 305 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 306 val |= GENI_DMA_MODE_EN; 307 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 308} 309 310/** 311 * geni_se_select_mode() - Select the serial engine transfer mode 312 * @se: Pointer to the concerned serial engine. 313 * @mode: Transfer mode to be selected. 314 */ 315void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) 316{ 317 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); 318 319 switch (mode) { 320 case GENI_SE_FIFO: 321 geni_se_select_fifo_mode(se); 322 break; 323 case GENI_SE_DMA: 324 geni_se_select_dma_mode(se); 325 break; 326 case GENI_SE_INVALID: 327 default: 328 break; 329 } 330} 331EXPORT_SYMBOL(geni_se_select_mode); 332 333/** 334 * DOC: Overview 335 * 336 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist 337 * of up to 4 operations, each operation represented by 4 configuration vectors 338 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for 339 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO. 340 * Refer to below examples for detailed bit-field description. 341 * 342 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1 343 * 344 * +-----------+-------+-------+-------+-------+ 345 * | | vec_0 | vec_1 | vec_2 | vec_3 | 346 * +-----------+-------+-------+-------+-------+ 347 * | start | 0x6 | 0xe | 0x16 | 0x1e | 348 * | direction | 1 | 1 | 1 | 1 | 349 * | length | 6 | 6 | 6 | 6 | 350 * | stop | 0 | 0 | 0 | 1 | 351 * +-----------+-------+-------+-------+-------+ 352 * 353 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0 354 * 355 * +-----------+-------+-------+-------+-------+ 356 * | | vec_0 | vec_1 | vec_2 | vec_3 | 357 * +-----------+-------+-------+-------+-------+ 358 * | start | 0x0 | 0x8 | 0x10 | 0x18 | 359 * | direction | 0 | 0 | 0 | 0 | 360 * | length | 7 | 6 | 7 | 6 | 361 * | stop | 0 | 0 | 0 | 1 | 362 * +-----------+-------+-------+-------+-------+ 363 * 364 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1 365 * 366 * +-----------+-------+-------+-------+-------+ 367 * | | vec_0 | vec_1 | vec_2 | vec_3 | 368 * +-----------+-------+-------+-------+-------+ 369 * | start | 0x16 | 0xe | 0x6 | 0x0 | 370 * | direction | 1 | 1 | 1 | 1 | 371 * | length | 7 | 7 | 6 | 0 | 372 * | stop | 0 | 0 | 1 | 0 | 373 * +-----------+-------+-------+-------+-------+ 374 * 375 */ 376 377#define NUM_PACKING_VECTORS 4 378#define PACKING_START_SHIFT 5 379#define PACKING_DIR_SHIFT 4 380#define PACKING_LEN_SHIFT 1 381#define PACKING_STOP_BIT BIT(0) 382#define PACKING_VECTOR_SHIFT 10 383/** 384 * geni_se_config_packing() - Packing configuration of the serial engine 385 * @se: Pointer to the concerned serial engine 386 * @bpw: Bits of data per transfer word. 387 * @pack_words: Number of words per fifo element. 388 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa. 389 * @tx_cfg: Flag to configure the TX Packing. 390 * @rx_cfg: Flag to configure the RX Packing. 391 * 392 * This function is used to configure the packing rules for the current 393 * transfer. 394 */ 395void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 396 bool msb_to_lsb, bool tx_cfg, bool rx_cfg) 397{ 398 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; 399 int len; 400 int temp_bpw = bpw; 401 int idx_start = msb_to_lsb ? bpw - 1 : 0; 402 int idx = idx_start; 403 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; 404 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE); 405 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE; 406 int i; 407 408 if (iter <= 0 || iter > NUM_PACKING_VECTORS) 409 return; 410 411 for (i = 0; i < iter; i++) { 412 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; 413 cfg[i] = idx << PACKING_START_SHIFT; 414 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT; 415 cfg[i] |= len << PACKING_LEN_SHIFT; 416 417 if (temp_bpw <= BITS_PER_BYTE) { 418 idx = ((i + 1) * BITS_PER_BYTE) + idx_start; 419 temp_bpw = bpw; 420 } else { 421 idx = idx + idx_delta; 422 temp_bpw = temp_bpw - BITS_PER_BYTE; 423 } 424 } 425 cfg[iter - 1] |= PACKING_STOP_BIT; 426 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); 427 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); 428 429 if (tx_cfg) { 430 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); 431 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); 432 } 433 if (rx_cfg) { 434 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); 435 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); 436 } 437 438 /* 439 * Number of protocol words in each FIFO entry 440 * 0 - 4x8, four words in each entry, max word size of 8 bits 441 * 1 - 2x16, two words in each entry, max word size of 16 bits 442 * 2 - 1x32, one word in each entry, max word size of 32 bits 443 * 3 - undefined 444 */ 445 if (pack_words || bpw == 32) 446 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); 447} 448EXPORT_SYMBOL(geni_se_config_packing); 449 450static void geni_se_clks_off(struct geni_se *se) 451{ 452 struct geni_wrapper *wrapper = se->wrapper; 453 454 clk_disable_unprepare(se->clk); 455 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 456 wrapper->ahb_clks); 457} 458 459/** 460 * geni_se_resources_off() - Turn off resources associated with the serial 461 * engine 462 * @se: Pointer to the concerned serial engine. 463 * 464 * Return: 0 on success, standard Linux error codes on failure/error. 465 */ 466int geni_se_resources_off(struct geni_se *se) 467{ 468 int ret; 469 470 if (has_acpi_companion(se->dev)) 471 return 0; 472 473 ret = pinctrl_pm_select_sleep_state(se->dev); 474 if (ret) 475 return ret; 476 477 geni_se_clks_off(se); 478 return 0; 479} 480EXPORT_SYMBOL(geni_se_resources_off); 481 482static int geni_se_clks_on(struct geni_se *se) 483{ 484 int ret; 485 struct geni_wrapper *wrapper = se->wrapper; 486 487 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), 488 wrapper->ahb_clks); 489 if (ret) 490 return ret; 491 492 ret = clk_prepare_enable(se->clk); 493 if (ret) 494 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), 495 wrapper->ahb_clks); 496 return ret; 497} 498 499/** 500 * geni_se_resources_on() - Turn on resources associated with the serial 501 * engine 502 * @se: Pointer to the concerned serial engine. 503 * 504 * Return: 0 on success, standard Linux error codes on failure/error. 505 */ 506int geni_se_resources_on(struct geni_se *se) 507{ 508 int ret; 509 510 if (has_acpi_companion(se->dev)) 511 return 0; 512 513 ret = geni_se_clks_on(se); 514 if (ret) 515 return ret; 516 517 ret = pinctrl_pm_select_default_state(se->dev); 518 if (ret) 519 geni_se_clks_off(se); 520 521 return ret; 522} 523EXPORT_SYMBOL(geni_se_resources_on); 524 525/** 526 * geni_se_clk_tbl_get() - Get the clock table to program DFS 527 * @se: Pointer to the concerned serial engine. 528 * @tbl: Table in which the output is returned. 529 * 530 * This function is called by the protocol drivers to determine the different 531 * clock frequencies supported by serial engine core clock. The protocol 532 * drivers use the output to determine the clock frequency index to be 533 * programmed into DFS. 534 * 535 * Return: number of valid performance levels in the table on success, 536 * standard Linux error codes on failure. 537 */ 538int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl) 539{ 540 long freq = 0; 541 int i; 542 543 if (se->clk_perf_tbl) { 544 *tbl = se->clk_perf_tbl; 545 return se->num_clk_levels; 546 } 547 548 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, 549 sizeof(*se->clk_perf_tbl), 550 GFP_KERNEL); 551 if (!se->clk_perf_tbl) 552 return -ENOMEM; 553 554 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) { 555 freq = clk_round_rate(se->clk, freq + 1); 556 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) 557 break; 558 se->clk_perf_tbl[i] = freq; 559 } 560 se->num_clk_levels = i; 561 *tbl = se->clk_perf_tbl; 562 return se->num_clk_levels; 563} 564EXPORT_SYMBOL(geni_se_clk_tbl_get); 565 566/** 567 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency 568 * @se: Pointer to the concerned serial engine. 569 * @req_freq: Requested clock frequency. 570 * @index: Index of the resultant frequency in the table. 571 * @res_freq: Resultant frequency of the source clock. 572 * @exact: Flag to indicate exact multiple requirement of the requested 573 * frequency. 574 * 575 * This function is called by the protocol drivers to determine the best match 576 * of the requested frequency as provided by the serial engine clock in order 577 * to meet the performance requirements. 578 * 579 * If we return success: 580 * - if @exact is true then @res_freq / <an_integer> == @req_freq 581 * - if @exact is false then @res_freq / <an_integer> <= @req_freq 582 * 583 * Return: 0 on success, standard Linux error codes on failure. 584 */ 585int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 586 unsigned int *index, unsigned long *res_freq, 587 bool exact) 588{ 589 unsigned long *tbl; 590 int num_clk_levels; 591 int i; 592 unsigned long best_delta; 593 unsigned long new_delta; 594 unsigned int divider; 595 596 num_clk_levels = geni_se_clk_tbl_get(se, &tbl); 597 if (num_clk_levels < 0) 598 return num_clk_levels; 599 600 if (num_clk_levels == 0) 601 return -EINVAL; 602 603 best_delta = ULONG_MAX; 604 for (i = 0; i < num_clk_levels; i++) { 605 divider = DIV_ROUND_UP(tbl[i], req_freq); 606 new_delta = req_freq - tbl[i] / divider; 607 if (new_delta < best_delta) { 608 /* We have a new best! */ 609 *index = i; 610 *res_freq = tbl[i]; 611 612 /* If the new best is exact then we're done */ 613 if (new_delta == 0) 614 return 0; 615 616 /* Record how close we got */ 617 best_delta = new_delta; 618 } 619 } 620 621 if (exact) 622 return -EINVAL; 623 624 return 0; 625} 626EXPORT_SYMBOL(geni_se_clk_freq_match); 627 628#define GENI_SE_DMA_DONE_EN BIT(0) 629#define GENI_SE_DMA_EOT_EN BIT(1) 630#define GENI_SE_DMA_AHB_ERR_EN BIT(2) 631#define GENI_SE_DMA_EOT_BUF BIT(0) 632/** 633 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer 634 * @se: Pointer to the concerned serial engine. 635 * @buf: Pointer to the TX buffer. 636 * @len: Length of the TX buffer. 637 * @iova: Pointer to store the mapped DMA address. 638 * 639 * This function is used to prepare the buffers for DMA TX. 640 * 641 * Return: 0 on success, standard Linux error codes on failure. 642 */ 643int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 644 dma_addr_t *iova) 645{ 646 struct geni_wrapper *wrapper = se->wrapper; 647 u32 val; 648 649 if (!wrapper) 650 return -EINVAL; 651 652 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); 653 if (dma_mapping_error(wrapper->dev, *iova)) 654 return -EIO; 655 656 val = GENI_SE_DMA_DONE_EN; 657 val |= GENI_SE_DMA_EOT_EN; 658 val |= GENI_SE_DMA_AHB_ERR_EN; 659 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); 660 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 661 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 662 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 663 writel(len, se->base + SE_DMA_TX_LEN); 664 return 0; 665} 666EXPORT_SYMBOL(geni_se_tx_dma_prep); 667 668/** 669 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer 670 * @se: Pointer to the concerned serial engine. 671 * @buf: Pointer to the RX buffer. 672 * @len: Length of the RX buffer. 673 * @iova: Pointer to store the mapped DMA address. 674 * 675 * This function is used to prepare the buffers for DMA RX. 676 * 677 * Return: 0 on success, standard Linux error codes on failure. 678 */ 679int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 680 dma_addr_t *iova) 681{ 682 struct geni_wrapper *wrapper = se->wrapper; 683 u32 val; 684 685 if (!wrapper) 686 return -EINVAL; 687 688 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); 689 if (dma_mapping_error(wrapper->dev, *iova)) 690 return -EIO; 691 692 val = GENI_SE_DMA_DONE_EN; 693 val |= GENI_SE_DMA_EOT_EN; 694 val |= GENI_SE_DMA_AHB_ERR_EN; 695 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); 696 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); 697 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 698 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 699 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 700 writel(len, se->base + SE_DMA_RX_LEN); 701 return 0; 702} 703EXPORT_SYMBOL(geni_se_rx_dma_prep); 704 705/** 706 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer 707 * @se: Pointer to the concerned serial engine. 708 * @iova: DMA address of the TX buffer. 709 * @len: Length of the TX buffer. 710 * 711 * This function is used to unprepare the DMA buffers after DMA TX. 712 */ 713void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 714{ 715 struct geni_wrapper *wrapper = se->wrapper; 716 717 if (iova && !dma_mapping_error(wrapper->dev, iova)) 718 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); 719} 720EXPORT_SYMBOL(geni_se_tx_dma_unprep); 721 722/** 723 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer 724 * @se: Pointer to the concerned serial engine. 725 * @iova: DMA address of the RX buffer. 726 * @len: Length of the RX buffer. 727 * 728 * This function is used to unprepare the DMA buffers after DMA RX. 729 */ 730void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) 731{ 732 struct geni_wrapper *wrapper = se->wrapper; 733 734 if (iova && !dma_mapping_error(wrapper->dev, iova)) 735 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); 736} 737EXPORT_SYMBOL(geni_se_rx_dma_unprep); 738 739int geni_icc_get(struct geni_se *se, const char *icc_ddr) 740{ 741 int i, err; 742 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; 743 744 if (has_acpi_companion(se->dev)) 745 return 0; 746 747 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 748 if (!icc_names[i]) 749 continue; 750 751 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); 752 if (IS_ERR(se->icc_paths[i].path)) 753 goto err; 754 } 755 756 return 0; 757 758err: 759 err = PTR_ERR(se->icc_paths[i].path); 760 if (err != -EPROBE_DEFER) 761 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", 762 icc_names[i], err); 763 return err; 764 765} 766EXPORT_SYMBOL(geni_icc_get); 767 768int geni_icc_set_bw(struct geni_se *se) 769{ 770 int i, ret; 771 772 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 773 ret = icc_set_bw(se->icc_paths[i].path, 774 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); 775 if (ret) { 776 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", 777 icc_path_names[i], ret); 778 return ret; 779 } 780 } 781 782 return 0; 783} 784EXPORT_SYMBOL(geni_icc_set_bw); 785 786void geni_icc_set_tag(struct geni_se *se, u32 tag) 787{ 788 int i; 789 790 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) 791 icc_set_tag(se->icc_paths[i].path, tag); 792} 793EXPORT_SYMBOL(geni_icc_set_tag); 794 795/* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */ 796int geni_icc_enable(struct geni_se *se) 797{ 798 int i, ret; 799 800 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 801 ret = icc_enable(se->icc_paths[i].path); 802 if (ret) { 803 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", 804 icc_path_names[i], ret); 805 return ret; 806 } 807 } 808 809 return 0; 810} 811EXPORT_SYMBOL(geni_icc_enable); 812 813int geni_icc_disable(struct geni_se *se) 814{ 815 int i, ret; 816 817 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { 818 ret = icc_disable(se->icc_paths[i].path); 819 if (ret) { 820 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", 821 icc_path_names[i], ret); 822 return ret; 823 } 824 } 825 826 return 0; 827} 828EXPORT_SYMBOL(geni_icc_disable); 829 830static int geni_se_probe(struct platform_device *pdev) 831{ 832 struct device *dev = &pdev->dev; 833 struct resource *res; 834 struct geni_wrapper *wrapper; 835 int ret; 836 837 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL); 838 if (!wrapper) 839 return -ENOMEM; 840 841 wrapper->dev = dev; 842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 843 wrapper->base = devm_ioremap_resource(dev, res); 844 if (IS_ERR(wrapper->base)) 845 return PTR_ERR(wrapper->base); 846 847 if (!has_acpi_companion(&pdev->dev)) { 848 wrapper->ahb_clks[0].id = "m-ahb"; 849 wrapper->ahb_clks[1].id = "s-ahb"; 850 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); 851 if (ret) { 852 dev_err(dev, "Err getting AHB clks %d\n", ret); 853 return ret; 854 } 855 } 856 857 dev_set_drvdata(dev, wrapper); 858 dev_dbg(dev, "GENI SE Driver probed\n"); 859 return devm_of_platform_populate(dev); 860} 861 862static const struct of_device_id geni_se_dt_match[] = { 863 { .compatible = "qcom,geni-se-qup", }, 864 {} 865}; 866MODULE_DEVICE_TABLE(of, geni_se_dt_match); 867 868static struct platform_driver geni_se_driver = { 869 .driver = { 870 .name = "geni_se_qup", 871 .of_match_table = geni_se_dt_match, 872 }, 873 .probe = geni_se_probe, 874}; 875module_platform_driver(geni_se_driver); 876 877MODULE_DESCRIPTION("GENI Serial Engine Driver"); 878MODULE_LICENSE("GPL v2"); 879