1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2019 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7#include <linux/of_address.h> 8#include <linux/platform_device.h> 9#include <linux/pm_domain.h> 10#include <linux/bitfield.h> 11#include <linux/regmap.h> 12#include <linux/mfd/syscon.h> 13#include <linux/of_device.h> 14#include <linux/reset-controller.h> 15#include <linux/reset.h> 16#include <linux/clk.h> 17#include <dt-bindings/power/meson8-power.h> 18#include <dt-bindings/power/meson-axg-power.h> 19#include <dt-bindings/power/meson-g12a-power.h> 20#include <dt-bindings/power/meson-gxbb-power.h> 21#include <dt-bindings/power/meson-sm1-power.h> 22 23/* AO Offsets */ 24 25#define GX_AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) 26#define GX_AO_RTI_GEN_PWR_ISO0 (0x3b << 2) 27 28/* 29 * Meson8/Meson8b/Meson8m2 only expose the power management registers of the 30 * AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03 31 * and so on. 32 */ 33#define MESON8_AO_RTI_GEN_PWR_SLEEP0 (0x02 << 2) 34#define MESON8_AO_RTI_GEN_PWR_ISO0 (0x03 << 2) 35 36/* HHI Offsets */ 37 38#define HHI_MEM_PD_REG0 (0x40 << 2) 39#define HHI_VPU_MEM_PD_REG0 (0x41 << 2) 40#define HHI_VPU_MEM_PD_REG1 (0x42 << 2) 41#define HHI_VPU_MEM_PD_REG3 (0x43 << 2) 42#define HHI_VPU_MEM_PD_REG4 (0x44 << 2) 43#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2) 44#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2) 45#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) 46#define HHI_VPU_MEM_PD_REG2 (0x4d << 2) 47 48struct meson_ee_pwrc; 49struct meson_ee_pwrc_domain; 50 51struct meson_ee_pwrc_mem_domain { 52 unsigned int reg; 53 unsigned int mask; 54}; 55 56struct meson_ee_pwrc_top_domain { 57 unsigned int sleep_reg; 58 unsigned int sleep_mask; 59 unsigned int iso_reg; 60 unsigned int iso_mask; 61}; 62 63struct meson_ee_pwrc_domain_desc { 64 char *name; 65 unsigned int reset_names_count; 66 unsigned int clk_names_count; 67 struct meson_ee_pwrc_top_domain *top_pd; 68 unsigned int mem_pd_count; 69 struct meson_ee_pwrc_mem_domain *mem_pd; 70 bool (*get_power)(struct meson_ee_pwrc_domain *pwrc_domain); 71}; 72 73struct meson_ee_pwrc_domain_data { 74 unsigned int count; 75 struct meson_ee_pwrc_domain_desc *domains; 76}; 77 78/* TOP Power Domains */ 79 80static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = { 81 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 82 .sleep_mask = BIT(8), 83 .iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 84 .iso_mask = BIT(9), 85}; 86 87static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = { 88 .sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0, 89 .sleep_mask = BIT(8), 90 .iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0, 91 .iso_mask = BIT(9), 92}; 93 94#define SM1_EE_PD(__bit) \ 95 { \ 96 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ 97 .sleep_mask = BIT(__bit), \ 98 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ 99 .iso_mask = BIT(__bit), \ 100 } 101 102static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8); 103static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16); 104static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); 105static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); 106static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); 107 108/* Memory PD Domains */ 109 110#define VPU_MEMPD(__reg) \ 111 { __reg, GENMASK(1, 0) }, \ 112 { __reg, GENMASK(3, 2) }, \ 113 { __reg, GENMASK(5, 4) }, \ 114 { __reg, GENMASK(7, 6) }, \ 115 { __reg, GENMASK(9, 8) }, \ 116 { __reg, GENMASK(11, 10) }, \ 117 { __reg, GENMASK(13, 12) }, \ 118 { __reg, GENMASK(15, 14) }, \ 119 { __reg, GENMASK(17, 16) }, \ 120 { __reg, GENMASK(19, 18) }, \ 121 { __reg, GENMASK(21, 20) }, \ 122 { __reg, GENMASK(23, 22) }, \ 123 { __reg, GENMASK(25, 24) }, \ 124 { __reg, GENMASK(27, 26) }, \ 125 { __reg, GENMASK(29, 28) }, \ 126 { __reg, GENMASK(31, 30) } 127 128#define VPU_HHI_MEMPD(__reg) \ 129 { __reg, BIT(8) }, \ 130 { __reg, BIT(9) }, \ 131 { __reg, BIT(10) }, \ 132 { __reg, BIT(11) }, \ 133 { __reg, BIT(12) }, \ 134 { __reg, BIT(13) }, \ 135 { __reg, BIT(14) }, \ 136 { __reg, BIT(15) } 137 138static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = { 139 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 140 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 141}; 142 143static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = { 144 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 145 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 146 VPU_MEMPD(HHI_VPU_MEM_PD_REG2), 147 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 148}; 149 150static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = { 151 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 152 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 153 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 154}; 155 156static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = { 157 { HHI_MEM_PD_REG0, GENMASK(3, 2) }, 158}; 159 160static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = { 161 { HHI_MEM_PD_REG0, GENMASK(1, 0) }, 162}; 163 164static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = { 165 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 166 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 167 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 168}; 169 170static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = { 171 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 172 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 173 VPU_MEMPD(HHI_VPU_MEM_PD_REG2), 174 VPU_MEMPD(HHI_VPU_MEM_PD_REG3), 175 { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) }, 176 { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) }, 177 { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) }, 178 { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) }, 179 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 180}; 181 182static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = { 183 { HHI_NANOQ_MEM_PD_REG0, 0xff }, 184 { HHI_NANOQ_MEM_PD_REG1, 0xff }, 185}; 186 187static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = { 188 { HHI_MEM_PD_REG0, GENMASK(31, 30) }, 189}; 190 191static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = { 192 { HHI_MEM_PD_REG0, GENMASK(29, 26) }, 193}; 194 195static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = { 196 { HHI_MEM_PD_REG0, GENMASK(25, 18) }, 197}; 198 199static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = { 200 { HHI_MEM_PD_REG0, GENMASK(5, 4) }, 201}; 202 203static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { 204 { HHI_MEM_PD_REG0, GENMASK(5, 4) }, 205 { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) }, 206 { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) }, 207 { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) }, 208 { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) }, 209 { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) }, 210 { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) }, 211 { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) }, 212 { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) }, 213 { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) }, 214 { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) }, 215 { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) }, 216 { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, 217}; 218 219#define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \ 220 { \ 221 .name = __name, \ 222 .reset_names_count = __resets, \ 223 .clk_names_count = __clks, \ 224 .top_pd = __top_pd, \ 225 .mem_pd_count = ARRAY_SIZE(__mem), \ 226 .mem_pd = __mem, \ 227 .get_power = __get_power, \ 228 } 229 230#define TOP_PD(__name, __top_pd, __mem, __get_power) \ 231 { \ 232 .name = __name, \ 233 .top_pd = __top_pd, \ 234 .mem_pd_count = ARRAY_SIZE(__mem), \ 235 .mem_pd = __mem, \ 236 .get_power = __get_power, \ 237 } 238 239#define MEM_PD(__name, __mem) \ 240 TOP_PD(__name, NULL, __mem, NULL) 241 242static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain); 243 244static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = { 245 [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu, 246 pwrc_ee_get_power, 5, 2), 247 [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 248 [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio), 249}; 250 251static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { 252 [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, 253 pwrc_ee_get_power, 11, 2), 254 [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 255}; 256 257static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { 258 [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu, 259 pwrc_ee_get_power, 12, 2), 260 [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 261}; 262 263static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = { 264 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, 265 meson8_pwrc_mem_vpu, pwrc_ee_get_power, 266 0, 1), 267 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", 268 meson_pwrc_mem_eth), 269 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", 270 meson8_pwrc_audio_dsp_mem), 271}; 272 273static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = { 274 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, 275 meson8_pwrc_mem_vpu, pwrc_ee_get_power, 276 11, 1), 277 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", 278 meson_pwrc_mem_eth), 279 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", 280 meson8_pwrc_audio_dsp_mem), 281}; 282 283static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = { 284 [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu, 285 pwrc_ee_get_power, 11, 2), 286 [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna, 287 pwrc_ee_get_power), 288 [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb, 289 pwrc_ee_get_power), 290 [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie, 291 pwrc_ee_get_power), 292 [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d, 293 pwrc_ee_get_power), 294 [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio), 295 [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 296}; 297 298struct meson_ee_pwrc_domain { 299 struct generic_pm_domain base; 300 bool enabled; 301 struct meson_ee_pwrc *pwrc; 302 struct meson_ee_pwrc_domain_desc desc; 303 struct clk_bulk_data *clks; 304 int num_clks; 305 struct reset_control *rstc; 306 int num_rstc; 307}; 308 309struct meson_ee_pwrc { 310 struct regmap *regmap_ao; 311 struct regmap *regmap_hhi; 312 struct meson_ee_pwrc_domain *domains; 313 struct genpd_onecell_data xlate; 314}; 315 316static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain) 317{ 318 u32 reg; 319 320 regmap_read(pwrc_domain->pwrc->regmap_ao, 321 pwrc_domain->desc.top_pd->sleep_reg, ®); 322 323 return (reg & pwrc_domain->desc.top_pd->sleep_mask); 324} 325 326static int meson_ee_pwrc_off(struct generic_pm_domain *domain) 327{ 328 struct meson_ee_pwrc_domain *pwrc_domain = 329 container_of(domain, struct meson_ee_pwrc_domain, base); 330 int i; 331 332 if (pwrc_domain->desc.top_pd) 333 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 334 pwrc_domain->desc.top_pd->sleep_reg, 335 pwrc_domain->desc.top_pd->sleep_mask, 336 pwrc_domain->desc.top_pd->sleep_mask); 337 udelay(20); 338 339 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) 340 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, 341 pwrc_domain->desc.mem_pd[i].reg, 342 pwrc_domain->desc.mem_pd[i].mask, 343 pwrc_domain->desc.mem_pd[i].mask); 344 345 udelay(20); 346 347 if (pwrc_domain->desc.top_pd) 348 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 349 pwrc_domain->desc.top_pd->iso_reg, 350 pwrc_domain->desc.top_pd->iso_mask, 351 pwrc_domain->desc.top_pd->iso_mask); 352 353 if (pwrc_domain->num_clks) { 354 msleep(20); 355 clk_bulk_disable_unprepare(pwrc_domain->num_clks, 356 pwrc_domain->clks); 357 } 358 359 return 0; 360} 361 362static int meson_ee_pwrc_on(struct generic_pm_domain *domain) 363{ 364 struct meson_ee_pwrc_domain *pwrc_domain = 365 container_of(domain, struct meson_ee_pwrc_domain, base); 366 int i, ret; 367 368 if (pwrc_domain->desc.top_pd) 369 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 370 pwrc_domain->desc.top_pd->sleep_reg, 371 pwrc_domain->desc.top_pd->sleep_mask, 0); 372 udelay(20); 373 374 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) 375 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, 376 pwrc_domain->desc.mem_pd[i].reg, 377 pwrc_domain->desc.mem_pd[i].mask, 0); 378 379 udelay(20); 380 381 ret = reset_control_assert(pwrc_domain->rstc); 382 if (ret) 383 return ret; 384 385 if (pwrc_domain->desc.top_pd) 386 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 387 pwrc_domain->desc.top_pd->iso_reg, 388 pwrc_domain->desc.top_pd->iso_mask, 0); 389 390 ret = reset_control_deassert(pwrc_domain->rstc); 391 if (ret) 392 return ret; 393 394 return clk_bulk_prepare_enable(pwrc_domain->num_clks, 395 pwrc_domain->clks); 396} 397 398static int meson_ee_pwrc_init_domain(struct platform_device *pdev, 399 struct meson_ee_pwrc *pwrc, 400 struct meson_ee_pwrc_domain *dom) 401{ 402 int ret; 403 404 dom->pwrc = pwrc; 405 dom->num_rstc = dom->desc.reset_names_count; 406 dom->num_clks = dom->desc.clk_names_count; 407 408 if (dom->num_rstc) { 409 int count = reset_control_get_count(&pdev->dev); 410 411 if (count != dom->num_rstc) 412 dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n", 413 count, dom->desc.name); 414 415 dom->rstc = devm_reset_control_array_get(&pdev->dev, false, 416 false); 417 if (IS_ERR(dom->rstc)) 418 return PTR_ERR(dom->rstc); 419 } 420 421 if (dom->num_clks) { 422 int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks); 423 if (ret < 0) 424 return ret; 425 426 if (dom->num_clks != ret) { 427 dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n", 428 ret, dom->desc.name); 429 dom->num_clks = ret; 430 } 431 } 432 433 dom->base.name = dom->desc.name; 434 dom->base.power_on = meson_ee_pwrc_on; 435 dom->base.power_off = meson_ee_pwrc_off; 436 437 /* 438 * TOFIX: This is a special case for the VPU power domain, which can 439 * be enabled previously by the bootloader. In this case the VPU 440 * pipeline may be functional but no driver maybe never attach 441 * to this power domain, and if the domain is disabled it could 442 * cause system errors. This is why the pm_domain_always_on_gov 443 * is used here. 444 * For the same reason, the clocks should be enabled in case 445 * we need to power the domain off, otherwise the internal clocks 446 * prepare/enable counters won't be in sync. 447 */ 448 if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) { 449 ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks); 450 if (ret) 451 return ret; 452 453 dom->base.flags = GENPD_FLAG_ALWAYS_ON; 454 ret = pm_genpd_init(&dom->base, NULL, false); 455 if (ret) 456 return ret; 457 } else { 458 ret = pm_genpd_init(&dom->base, NULL, 459 (dom->desc.get_power ? 460 dom->desc.get_power(dom) : true)); 461 if (ret) 462 return ret; 463 } 464 465 return 0; 466} 467 468static int meson_ee_pwrc_probe(struct platform_device *pdev) 469{ 470 const struct meson_ee_pwrc_domain_data *match; 471 struct regmap *regmap_ao, *regmap_hhi; 472 struct meson_ee_pwrc *pwrc; 473 int i, ret; 474 475 match = of_device_get_match_data(&pdev->dev); 476 if (!match) { 477 dev_err(&pdev->dev, "failed to get match data\n"); 478 return -ENODEV; 479 } 480 481 pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL); 482 if (!pwrc) 483 return -ENOMEM; 484 485 pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count, 486 sizeof(*pwrc->xlate.domains), 487 GFP_KERNEL); 488 if (!pwrc->xlate.domains) 489 return -ENOMEM; 490 491 pwrc->domains = devm_kcalloc(&pdev->dev, match->count, 492 sizeof(*pwrc->domains), GFP_KERNEL); 493 if (!pwrc->domains) 494 return -ENOMEM; 495 496 pwrc->xlate.num_domains = match->count; 497 498 regmap_hhi = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node)); 499 if (IS_ERR(regmap_hhi)) { 500 dev_err(&pdev->dev, "failed to get HHI regmap\n"); 501 return PTR_ERR(regmap_hhi); 502 } 503 504 regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 505 "amlogic,ao-sysctrl"); 506 if (IS_ERR(regmap_ao)) { 507 dev_err(&pdev->dev, "failed to get AO regmap\n"); 508 return PTR_ERR(regmap_ao); 509 } 510 511 pwrc->regmap_ao = regmap_ao; 512 pwrc->regmap_hhi = regmap_hhi; 513 514 platform_set_drvdata(pdev, pwrc); 515 516 for (i = 0 ; i < match->count ; ++i) { 517 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i]; 518 519 memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc)); 520 521 ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom); 522 if (ret) 523 return ret; 524 525 pwrc->xlate.domains[i] = &dom->base; 526 } 527 528 return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); 529} 530 531static void meson_ee_pwrc_shutdown(struct platform_device *pdev) 532{ 533 struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev); 534 int i; 535 536 for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) { 537 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i]; 538 539 if (dom->desc.get_power && !dom->desc.get_power(dom)) 540 meson_ee_pwrc_off(&dom->base); 541 } 542} 543 544static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = { 545 .count = ARRAY_SIZE(g12a_pwrc_domains), 546 .domains = g12a_pwrc_domains, 547}; 548 549static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = { 550 .count = ARRAY_SIZE(axg_pwrc_domains), 551 .domains = axg_pwrc_domains, 552}; 553 554static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = { 555 .count = ARRAY_SIZE(gxbb_pwrc_domains), 556 .domains = gxbb_pwrc_domains, 557}; 558 559static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = { 560 .count = ARRAY_SIZE(meson8_pwrc_domains), 561 .domains = meson8_pwrc_domains, 562}; 563 564static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = { 565 .count = ARRAY_SIZE(meson8b_pwrc_domains), 566 .domains = meson8b_pwrc_domains, 567}; 568 569static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = { 570 .count = ARRAY_SIZE(sm1_pwrc_domains), 571 .domains = sm1_pwrc_domains, 572}; 573 574static const struct of_device_id meson_ee_pwrc_match_table[] = { 575 { 576 .compatible = "amlogic,meson8-pwrc", 577 .data = &meson_ee_m8_pwrc_data, 578 }, 579 { 580 .compatible = "amlogic,meson8b-pwrc", 581 .data = &meson_ee_m8b_pwrc_data, 582 }, 583 { 584 .compatible = "amlogic,meson8m2-pwrc", 585 .data = &meson_ee_m8b_pwrc_data, 586 }, 587 { 588 .compatible = "amlogic,meson-axg-pwrc", 589 .data = &meson_ee_axg_pwrc_data, 590 }, 591 { 592 .compatible = "amlogic,meson-gxbb-pwrc", 593 .data = &meson_ee_gxbb_pwrc_data, 594 }, 595 { 596 .compatible = "amlogic,meson-g12a-pwrc", 597 .data = &meson_ee_g12a_pwrc_data, 598 }, 599 { 600 .compatible = "amlogic,meson-sm1-pwrc", 601 .data = &meson_ee_sm1_pwrc_data, 602 }, 603 { /* sentinel */ } 604}; 605 606static struct platform_driver meson_ee_pwrc_driver = { 607 .probe = meson_ee_pwrc_probe, 608 .shutdown = meson_ee_pwrc_shutdown, 609 .driver = { 610 .name = "meson_ee_pwrc", 611 .of_match_table = meson_ee_pwrc_match_table, 612 }, 613}; 614builtin_platform_driver(meson_ee_pwrc_driver); 615