18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * UFS Host driver for Synopsys Designware Core 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Authors: Joao Pinto <jpinto@synopsys.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef _UFSHCI_DWC_H 118c2ecf20Sopenharmony_ci#define _UFSHCI_DWC_H 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci/* DWC HC UFSHCI specific Registers */ 148c2ecf20Sopenharmony_cienum dwc_specific_registers { 158c2ecf20Sopenharmony_ci DWC_UFS_REG_HCLKDIV = 0xFC, 168c2ecf20Sopenharmony_ci}; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* Clock Divider Values: Hex equivalent of frequency in MHz */ 198c2ecf20Sopenharmony_cienum clk_div_values { 208c2ecf20Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, 218c2ecf20Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, 228c2ecf20Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, 238c2ecf20Sopenharmony_ci}; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci/* Selector Index */ 268c2ecf20Sopenharmony_cienum selector_index { 278c2ecf20Sopenharmony_ci SELIND_LN0_TX = 0x00, 288c2ecf20Sopenharmony_ci SELIND_LN1_TX = 0x01, 298c2ecf20Sopenharmony_ci SELIND_LN0_RX = 0x04, 308c2ecf20Sopenharmony_ci SELIND_LN1_RX = 0x05, 318c2ecf20Sopenharmony_ci}; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci#endif /* End of Header */ 34