1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * UFS Host Controller driver for Exynos specific extensions 4 * 5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#ifndef _UFS_EXYNOS_H_ 10#define _UFS_EXYNOS_H_ 11 12/* 13 * UNIPRO registers 14 */ 15#define UNIPRO_DBG_FORCE_DME_CTRL_STATE 0x150 16 17/* 18 * MIBs for PA debug registers 19 */ 20#define PA_DBG_CLK_PERIOD 0x9514 21#define PA_DBG_TXPHY_CFGUPDT 0x9518 22#define PA_DBG_RXPHY_CFGUPDT 0x9519 23#define PA_DBG_MODE 0x9529 24#define PA_DBG_SKIP_RESET_PHY 0x9539 25#define PA_DBG_OV_TM 0x9540 26#define PA_DBG_SKIP_LINE_RESET 0x9541 27#define PA_DBG_LINE_RESET_REQ 0x9543 28#define PA_DBG_OPTION_SUITE 0x9564 29#define PA_DBG_OPTION_SUITE_DYN 0x9565 30 31/* 32 * MIBs for Transport Layer debug registers 33 */ 34#define T_DBG_SKIP_INIT_HIBERN8_EXIT 0xc001 35 36/* 37 * Exynos MPHY attributes 38 */ 39#define TX_LINERESET_N_VAL 0x0277 40#define TX_LINERESET_N(v) (((v) >> 10) & 0xFF) 41#define TX_LINERESET_P_VAL 0x027D 42#define TX_LINERESET_P(v) (((v) >> 12) & 0xFF) 43#define TX_OV_SLEEP_CNT_TIMER 0x028E 44#define TX_OV_H8_ENTER_EN (1 << 7) 45#define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F) 46#define TX_HIGH_Z_CNT_11_08 0x028C 47#define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF) 48#define TX_HIGH_Z_CNT_07_00 0x028D 49#define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF) 50#define TX_BASE_NVAL_07_00 0x0293 51#define TX_BASE_NVAL_L(v) ((v) & 0xFF) 52#define TX_BASE_NVAL_15_08 0x0294 53#define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF) 54#define TX_GRAN_NVAL_07_00 0x0295 55#define TX_GRAN_NVAL_L(v) ((v) & 0xFF) 56#define TX_GRAN_NVAL_10_08 0x0296 57#define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3) 58 59#define RX_FILLER_ENABLE 0x0316 60#define RX_FILLER_EN (1 << 1) 61#define RX_LINERESET_VAL 0x0317 62#define RX_LINERESET(v) (((v) >> 12) & 0xFF) 63#define RX_LCC_IGNORE 0x0318 64#define RX_SYNC_MASK_LENGTH 0x0321 65#define RX_HIBERN8_WAIT_VAL_BIT_20_16 0x0331 66#define RX_HIBERN8_WAIT_VAL_BIT_15_08 0x0332 67#define RX_HIBERN8_WAIT_VAL_BIT_07_00 0x0333 68#define RX_OV_SLEEP_CNT_TIMER 0x0340 69#define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F) 70#define RX_OV_STALL_CNT_TIMER 0x0341 71#define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF) 72#define RX_BASE_NVAL_07_00 0x0355 73#define RX_BASE_NVAL_L(v) ((v) & 0xFF) 74#define RX_BASE_NVAL_15_08 0x0354 75#define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF) 76#define RX_GRAN_NVAL_07_00 0x0353 77#define RX_GRAN_NVAL_L(v) ((v) & 0xFF) 78#define RX_GRAN_NVAL_10_08 0x0352 79#define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3) 80 81#define CMN_PWM_CLK_CTRL 0x0402 82#define PWM_CLK_CTRL_MASK 0x3 83 84#define IATOVAL_NSEC 20000 /* unit: ns */ 85#define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate) 86 87struct exynos_ufs; 88 89/* vendor specific pre-defined parameters */ 90#define SLOW 1 91#define FAST 2 92 93#define UFS_EXYNOS_LIMIT_NUM_LANES_RX 2 94#define UFS_EXYNOS_LIMIT_NUM_LANES_TX 2 95#define UFS_EXYNOS_LIMIT_HSGEAR_RX UFS_HS_G3 96#define UFS_EXYNOS_LIMIT_HSGEAR_TX UFS_HS_G3 97#define UFS_EXYNOS_LIMIT_PWMGEAR_RX UFS_PWM_G4 98#define UFS_EXYNOS_LIMIT_PWMGEAR_TX UFS_PWM_G4 99#define UFS_EXYNOS_LIMIT_RX_PWR_PWM SLOW_MODE 100#define UFS_EXYNOS_LIMIT_TX_PWR_PWM SLOW_MODE 101#define UFS_EXYNOS_LIMIT_RX_PWR_HS FAST_MODE 102#define UFS_EXYNOS_LIMIT_TX_PWR_HS FAST_MODE 103#define UFS_EXYNOS_LIMIT_HS_RATE PA_HS_MODE_B 104#define UFS_EXYNOS_LIMIT_DESIRED_MODE FAST 105 106#define RX_ADV_FINE_GRAN_SUP_EN 0x1 107#define RX_ADV_FINE_GRAN_STEP_VAL 0x3 108#define RX_ADV_MIN_ACTV_TIME_CAP 0x9 109 110#define PA_GRANULARITY_VAL 0x6 111#define PA_TACTIVATE_VAL 0x3 112#define PA_HIBERN8TIME_VAL 0x20 113 114#define PCLK_AVAIL_MIN 70000000 115#define PCLK_AVAIL_MAX 133000000 116 117struct exynos_ufs_uic_attr { 118 /* TX Attributes */ 119 unsigned int tx_trailingclks; 120 unsigned int tx_dif_p_nsec; 121 unsigned int tx_dif_n_nsec; 122 unsigned int tx_high_z_cnt_nsec; 123 unsigned int tx_base_unit_nsec; 124 unsigned int tx_gran_unit_nsec; 125 unsigned int tx_sleep_cnt; 126 unsigned int tx_min_activatetime; 127 /* RX Attributes */ 128 unsigned int rx_filler_enable; 129 unsigned int rx_dif_p_nsec; 130 unsigned int rx_hibern8_wait_nsec; 131 unsigned int rx_base_unit_nsec; 132 unsigned int rx_gran_unit_nsec; 133 unsigned int rx_sleep_cnt; 134 unsigned int rx_stall_cnt; 135 unsigned int rx_hs_g1_sync_len_cap; 136 unsigned int rx_hs_g2_sync_len_cap; 137 unsigned int rx_hs_g3_sync_len_cap; 138 unsigned int rx_hs_g1_prep_sync_len_cap; 139 unsigned int rx_hs_g2_prep_sync_len_cap; 140 unsigned int rx_hs_g3_prep_sync_len_cap; 141 /* Common Attributes */ 142 unsigned int cmn_pwm_clk_ctrl; 143 /* Internal Attributes */ 144 unsigned int pa_dbg_option_suite; 145 /* Changeable Attributes */ 146 unsigned int rx_adv_fine_gran_sup_en; 147 unsigned int rx_adv_fine_gran_step; 148 unsigned int rx_min_actv_time_cap; 149 unsigned int rx_hibern8_time_cap; 150 unsigned int rx_adv_min_actv_time_cap; 151 unsigned int rx_adv_hibern8_time_cap; 152 unsigned int pa_granularity; 153 unsigned int pa_tactivate; 154 unsigned int pa_hibern8time; 155}; 156 157struct exynos_ufs_drv_data { 158 char *compatible; 159 struct exynos_ufs_uic_attr *uic_attr; 160 unsigned int quirks; 161 unsigned int opts; 162 /* SoC's specific operations */ 163 int (*drv_init)(struct device *dev, struct exynos_ufs *ufs); 164 int (*pre_link)(struct exynos_ufs *ufs); 165 int (*post_link)(struct exynos_ufs *ufs); 166 int (*pre_pwr_change)(struct exynos_ufs *ufs, 167 struct ufs_pa_layer_attr *pwr); 168 int (*post_pwr_change)(struct exynos_ufs *ufs, 169 struct ufs_pa_layer_attr *pwr); 170}; 171 172struct ufs_phy_time_cfg { 173 u32 tx_linereset_p; 174 u32 tx_linereset_n; 175 u32 tx_high_z_cnt; 176 u32 tx_base_n_val; 177 u32 tx_gran_n_val; 178 u32 tx_sleep_cnt; 179 u32 rx_linereset; 180 u32 rx_hibern8_wait; 181 u32 rx_base_n_val; 182 u32 rx_gran_n_val; 183 u32 rx_sleep_cnt; 184 u32 rx_stall_cnt; 185}; 186 187struct exynos_ufs { 188 struct ufs_hba *hba; 189 struct phy *phy; 190 void __iomem *reg_hci; 191 void __iomem *reg_unipro; 192 void __iomem *reg_ufsp; 193 struct clk *clk_hci_core; 194 struct clk *clk_unipro_main; 195 struct clk *clk_apb; 196 u32 pclk_rate; 197 u32 pclk_div; 198 u32 pclk_avail_min; 199 u32 pclk_avail_max; 200 unsigned long mclk_rate; 201 int avail_ln_rx; 202 int avail_ln_tx; 203 int rx_sel_idx; 204 struct ufs_pa_layer_attr dev_req_params; 205 struct ufs_phy_time_cfg t_cfg; 206 ktime_t entry_hibern8_t; 207 struct exynos_ufs_drv_data *drv_data; 208 209 u32 opts; 210#define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0) 211#define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1) 212#define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2) 213#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) 214#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) 215}; 216 217#define for_each_ufs_rx_lane(ufs, i) \ 218 for (i = (ufs)->rx_sel_idx; \ 219 i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++) 220#define for_each_ufs_tx_lane(ufs, i) \ 221 for (i = 0; i < (ufs)->avail_ln_tx; i++) 222 223#define EXYNOS_UFS_MMIO_FUNC(name) \ 224static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\ 225{ \ 226 writel(val, ufs->reg_##name + reg); \ 227} \ 228 \ 229static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg) \ 230{ \ 231 return readl(ufs->reg_##name + reg); \ 232} 233 234EXYNOS_UFS_MMIO_FUNC(hci); 235EXYNOS_UFS_MMIO_FUNC(unipro); 236EXYNOS_UFS_MMIO_FUNC(ufsp); 237#undef EXYNOS_UFS_MMIO_FUNC 238 239long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long); 240 241static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba) 242{ 243 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), TRUE); 244} 245 246static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba) 247{ 248 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), FALSE); 249} 250 251static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba) 252{ 253 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), TRUE); 254} 255 256static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba) 257{ 258 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), FALSE); 259} 260 261struct exynos_ufs_drv_data exynos_ufs_drvs; 262 263struct exynos_ufs_uic_attr exynos7_uic_attr = { 264 .tx_trailingclks = 0x10, 265 .tx_dif_p_nsec = 3000000, /* unit: ns */ 266 .tx_dif_n_nsec = 1000000, /* unit: ns */ 267 .tx_high_z_cnt_nsec = 20000, /* unit: ns */ 268 .tx_base_unit_nsec = 100000, /* unit: ns */ 269 .tx_gran_unit_nsec = 4000, /* unit: ns */ 270 .tx_sleep_cnt = 1000, /* unit: ns */ 271 .tx_min_activatetime = 0xa, 272 .rx_filler_enable = 0x2, 273 .rx_dif_p_nsec = 1000000, /* unit: ns */ 274 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ 275 .rx_base_unit_nsec = 100000, /* unit: ns */ 276 .rx_gran_unit_nsec = 4000, /* unit: ns */ 277 .rx_sleep_cnt = 1280, /* unit: ns */ 278 .rx_stall_cnt = 320, /* unit: ns */ 279 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), 280 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), 281 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), 282 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), 283 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), 284 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), 285 .pa_dbg_option_suite = 0x30103, 286}; 287#endif /* _UFS_EXYNOS_H_ */ 288