1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6#include "qla_def.h" 7 8#include <linux/moduleparam.h> 9#include <linux/vmalloc.h> 10#include <linux/delay.h> 11#include <linux/kthread.h> 12#include <linux/mutex.h> 13#include <linux/kobject.h> 14#include <linux/slab.h> 15#include <linux/blk-mq-pci.h> 16#include <linux/refcount.h> 17#include <linux/crash_dump.h> 18 19#include <scsi/scsi_tcq.h> 20#include <scsi/scsicam.h> 21#include <scsi/scsi_transport.h> 22#include <scsi/scsi_transport_fc.h> 23 24#include "qla_target.h" 25 26/* 27 * Driver version 28 */ 29char qla2x00_version_str[40]; 30 31static int apidev_major; 32 33/* 34 * SRB allocation cache 35 */ 36struct kmem_cache *srb_cachep; 37 38int ql2xfulldump_on_mpifail; 39module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 40MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 41 "Set this to take full dump on MPI hang."); 42 43int ql2xenforce_iocb_limit = 1; 44module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 45MODULE_PARM_DESC(ql2xenforce_iocb_limit, 46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 47 48/* 49 * CT6 CTX allocation cache 50 */ 51static struct kmem_cache *ctx_cachep; 52/* 53 * error level for logging 54 */ 55uint ql_errlev = 0x8001; 56 57static int ql2xenableclass2; 58module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 59MODULE_PARM_DESC(ql2xenableclass2, 60 "Specify if Class 2 operations are supported from the very " 61 "beginning. Default is 0 - class 2 not supported."); 62 63 64int ql2xlogintimeout = 20; 65module_param(ql2xlogintimeout, int, S_IRUGO); 66MODULE_PARM_DESC(ql2xlogintimeout, 67 "Login timeout value in seconds."); 68 69int qlport_down_retry; 70module_param(qlport_down_retry, int, S_IRUGO); 71MODULE_PARM_DESC(qlport_down_retry, 72 "Maximum number of command retries to a port that returns " 73 "a PORT-DOWN status."); 74 75int ql2xplogiabsentdevice; 76module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 77MODULE_PARM_DESC(ql2xplogiabsentdevice, 78 "Option to enable PLOGI to devices that are not present after " 79 "a Fabric scan. This is needed for several broken switches. " 80 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 81 82int ql2xloginretrycount; 83module_param(ql2xloginretrycount, int, S_IRUGO); 84MODULE_PARM_DESC(ql2xloginretrycount, 85 "Specify an alternate value for the NVRAM login retry count."); 86 87int ql2xallocfwdump = 1; 88module_param(ql2xallocfwdump, int, S_IRUGO); 89MODULE_PARM_DESC(ql2xallocfwdump, 90 "Option to enable allocation of memory for a firmware dump " 91 "during HBA initialization. Memory allocation requirements " 92 "vary by ISP type. Default is 1 - allocate memory."); 93 94int ql2xextended_error_logging; 95module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 96module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 97MODULE_PARM_DESC(ql2xextended_error_logging, 98 "Option to enable extended error logging,\n" 99 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 100 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 101 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 102 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 103 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 104 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 105 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 106 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 107 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 108 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 109 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 110 "\t\t0x1e400000 - Preferred value for capturing essential " 111 "debug information (equivalent to old " 112 "ql2xextended_error_logging=1).\n" 113 "\t\tDo LOGICAL OR of the value to enable more than one level"); 114 115int ql2xshiftctondsd = 6; 116module_param(ql2xshiftctondsd, int, S_IRUGO); 117MODULE_PARM_DESC(ql2xshiftctondsd, 118 "Set to control shifting of command type processing " 119 "based on total number of SG elements."); 120 121int ql2xfdmienable = 1; 122module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 123module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 124MODULE_PARM_DESC(ql2xfdmienable, 125 "Enables FDMI registrations. " 126 "0 - no FDMI registrations. " 127 "1 - provide FDMI registrations (default)."); 128 129#define MAX_Q_DEPTH 64 130static int ql2xmaxqdepth = MAX_Q_DEPTH; 131module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 132MODULE_PARM_DESC(ql2xmaxqdepth, 133 "Maximum queue depth to set for each LUN. " 134 "Default is 64."); 135 136int ql2xenabledif = 2; 137module_param(ql2xenabledif, int, S_IRUGO); 138MODULE_PARM_DESC(ql2xenabledif, 139 " Enable T10-CRC-DIF:\n" 140 " Default is 2.\n" 141 " 0 -- No DIF Support\n" 142 " 1 -- Enable DIF for all types\n" 143 " 2 -- Enable DIF for all types, except Type 0.\n"); 144 145#if (IS_ENABLED(CONFIG_NVME_FC)) 146int ql2xnvmeenable = 1; 147#else 148int ql2xnvmeenable; 149#endif 150module_param(ql2xnvmeenable, int, 0644); 151MODULE_PARM_DESC(ql2xnvmeenable, 152 "Enables NVME support. " 153 "0 - no NVMe. Default is Y"); 154 155int ql2xenablehba_err_chk = 2; 156module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 157MODULE_PARM_DESC(ql2xenablehba_err_chk, 158 " Enable T10-CRC-DIF Error isolation by HBA:\n" 159 " Default is 2.\n" 160 " 0 -- Error isolation disabled\n" 161 " 1 -- Error isolation enabled only for DIX Type 0\n" 162 " 2 -- Error isolation enabled for all Types\n"); 163 164int ql2xiidmaenable = 1; 165module_param(ql2xiidmaenable, int, S_IRUGO); 166MODULE_PARM_DESC(ql2xiidmaenable, 167 "Enables iIDMA settings " 168 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 169 170int ql2xmqsupport = 1; 171module_param(ql2xmqsupport, int, S_IRUGO); 172MODULE_PARM_DESC(ql2xmqsupport, 173 "Enable on demand multiple queue pairs support " 174 "Default is 1 for supported. " 175 "Set it to 0 to turn off mq qpair support."); 176 177int ql2xfwloadbin; 178module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 179module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 180MODULE_PARM_DESC(ql2xfwloadbin, 181 "Option to specify location from which to load ISP firmware:.\n" 182 " 2 -- load firmware via the request_firmware() (hotplug).\n" 183 " interface.\n" 184 " 1 -- load firmware from flash.\n" 185 " 0 -- use default semantics.\n"); 186 187int ql2xetsenable; 188module_param(ql2xetsenable, int, S_IRUGO); 189MODULE_PARM_DESC(ql2xetsenable, 190 "Enables firmware ETS burst." 191 "Default is 0 - skip ETS enablement."); 192 193int ql2xdbwr = 1; 194module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 195MODULE_PARM_DESC(ql2xdbwr, 196 "Option to specify scheme for request queue posting.\n" 197 " 0 -- Regular doorbell.\n" 198 " 1 -- CAMRAM doorbell (faster).\n"); 199 200int ql2xgffidenable; 201module_param(ql2xgffidenable, int, S_IRUGO); 202MODULE_PARM_DESC(ql2xgffidenable, 203 "Enables GFF_ID checks of port type. " 204 "Default is 0 - Do not use GFF_ID information."); 205 206int ql2xasynctmfenable = 1; 207module_param(ql2xasynctmfenable, int, S_IRUGO); 208MODULE_PARM_DESC(ql2xasynctmfenable, 209 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 210 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 211 212int ql2xdontresethba; 213module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 214MODULE_PARM_DESC(ql2xdontresethba, 215 "Option to specify reset behaviour.\n" 216 " 0 (Default) -- Reset on failure.\n" 217 " 1 -- Do not reset on failure.\n"); 218 219uint64_t ql2xmaxlun = MAX_LUNS; 220module_param(ql2xmaxlun, ullong, S_IRUGO); 221MODULE_PARM_DESC(ql2xmaxlun, 222 "Defines the maximum LU number to register with the SCSI " 223 "midlayer. Default is 65535."); 224 225int ql2xmdcapmask = 0x1F; 226module_param(ql2xmdcapmask, int, S_IRUGO); 227MODULE_PARM_DESC(ql2xmdcapmask, 228 "Set the Minidump driver capture mask level. " 229 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 230 231int ql2xmdenable = 1; 232module_param(ql2xmdenable, int, S_IRUGO); 233MODULE_PARM_DESC(ql2xmdenable, 234 "Enable/disable MiniDump. " 235 "0 - MiniDump disabled. " 236 "1 (Default) - MiniDump enabled."); 237 238int ql2xexlogins; 239module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 240MODULE_PARM_DESC(ql2xexlogins, 241 "Number of extended Logins. " 242 "0 (Default)- Disabled."); 243 244int ql2xexchoffld = 1024; 245module_param(ql2xexchoffld, uint, 0644); 246MODULE_PARM_DESC(ql2xexchoffld, 247 "Number of target exchanges."); 248 249int ql2xiniexchg = 1024; 250module_param(ql2xiniexchg, uint, 0644); 251MODULE_PARM_DESC(ql2xiniexchg, 252 "Number of initiator exchanges."); 253 254int ql2xfwholdabts; 255module_param(ql2xfwholdabts, int, S_IRUGO); 256MODULE_PARM_DESC(ql2xfwholdabts, 257 "Allow FW to hold status IOCB until ABTS rsp received. " 258 "0 (Default) Do not set fw option. " 259 "1 - Set fw option to hold ABTS."); 260 261int ql2xmvasynctoatio = 1; 262module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 263MODULE_PARM_DESC(ql2xmvasynctoatio, 264 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 265 "0 (Default). Do not move IOCBs" 266 "1 - Move IOCBs."); 267 268int ql2xautodetectsfp = 1; 269module_param(ql2xautodetectsfp, int, 0444); 270MODULE_PARM_DESC(ql2xautodetectsfp, 271 "Detect SFP range and set appropriate distance.\n" 272 "1 (Default): Enable\n"); 273 274int ql2xenablemsix = 1; 275module_param(ql2xenablemsix, int, 0444); 276MODULE_PARM_DESC(ql2xenablemsix, 277 "Set to enable MSI or MSI-X interrupt mechanism.\n" 278 " Default is 1, enable MSI-X interrupt mechanism.\n" 279 " 0 -- enable traditional pin-based mechanism.\n" 280 " 1 -- enable MSI-X interrupt mechanism.\n" 281 " 2 -- enable MSI interrupt mechanism.\n"); 282 283int qla2xuseresexchforels; 284module_param(qla2xuseresexchforels, int, 0444); 285MODULE_PARM_DESC(qla2xuseresexchforels, 286 "Reserve 1/2 of emergency exchanges for ELS.\n" 287 " 0 (default): disabled"); 288 289static int ql2xprotmask; 290module_param(ql2xprotmask, int, 0644); 291MODULE_PARM_DESC(ql2xprotmask, 292 "Override DIF/DIX protection capabilities mask\n" 293 "Default is 0 which sets protection mask based on " 294 "capabilities reported by HBA firmware.\n"); 295 296static int ql2xprotguard; 297module_param(ql2xprotguard, int, 0644); 298MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 299 " 0 -- Let HBA firmware decide\n" 300 " 1 -- Force T10 CRC\n" 301 " 2 -- Force IP checksum\n"); 302 303int ql2xdifbundlinginternalbuffers; 304module_param(ql2xdifbundlinginternalbuffers, int, 0644); 305MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 306 "Force using internal buffers for DIF information\n" 307 "0 (Default). Based on check.\n" 308 "1 Force using internal buffers\n"); 309 310int ql2xsmartsan; 311module_param(ql2xsmartsan, int, 0444); 312module_param_named(smartsan, ql2xsmartsan, int, 0444); 313MODULE_PARM_DESC(ql2xsmartsan, 314 "Send SmartSAN Management Attributes for FDMI Registration." 315 " Default is 0 - No SmartSAN registration," 316 " 1 - Register SmartSAN Management Attributes."); 317 318int ql2xrdpenable; 319module_param(ql2xrdpenable, int, 0444); 320module_param_named(rdpenable, ql2xrdpenable, int, 0444); 321MODULE_PARM_DESC(ql2xrdpenable, 322 "Enables RDP responses. " 323 "0 - no RDP responses (default). " 324 "1 - provide RDP responses."); 325 326static void qla2x00_clear_drv_active(struct qla_hw_data *); 327static void qla2x00_free_device(scsi_qla_host_t *); 328static int qla2xxx_map_queues(struct Scsi_Host *shost); 329static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 330 331 332static struct scsi_transport_template *qla2xxx_transport_template = NULL; 333struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 334 335/* TODO Convert to inlines 336 * 337 * Timer routines 338 */ 339 340__inline__ void 341qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 342{ 343 timer_setup(&vha->timer, qla2x00_timer, 0); 344 vha->timer.expires = jiffies + interval * HZ; 345 add_timer(&vha->timer); 346 vha->timer_active = 1; 347} 348 349static inline void 350qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 351{ 352 /* Currently used for 82XX only. */ 353 if (vha->device_flags & DFLG_DEV_FAILED) { 354 ql_dbg(ql_dbg_timer, vha, 0x600d, 355 "Device in a failed state, returning.\n"); 356 return; 357 } 358 359 mod_timer(&vha->timer, jiffies + interval * HZ); 360} 361 362static __inline__ void 363qla2x00_stop_timer(scsi_qla_host_t *vha) 364{ 365 del_timer_sync(&vha->timer); 366 vha->timer_active = 0; 367} 368 369static int qla2x00_do_dpc(void *data); 370 371static void qla2x00_rst_aen(scsi_qla_host_t *); 372 373static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 374 struct req_que **, struct rsp_que **); 375static void qla2x00_free_fw_dump(struct qla_hw_data *); 376static void qla2x00_mem_free(struct qla_hw_data *); 377int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 378 struct qla_qpair *qpair); 379 380/* -------------------------------------------------------------------------- */ 381static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 382 struct rsp_que *rsp) 383{ 384 struct qla_hw_data *ha = vha->hw; 385 386 rsp->qpair = ha->base_qpair; 387 rsp->req = req; 388 ha->base_qpair->hw = ha; 389 ha->base_qpair->req = req; 390 ha->base_qpair->rsp = rsp; 391 ha->base_qpair->vha = vha; 392 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 393 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 394 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 395 ha->base_qpair->srb_mempool = ha->srb_mempool; 396 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 397 ha->base_qpair->enable_class_2 = ql2xenableclass2; 398 /* init qpair to this cpu. Will adjust at run time. */ 399 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 400 ha->base_qpair->pdev = ha->pdev; 401 402 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 403 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 404} 405 406static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 407 struct rsp_que *rsp) 408{ 409 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 410 411 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 412 GFP_KERNEL); 413 if (!ha->req_q_map) { 414 ql_log(ql_log_fatal, vha, 0x003b, 415 "Unable to allocate memory for request queue ptrs.\n"); 416 goto fail_req_map; 417 } 418 419 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 420 GFP_KERNEL); 421 if (!ha->rsp_q_map) { 422 ql_log(ql_log_fatal, vha, 0x003c, 423 "Unable to allocate memory for response queue ptrs.\n"); 424 goto fail_rsp_map; 425 } 426 427 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 428 if (ha->base_qpair == NULL) { 429 ql_log(ql_log_warn, vha, 0x00e0, 430 "Failed to allocate base queue pair memory.\n"); 431 goto fail_base_qpair; 432 } 433 434 qla_init_base_qpair(vha, req, rsp); 435 436 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 437 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 438 GFP_KERNEL); 439 if (!ha->queue_pair_map) { 440 ql_log(ql_log_fatal, vha, 0x0180, 441 "Unable to allocate memory for queue pair ptrs.\n"); 442 goto fail_qpair_map; 443 } 444 } 445 446 /* 447 * Make sure we record at least the request and response queue zero in 448 * case we need to free them if part of the probe fails. 449 */ 450 ha->rsp_q_map[0] = rsp; 451 ha->req_q_map[0] = req; 452 set_bit(0, ha->rsp_qid_map); 453 set_bit(0, ha->req_qid_map); 454 return 0; 455 456fail_qpair_map: 457 kfree(ha->base_qpair); 458 ha->base_qpair = NULL; 459fail_base_qpair: 460 kfree(ha->rsp_q_map); 461 ha->rsp_q_map = NULL; 462fail_rsp_map: 463 kfree(ha->req_q_map); 464 ha->req_q_map = NULL; 465fail_req_map: 466 return -ENOMEM; 467} 468 469static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 470{ 471 if (IS_QLAFX00(ha)) { 472 if (req && req->ring_fx00) 473 dma_free_coherent(&ha->pdev->dev, 474 (req->length_fx00 + 1) * sizeof(request_t), 475 req->ring_fx00, req->dma_fx00); 476 } else if (req && req->ring) 477 dma_free_coherent(&ha->pdev->dev, 478 (req->length + 1) * sizeof(request_t), 479 req->ring, req->dma); 480 481 if (req) 482 kfree(req->outstanding_cmds); 483 484 kfree(req); 485} 486 487static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 488{ 489 if (IS_QLAFX00(ha)) { 490 if (rsp && rsp->ring_fx00) 491 dma_free_coherent(&ha->pdev->dev, 492 (rsp->length_fx00 + 1) * sizeof(request_t), 493 rsp->ring_fx00, rsp->dma_fx00); 494 } else if (rsp && rsp->ring) { 495 dma_free_coherent(&ha->pdev->dev, 496 (rsp->length + 1) * sizeof(response_t), 497 rsp->ring, rsp->dma); 498 } 499 kfree(rsp); 500} 501 502static void qla2x00_free_queues(struct qla_hw_data *ha) 503{ 504 struct req_que *req; 505 struct rsp_que *rsp; 506 int cnt; 507 unsigned long flags; 508 509 if (ha->queue_pair_map) { 510 kfree(ha->queue_pair_map); 511 ha->queue_pair_map = NULL; 512 } 513 if (ha->base_qpair) { 514 kfree(ha->base_qpair); 515 ha->base_qpair = NULL; 516 } 517 518 spin_lock_irqsave(&ha->hardware_lock, flags); 519 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 520 if (!test_bit(cnt, ha->req_qid_map)) 521 continue; 522 523 req = ha->req_q_map[cnt]; 524 clear_bit(cnt, ha->req_qid_map); 525 ha->req_q_map[cnt] = NULL; 526 527 spin_unlock_irqrestore(&ha->hardware_lock, flags); 528 qla2x00_free_req_que(ha, req); 529 spin_lock_irqsave(&ha->hardware_lock, flags); 530 } 531 spin_unlock_irqrestore(&ha->hardware_lock, flags); 532 533 kfree(ha->req_q_map); 534 ha->req_q_map = NULL; 535 536 537 spin_lock_irqsave(&ha->hardware_lock, flags); 538 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 539 if (!test_bit(cnt, ha->rsp_qid_map)) 540 continue; 541 542 rsp = ha->rsp_q_map[cnt]; 543 clear_bit(cnt, ha->rsp_qid_map); 544 ha->rsp_q_map[cnt] = NULL; 545 spin_unlock_irqrestore(&ha->hardware_lock, flags); 546 qla2x00_free_rsp_que(ha, rsp); 547 spin_lock_irqsave(&ha->hardware_lock, flags); 548 } 549 spin_unlock_irqrestore(&ha->hardware_lock, flags); 550 551 kfree(ha->rsp_q_map); 552 ha->rsp_q_map = NULL; 553} 554 555static char * 556qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 557{ 558 struct qla_hw_data *ha = vha->hw; 559 static const char *const pci_bus_modes[] = { 560 "33", "66", "100", "133", 561 }; 562 uint16_t pci_bus; 563 564 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 565 if (pci_bus) { 566 snprintf(str, str_len, "PCI-X (%s MHz)", 567 pci_bus_modes[pci_bus]); 568 } else { 569 pci_bus = (ha->pci_attr & BIT_8) >> 8; 570 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 571 } 572 573 return str; 574} 575 576static char * 577qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 578{ 579 static const char *const pci_bus_modes[] = { 580 "33", "66", "100", "133", 581 }; 582 struct qla_hw_data *ha = vha->hw; 583 uint32_t pci_bus; 584 585 if (pci_is_pcie(ha->pdev)) { 586 uint32_t lstat, lspeed, lwidth; 587 const char *speed_str; 588 589 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 590 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 591 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 592 593 switch (lspeed) { 594 case 1: 595 speed_str = "2.5GT/s"; 596 break; 597 case 2: 598 speed_str = "5.0GT/s"; 599 break; 600 case 3: 601 speed_str = "8.0GT/s"; 602 break; 603 case 4: 604 speed_str = "16.0GT/s"; 605 break; 606 default: 607 speed_str = "<unknown>"; 608 break; 609 } 610 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 611 612 return str; 613 } 614 615 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 616 if (pci_bus == 0 || pci_bus == 8) 617 snprintf(str, str_len, "PCI (%s MHz)", 618 pci_bus_modes[pci_bus >> 3]); 619 else 620 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 621 pci_bus & 4 ? 2 : 1, 622 pci_bus_modes[pci_bus & 3]); 623 624 return str; 625} 626 627static char * 628qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 629{ 630 char un_str[10]; 631 struct qla_hw_data *ha = vha->hw; 632 633 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 634 ha->fw_minor_version, ha->fw_subminor_version); 635 636 if (ha->fw_attributes & BIT_9) { 637 strcat(str, "FLX"); 638 return (str); 639 } 640 641 switch (ha->fw_attributes & 0xFF) { 642 case 0x7: 643 strcat(str, "EF"); 644 break; 645 case 0x17: 646 strcat(str, "TP"); 647 break; 648 case 0x37: 649 strcat(str, "IP"); 650 break; 651 case 0x77: 652 strcat(str, "VI"); 653 break; 654 default: 655 sprintf(un_str, "(%x)", ha->fw_attributes); 656 strcat(str, un_str); 657 break; 658 } 659 if (ha->fw_attributes & 0x100) 660 strcat(str, "X"); 661 662 return (str); 663} 664 665static char * 666qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 667{ 668 struct qla_hw_data *ha = vha->hw; 669 670 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 671 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 672 return str; 673} 674 675void qla2x00_sp_free_dma(srb_t *sp) 676{ 677 struct qla_hw_data *ha = sp->vha->hw; 678 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 679 680 if (sp->flags & SRB_DMA_VALID) { 681 scsi_dma_unmap(cmd); 682 sp->flags &= ~SRB_DMA_VALID; 683 } 684 685 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 686 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 687 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 688 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 689 } 690 691 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 692 /* List assured to be having elements */ 693 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 694 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 695 } 696 697 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 698 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 699 700 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 701 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 702 } 703 704 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 705 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 706 707 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 708 ctx1->fcp_cmnd_dma); 709 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 710 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 711 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 712 mempool_free(ctx1, ha->ctx_mempool); 713 } 714} 715 716void qla2x00_sp_compl(srb_t *sp, int res) 717{ 718 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 719 struct completion *comp = sp->comp; 720 721 sp->free(sp); 722 cmd->result = res; 723 CMD_SP(cmd) = NULL; 724 cmd->scsi_done(cmd); 725 if (comp) 726 complete(comp); 727} 728 729void qla2xxx_qpair_sp_free_dma(srb_t *sp) 730{ 731 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 732 struct qla_hw_data *ha = sp->fcport->vha->hw; 733 734 if (sp->flags & SRB_DMA_VALID) { 735 scsi_dma_unmap(cmd); 736 sp->flags &= ~SRB_DMA_VALID; 737 } 738 739 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 740 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 741 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 742 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 743 } 744 745 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 746 /* List assured to be having elements */ 747 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 748 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 749 } 750 751 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 752 struct crc_context *difctx = sp->u.scmd.crc_ctx; 753 struct dsd_dma *dif_dsd, *nxt_dsd; 754 755 list_for_each_entry_safe(dif_dsd, nxt_dsd, 756 &difctx->ldif_dma_hndl_list, list) { 757 list_del(&dif_dsd->list); 758 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 759 dif_dsd->dsd_list_dma); 760 kfree(dif_dsd); 761 difctx->no_dif_bundl--; 762 } 763 764 list_for_each_entry_safe(dif_dsd, nxt_dsd, 765 &difctx->ldif_dsd_list, list) { 766 list_del(&dif_dsd->list); 767 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 768 dif_dsd->dsd_list_dma); 769 kfree(dif_dsd); 770 difctx->no_ldif_dsd--; 771 } 772 773 if (difctx->no_ldif_dsd) { 774 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 775 "%s: difctx->no_ldif_dsd=%x\n", 776 __func__, difctx->no_ldif_dsd); 777 } 778 779 if (difctx->no_dif_bundl) { 780 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 781 "%s: difctx->no_dif_bundl=%x\n", 782 __func__, difctx->no_dif_bundl); 783 } 784 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 785 } 786 787 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 788 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 789 790 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 791 ctx1->fcp_cmnd_dma); 792 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 793 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 794 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 795 mempool_free(ctx1, ha->ctx_mempool); 796 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 797 } 798 799 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 800 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 801 802 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 803 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 804 } 805} 806 807void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 808{ 809 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 810 struct completion *comp = sp->comp; 811 812 sp->free(sp); 813 cmd->result = res; 814 CMD_SP(cmd) = NULL; 815 cmd->scsi_done(cmd); 816 if (comp) 817 complete(comp); 818} 819 820static int 821qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 822{ 823 scsi_qla_host_t *vha = shost_priv(host); 824 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 825 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 826 struct qla_hw_data *ha = vha->hw; 827 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 828 srb_t *sp; 829 int rval; 830 831 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 832 WARN_ON_ONCE(!rport)) { 833 cmd->result = DID_NO_CONNECT << 16; 834 goto qc24_fail_command; 835 } 836 837 if (ha->mqenable) { 838 uint32_t tag; 839 uint16_t hwq; 840 struct qla_qpair *qpair = NULL; 841 842 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 843 hwq = blk_mq_unique_tag_to_hwq(tag); 844 qpair = ha->queue_pair_map[hwq]; 845 846 if (qpair) 847 return qla2xxx_mqueuecommand(host, cmd, qpair); 848 } 849 850 if (ha->flags.eeh_busy) { 851 if (ha->flags.pci_channel_io_perm_failure) { 852 ql_dbg(ql_dbg_aer, vha, 0x9010, 853 "PCI Channel IO permanent failure, exiting " 854 "cmd=%p.\n", cmd); 855 cmd->result = DID_NO_CONNECT << 16; 856 } else { 857 ql_dbg(ql_dbg_aer, vha, 0x9011, 858 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 859 cmd->result = DID_REQUEUE << 16; 860 } 861 goto qc24_fail_command; 862 } 863 864 rval = fc_remote_port_chkready(rport); 865 if (rval) { 866 cmd->result = rval; 867 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 868 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 869 cmd, rval); 870 goto qc24_fail_command; 871 } 872 873 if (!vha->flags.difdix_supported && 874 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 875 ql_dbg(ql_dbg_io, vha, 0x3004, 876 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 877 cmd); 878 cmd->result = DID_NO_CONNECT << 16; 879 goto qc24_fail_command; 880 } 881 882 if (!fcport || fcport->deleted) { 883 cmd->result = DID_IMM_RETRY << 16; 884 goto qc24_fail_command; 885 } 886 887 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 888 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 889 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 890 ql_dbg(ql_dbg_io, vha, 0x3005, 891 "Returning DNC, fcport_state=%d loop_state=%d.\n", 892 atomic_read(&fcport->state), 893 atomic_read(&base_vha->loop_state)); 894 cmd->result = DID_NO_CONNECT << 16; 895 goto qc24_fail_command; 896 } 897 goto qc24_target_busy; 898 } 899 900 /* 901 * Return target busy if we've received a non-zero retry_delay_timer 902 * in a FCP_RSP. 903 */ 904 if (fcport->retry_delay_timestamp == 0) { 905 /* retry delay not set */ 906 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 907 fcport->retry_delay_timestamp = 0; 908 else 909 goto qc24_target_busy; 910 911 sp = scsi_cmd_priv(cmd); 912 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 913 914 sp->u.scmd.cmd = cmd; 915 sp->type = SRB_SCSI_CMD; 916 917 CMD_SP(cmd) = (void *)sp; 918 sp->free = qla2x00_sp_free_dma; 919 sp->done = qla2x00_sp_compl; 920 921 rval = ha->isp_ops->start_scsi(sp); 922 if (rval != QLA_SUCCESS) { 923 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 924 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 925 goto qc24_host_busy_free_sp; 926 } 927 928 return 0; 929 930qc24_host_busy_free_sp: 931 sp->free(sp); 932 933qc24_target_busy: 934 return SCSI_MLQUEUE_TARGET_BUSY; 935 936qc24_fail_command: 937 cmd->scsi_done(cmd); 938 939 return 0; 940} 941 942/* For MQ supported I/O */ 943int 944qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 945 struct qla_qpair *qpair) 946{ 947 scsi_qla_host_t *vha = shost_priv(host); 948 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 949 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 950 struct qla_hw_data *ha = vha->hw; 951 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 952 srb_t *sp; 953 int rval; 954 955 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 956 if (rval) { 957 cmd->result = rval; 958 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 959 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 960 cmd, rval); 961 goto qc24_fail_command; 962 } 963 964 if (!qpair->online) { 965 ql_dbg(ql_dbg_io, vha, 0x3077, 966 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 967 cmd->result = DID_NO_CONNECT << 16; 968 goto qc24_fail_command; 969 } 970 971 if (!fcport || fcport->deleted) { 972 cmd->result = DID_IMM_RETRY << 16; 973 goto qc24_fail_command; 974 } 975 976 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 977 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 978 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 979 ql_dbg(ql_dbg_io, vha, 0x3077, 980 "Returning DNC, fcport_state=%d loop_state=%d.\n", 981 atomic_read(&fcport->state), 982 atomic_read(&base_vha->loop_state)); 983 cmd->result = DID_NO_CONNECT << 16; 984 goto qc24_fail_command; 985 } 986 goto qc24_target_busy; 987 } 988 989 /* 990 * Return target busy if we've received a non-zero retry_delay_timer 991 * in a FCP_RSP. 992 */ 993 if (fcport->retry_delay_timestamp == 0) { 994 /* retry delay not set */ 995 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 996 fcport->retry_delay_timestamp = 0; 997 else 998 goto qc24_target_busy; 999 1000 sp = scsi_cmd_priv(cmd); 1001 qla2xxx_init_sp(sp, vha, qpair, fcport); 1002 1003 sp->u.scmd.cmd = cmd; 1004 sp->type = SRB_SCSI_CMD; 1005 CMD_SP(cmd) = (void *)sp; 1006 sp->free = qla2xxx_qpair_sp_free_dma; 1007 sp->done = qla2xxx_qpair_sp_compl; 1008 1009 rval = ha->isp_ops->start_scsi_mq(sp); 1010 if (rval != QLA_SUCCESS) { 1011 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1012 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1013 goto qc24_host_busy_free_sp; 1014 } 1015 1016 return 0; 1017 1018qc24_host_busy_free_sp: 1019 sp->free(sp); 1020 1021qc24_target_busy: 1022 return SCSI_MLQUEUE_TARGET_BUSY; 1023 1024qc24_fail_command: 1025 cmd->scsi_done(cmd); 1026 1027 return 0; 1028} 1029 1030/* 1031 * qla2x00_eh_wait_on_command 1032 * Waits for the command to be returned by the Firmware for some 1033 * max time. 1034 * 1035 * Input: 1036 * cmd = Scsi Command to wait on. 1037 * 1038 * Return: 1039 * Completed in time : QLA_SUCCESS 1040 * Did not complete in time : QLA_FUNCTION_FAILED 1041 */ 1042static int 1043qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1044{ 1045#define ABORT_POLLING_PERIOD 1000 1046#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1047 unsigned long wait_iter = ABORT_WAIT_ITER; 1048 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1049 struct qla_hw_data *ha = vha->hw; 1050 int ret = QLA_SUCCESS; 1051 1052 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1053 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1054 "Return:eh_wait.\n"); 1055 return ret; 1056 } 1057 1058 while (CMD_SP(cmd) && wait_iter--) { 1059 msleep(ABORT_POLLING_PERIOD); 1060 } 1061 if (CMD_SP(cmd)) 1062 ret = QLA_FUNCTION_FAILED; 1063 1064 return ret; 1065} 1066 1067/* 1068 * qla2x00_wait_for_hba_online 1069 * Wait till the HBA is online after going through 1070 * <= MAX_RETRIES_OF_ISP_ABORT or 1071 * finally HBA is disabled ie marked offline 1072 * 1073 * Input: 1074 * ha - pointer to host adapter structure 1075 * 1076 * Note: 1077 * Does context switching-Release SPIN_LOCK 1078 * (if any) before calling this routine. 1079 * 1080 * Return: 1081 * Success (Adapter is online) : 0 1082 * Failed (Adapter is offline/disabled) : 1 1083 */ 1084int 1085qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1086{ 1087 int return_status; 1088 unsigned long wait_online; 1089 struct qla_hw_data *ha = vha->hw; 1090 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1091 1092 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1093 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1094 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1095 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1096 ha->dpc_active) && time_before(jiffies, wait_online)) { 1097 1098 msleep(1000); 1099 } 1100 if (base_vha->flags.online) 1101 return_status = QLA_SUCCESS; 1102 else 1103 return_status = QLA_FUNCTION_FAILED; 1104 1105 return (return_status); 1106} 1107 1108static inline int test_fcport_count(scsi_qla_host_t *vha) 1109{ 1110 struct qla_hw_data *ha = vha->hw; 1111 unsigned long flags; 1112 int res; 1113 1114 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1115 ql_dbg(ql_dbg_init, vha, 0x00ec, 1116 "tgt %p, fcport_count=%d\n", 1117 vha, vha->fcport_count); 1118 res = (vha->fcport_count == 0); 1119 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1120 1121 return res; 1122} 1123 1124/* 1125 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1126 * it has dependency on UNLOADING flag to stop device discovery 1127 */ 1128void 1129qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1130{ 1131 u8 i; 1132 1133 qla2x00_mark_all_devices_lost(vha); 1134 1135 for (i = 0; i < 10; i++) { 1136 if (wait_event_timeout(vha->fcport_waitQ, 1137 test_fcport_count(vha), HZ) > 0) 1138 break; 1139 } 1140 1141 flush_workqueue(vha->hw->wq); 1142} 1143 1144/* 1145 * qla2x00_wait_for_hba_ready 1146 * Wait till the HBA is ready before doing driver unload 1147 * 1148 * Input: 1149 * ha - pointer to host adapter structure 1150 * 1151 * Note: 1152 * Does context switching-Release SPIN_LOCK 1153 * (if any) before calling this routine. 1154 * 1155 */ 1156static void 1157qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1158{ 1159 struct qla_hw_data *ha = vha->hw; 1160 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1161 1162 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1163 ha->flags.mbox_busy) || 1164 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1165 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1166 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1167 break; 1168 msleep(1000); 1169 } 1170} 1171 1172int 1173qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1174{ 1175 int return_status; 1176 unsigned long wait_reset; 1177 struct qla_hw_data *ha = vha->hw; 1178 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1179 1180 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1181 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1182 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1183 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1184 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1185 1186 msleep(1000); 1187 1188 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1189 ha->flags.chip_reset_done) 1190 break; 1191 } 1192 if (ha->flags.chip_reset_done) 1193 return_status = QLA_SUCCESS; 1194 else 1195 return_status = QLA_FUNCTION_FAILED; 1196 1197 return return_status; 1198} 1199 1200/************************************************************************** 1201* qla2xxx_eh_abort 1202* 1203* Description: 1204* The abort function will abort the specified command. 1205* 1206* Input: 1207* cmd = Linux SCSI command packet to be aborted. 1208* 1209* Returns: 1210* Either SUCCESS or FAILED. 1211* 1212* Note: 1213* Only return FAILED if command not returned by firmware. 1214**************************************************************************/ 1215static int 1216qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1217{ 1218 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1219 DECLARE_COMPLETION_ONSTACK(comp); 1220 srb_t *sp; 1221 int ret; 1222 unsigned int id; 1223 uint64_t lun; 1224 int rval; 1225 struct qla_hw_data *ha = vha->hw; 1226 uint32_t ratov_j; 1227 struct qla_qpair *qpair; 1228 unsigned long flags; 1229 int fast_fail_status = SUCCESS; 1230 1231 if (qla2x00_isp_reg_stat(ha)) { 1232 ql_log(ql_log_info, vha, 0x8042, 1233 "PCI/Register disconnect, exiting.\n"); 1234 qla_pci_set_eeh_busy(vha); 1235 return FAILED; 1236 } 1237 1238 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1239 ret = fc_block_scsi_eh(cmd); 1240 if (ret != 0) 1241 fast_fail_status = ret; 1242 1243 sp = scsi_cmd_priv(cmd); 1244 qpair = sp->qpair; 1245 1246 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1247 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1248 1249 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1250 sp->comp = ∁ 1251 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1252 1253 1254 id = cmd->device->id; 1255 lun = cmd->device->lun; 1256 1257 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1258 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1259 vha->host_no, id, lun, sp, cmd, sp->handle); 1260 1261 /* 1262 * Abort will release the original Command/sp from FW. Let the 1263 * original command call scsi_done. In return, he will wakeup 1264 * this sleeping thread. 1265 */ 1266 rval = ha->isp_ops->abort_command(sp); 1267 1268 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1269 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1270 1271 /* Wait for the command completion. */ 1272 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1273 ratov_j = msecs_to_jiffies(ratov_j); 1274 switch (rval) { 1275 case QLA_SUCCESS: 1276 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1277 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1278 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1279 __func__, ha->r_a_tov/10); 1280 ret = FAILED; 1281 } else { 1282 ret = fast_fail_status; 1283 } 1284 break; 1285 default: 1286 ret = FAILED; 1287 break; 1288 } 1289 1290 sp->comp = NULL; 1291 1292 ql_log(ql_log_info, vha, 0x801c, 1293 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1294 vha->host_no, id, lun, ret); 1295 1296 return ret; 1297} 1298 1299/* 1300 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1301 */ 1302int 1303qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1304 uint64_t l, enum nexus_wait_type type) 1305{ 1306 int cnt, match, status; 1307 unsigned long flags; 1308 struct qla_hw_data *ha = vha->hw; 1309 struct req_que *req; 1310 srb_t *sp; 1311 struct scsi_cmnd *cmd; 1312 1313 status = QLA_SUCCESS; 1314 1315 spin_lock_irqsave(&ha->hardware_lock, flags); 1316 req = vha->req; 1317 for (cnt = 1; status == QLA_SUCCESS && 1318 cnt < req->num_outstanding_cmds; cnt++) { 1319 sp = req->outstanding_cmds[cnt]; 1320 if (!sp) 1321 continue; 1322 if (sp->type != SRB_SCSI_CMD) 1323 continue; 1324 if (vha->vp_idx != sp->vha->vp_idx) 1325 continue; 1326 match = 0; 1327 cmd = GET_CMD_SP(sp); 1328 switch (type) { 1329 case WAIT_HOST: 1330 match = 1; 1331 break; 1332 case WAIT_TARGET: 1333 match = cmd->device->id == t; 1334 break; 1335 case WAIT_LUN: 1336 match = (cmd->device->id == t && 1337 cmd->device->lun == l); 1338 break; 1339 } 1340 if (!match) 1341 continue; 1342 1343 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1344 status = qla2x00_eh_wait_on_command(cmd); 1345 spin_lock_irqsave(&ha->hardware_lock, flags); 1346 } 1347 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1348 1349 return status; 1350} 1351 1352static char *reset_errors[] = { 1353 "HBA not online", 1354 "HBA not ready", 1355 "Task management failed", 1356 "Waiting for command completions", 1357}; 1358 1359static int 1360__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1361 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1362{ 1363 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1364 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1365 int err; 1366 1367 if (!fcport) { 1368 return FAILED; 1369 } 1370 1371 err = fc_block_scsi_eh(cmd); 1372 if (err != 0) 1373 return err; 1374 1375 if (fcport->deleted) 1376 return SUCCESS; 1377 1378 ql_log(ql_log_info, vha, 0x8009, 1379 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1380 cmd->device->id, cmd->device->lun, cmd); 1381 1382 err = 0; 1383 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1384 ql_log(ql_log_warn, vha, 0x800a, 1385 "Wait for hba online failed for cmd=%p.\n", cmd); 1386 goto eh_reset_failed; 1387 } 1388 err = 2; 1389 if (do_reset(fcport, cmd->device->lun, 1) 1390 != QLA_SUCCESS) { 1391 ql_log(ql_log_warn, vha, 0x800c, 1392 "do_reset failed for cmd=%p.\n", cmd); 1393 goto eh_reset_failed; 1394 } 1395 err = 3; 1396 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1397 cmd->device->lun, type) != QLA_SUCCESS) { 1398 ql_log(ql_log_warn, vha, 0x800d, 1399 "wait for pending cmds failed for cmd=%p.\n", cmd); 1400 goto eh_reset_failed; 1401 } 1402 1403 ql_log(ql_log_info, vha, 0x800e, 1404 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1405 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1406 1407 return SUCCESS; 1408 1409eh_reset_failed: 1410 ql_log(ql_log_info, vha, 0x800f, 1411 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1412 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1413 cmd); 1414 return FAILED; 1415} 1416 1417static int 1418qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1419{ 1420 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1421 struct qla_hw_data *ha = vha->hw; 1422 1423 if (qla2x00_isp_reg_stat(ha)) { 1424 ql_log(ql_log_info, vha, 0x803e, 1425 "PCI/Register disconnect, exiting.\n"); 1426 qla_pci_set_eeh_busy(vha); 1427 return FAILED; 1428 } 1429 1430 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1431 ha->isp_ops->lun_reset); 1432} 1433 1434static int 1435qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1436{ 1437 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1438 struct qla_hw_data *ha = vha->hw; 1439 1440 if (qla2x00_isp_reg_stat(ha)) { 1441 ql_log(ql_log_info, vha, 0x803f, 1442 "PCI/Register disconnect, exiting.\n"); 1443 qla_pci_set_eeh_busy(vha); 1444 return FAILED; 1445 } 1446 1447 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1448 ha->isp_ops->target_reset); 1449} 1450 1451/************************************************************************** 1452* qla2xxx_eh_bus_reset 1453* 1454* Description: 1455* The bus reset function will reset the bus and abort any executing 1456* commands. 1457* 1458* Input: 1459* cmd = Linux SCSI command packet of the command that cause the 1460* bus reset. 1461* 1462* Returns: 1463* SUCCESS/FAILURE (defined as macro in scsi.h). 1464* 1465**************************************************************************/ 1466static int 1467qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1468{ 1469 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1470 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1471 int ret = FAILED; 1472 unsigned int id; 1473 uint64_t lun; 1474 struct qla_hw_data *ha = vha->hw; 1475 1476 if (qla2x00_isp_reg_stat(ha)) { 1477 ql_log(ql_log_info, vha, 0x8040, 1478 "PCI/Register disconnect, exiting.\n"); 1479 qla_pci_set_eeh_busy(vha); 1480 return FAILED; 1481 } 1482 1483 id = cmd->device->id; 1484 lun = cmd->device->lun; 1485 1486 if (!fcport) { 1487 return ret; 1488 } 1489 1490 ret = fc_block_scsi_eh(cmd); 1491 if (ret != 0) 1492 return ret; 1493 ret = FAILED; 1494 1495 if (qla2x00_chip_is_down(vha)) 1496 return ret; 1497 1498 ql_log(ql_log_info, vha, 0x8012, 1499 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1500 1501 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1502 ql_log(ql_log_fatal, vha, 0x8013, 1503 "Wait for hba online failed board disabled.\n"); 1504 goto eh_bus_reset_done; 1505 } 1506 1507 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1508 ret = SUCCESS; 1509 1510 if (ret == FAILED) 1511 goto eh_bus_reset_done; 1512 1513 /* Flush outstanding commands. */ 1514 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1515 QLA_SUCCESS) { 1516 ql_log(ql_log_warn, vha, 0x8014, 1517 "Wait for pending commands failed.\n"); 1518 ret = FAILED; 1519 } 1520 1521eh_bus_reset_done: 1522 ql_log(ql_log_warn, vha, 0x802b, 1523 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1524 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1525 1526 return ret; 1527} 1528 1529/************************************************************************** 1530* qla2xxx_eh_host_reset 1531* 1532* Description: 1533* The reset function will reset the Adapter. 1534* 1535* Input: 1536* cmd = Linux SCSI command packet of the command that cause the 1537* adapter reset. 1538* 1539* Returns: 1540* Either SUCCESS or FAILED. 1541* 1542* Note: 1543**************************************************************************/ 1544static int 1545qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1546{ 1547 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1548 struct qla_hw_data *ha = vha->hw; 1549 int ret = FAILED; 1550 unsigned int id; 1551 uint64_t lun; 1552 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1553 1554 if (qla2x00_isp_reg_stat(ha)) { 1555 ql_log(ql_log_info, vha, 0x8041, 1556 "PCI/Register disconnect, exiting.\n"); 1557 qla_pci_set_eeh_busy(vha); 1558 return SUCCESS; 1559 } 1560 1561 id = cmd->device->id; 1562 lun = cmd->device->lun; 1563 1564 ql_log(ql_log_info, vha, 0x8018, 1565 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1566 1567 /* 1568 * No point in issuing another reset if one is active. Also do not 1569 * attempt a reset if we are updating flash. 1570 */ 1571 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1572 goto eh_host_reset_lock; 1573 1574 if (vha != base_vha) { 1575 if (qla2x00_vp_abort_isp(vha)) 1576 goto eh_host_reset_lock; 1577 } else { 1578 if (IS_P3P_TYPE(vha->hw)) { 1579 if (!qla82xx_fcoe_ctx_reset(vha)) { 1580 /* Ctx reset success */ 1581 ret = SUCCESS; 1582 goto eh_host_reset_lock; 1583 } 1584 /* fall thru if ctx reset failed */ 1585 } 1586 if (ha->wq) 1587 flush_workqueue(ha->wq); 1588 1589 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1590 if (ha->isp_ops->abort_isp(base_vha)) { 1591 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1592 /* failed. schedule dpc to try */ 1593 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1594 1595 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1596 ql_log(ql_log_warn, vha, 0x802a, 1597 "wait for hba online failed.\n"); 1598 goto eh_host_reset_lock; 1599 } 1600 } 1601 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1602 } 1603 1604 /* Waiting for command to be returned to OS.*/ 1605 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1606 QLA_SUCCESS) 1607 ret = SUCCESS; 1608 1609eh_host_reset_lock: 1610 ql_log(ql_log_info, vha, 0x8017, 1611 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1612 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1613 1614 return ret; 1615} 1616 1617/* 1618* qla2x00_loop_reset 1619* Issue loop reset. 1620* 1621* Input: 1622* ha = adapter block pointer. 1623* 1624* Returns: 1625* 0 = success 1626*/ 1627int 1628qla2x00_loop_reset(scsi_qla_host_t *vha) 1629{ 1630 int ret; 1631 struct qla_hw_data *ha = vha->hw; 1632 1633 if (IS_QLAFX00(ha)) 1634 return QLA_SUCCESS; 1635 1636 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1637 atomic_set(&vha->loop_state, LOOP_DOWN); 1638 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1639 qla2x00_mark_all_devices_lost(vha); 1640 ret = qla2x00_full_login_lip(vha); 1641 if (ret != QLA_SUCCESS) { 1642 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1643 "full_login_lip=%d.\n", ret); 1644 } 1645 } 1646 1647 if (ha->flags.enable_lip_reset) { 1648 ret = qla2x00_lip_reset(vha); 1649 if (ret != QLA_SUCCESS) 1650 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1651 "lip_reset failed (%d).\n", ret); 1652 } 1653 1654 /* Issue marker command only when we are going to start the I/O */ 1655 vha->marker_needed = 1; 1656 1657 return QLA_SUCCESS; 1658} 1659 1660/* 1661 * The caller must ensure that no completion interrupts will happen 1662 * while this function is in progress. 1663 */ 1664static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1665 unsigned long *flags) 1666 __releases(qp->qp_lock_ptr) 1667 __acquires(qp->qp_lock_ptr) 1668{ 1669 DECLARE_COMPLETION_ONSTACK(comp); 1670 scsi_qla_host_t *vha = qp->vha; 1671 struct qla_hw_data *ha = vha->hw; 1672 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1673 int rval; 1674 bool ret_cmd; 1675 uint32_t ratov_j; 1676 1677 lockdep_assert_held(qp->qp_lock_ptr); 1678 1679 if (qla2x00_chip_is_down(vha)) { 1680 sp->done(sp, res); 1681 return; 1682 } 1683 1684 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1685 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1686 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1687 !qla2x00_isp_reg_stat(ha))) { 1688 if (sp->comp) { 1689 sp->done(sp, res); 1690 return; 1691 } 1692 1693 sp->comp = ∁ 1694 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1695 1696 rval = ha->isp_ops->abort_command(sp); 1697 /* Wait for command completion. */ 1698 ret_cmd = false; 1699 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1700 ratov_j = msecs_to_jiffies(ratov_j); 1701 switch (rval) { 1702 case QLA_SUCCESS: 1703 if (wait_for_completion_timeout(&comp, ratov_j)) { 1704 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1705 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1706 __func__, ha->r_a_tov/10); 1707 ret_cmd = true; 1708 } 1709 /* else FW return SP to driver */ 1710 break; 1711 default: 1712 ret_cmd = true; 1713 break; 1714 } 1715 1716 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1717 switch (sp->type) { 1718 case SRB_SCSI_CMD: 1719 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1720 sp->done(sp, res); 1721 break; 1722 default: 1723 if (ret_cmd) 1724 sp->done(sp, res); 1725 break; 1726 } 1727 } else { 1728 sp->done(sp, res); 1729 } 1730} 1731 1732/* 1733 * The caller must ensure that no completion interrupts will happen 1734 * while this function is in progress. 1735 */ 1736static void 1737__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1738{ 1739 int cnt; 1740 unsigned long flags; 1741 srb_t *sp; 1742 scsi_qla_host_t *vha = qp->vha; 1743 struct qla_hw_data *ha = vha->hw; 1744 struct req_que *req; 1745 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1746 struct qla_tgt_cmd *cmd; 1747 1748 if (!ha->req_q_map) 1749 return; 1750 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1751 req = qp->req; 1752 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1753 sp = req->outstanding_cmds[cnt]; 1754 if (sp) { 1755 /* 1756 * perform lockless completion during driver unload 1757 */ 1758 if (qla2x00_chip_is_down(vha)) { 1759 req->outstanding_cmds[cnt] = NULL; 1760 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1761 sp->done(sp, res); 1762 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1763 continue; 1764 } 1765 1766 switch (sp->cmd_type) { 1767 case TYPE_SRB: 1768 qla2x00_abort_srb(qp, sp, res, &flags); 1769 break; 1770 case TYPE_TGT_CMD: 1771 if (!vha->hw->tgt.tgt_ops || !tgt || 1772 qla_ini_mode_enabled(vha)) { 1773 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1774 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1775 vha->dpc_flags); 1776 continue; 1777 } 1778 cmd = (struct qla_tgt_cmd *)sp; 1779 cmd->aborted = 1; 1780 break; 1781 case TYPE_TGT_TMCMD: 1782 /* Skip task management functions. */ 1783 break; 1784 default: 1785 break; 1786 } 1787 req->outstanding_cmds[cnt] = NULL; 1788 } 1789 } 1790 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1791} 1792 1793/* 1794 * The caller must ensure that no completion interrupts will happen 1795 * while this function is in progress. 1796 */ 1797void 1798qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1799{ 1800 int que; 1801 struct qla_hw_data *ha = vha->hw; 1802 1803 /* Continue only if initialization complete. */ 1804 if (!ha->base_qpair) 1805 return; 1806 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1807 1808 if (!ha->queue_pair_map) 1809 return; 1810 for (que = 0; que < ha->max_qpairs; que++) { 1811 if (!ha->queue_pair_map[que]) 1812 continue; 1813 1814 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1815 } 1816} 1817 1818static int 1819qla2xxx_slave_alloc(struct scsi_device *sdev) 1820{ 1821 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1822 1823 if (!rport || fc_remote_port_chkready(rport)) 1824 return -ENXIO; 1825 1826 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1827 1828 return 0; 1829} 1830 1831static int 1832qla2xxx_slave_configure(struct scsi_device *sdev) 1833{ 1834 scsi_qla_host_t *vha = shost_priv(sdev->host); 1835 struct req_que *req = vha->req; 1836 1837 if (IS_T10_PI_CAPABLE(vha->hw)) 1838 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1839 1840 scsi_change_queue_depth(sdev, req->max_q_depth); 1841 return 0; 1842} 1843 1844static void 1845qla2xxx_slave_destroy(struct scsi_device *sdev) 1846{ 1847 sdev->hostdata = NULL; 1848} 1849 1850/** 1851 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1852 * @ha: HA context 1853 * 1854 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1855 * supported addressing method. 1856 */ 1857static void 1858qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1859{ 1860 /* Assume a 32bit DMA mask. */ 1861 ha->flags.enable_64bit_addressing = 0; 1862 1863 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1864 /* Any upper-dword bits set? */ 1865 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1866 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1867 /* Ok, a 64bit DMA mask is applicable. */ 1868 ha->flags.enable_64bit_addressing = 1; 1869 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1870 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1871 return; 1872 } 1873 } 1874 1875 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1876 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1877} 1878 1879static void 1880qla2x00_enable_intrs(struct qla_hw_data *ha) 1881{ 1882 unsigned long flags = 0; 1883 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1884 1885 spin_lock_irqsave(&ha->hardware_lock, flags); 1886 ha->interrupts_on = 1; 1887 /* enable risc and host interrupts */ 1888 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1889 rd_reg_word(®->ictrl); 1890 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1891 1892} 1893 1894static void 1895qla2x00_disable_intrs(struct qla_hw_data *ha) 1896{ 1897 unsigned long flags = 0; 1898 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1899 1900 spin_lock_irqsave(&ha->hardware_lock, flags); 1901 ha->interrupts_on = 0; 1902 /* disable risc and host interrupts */ 1903 wrt_reg_word(®->ictrl, 0); 1904 rd_reg_word(®->ictrl); 1905 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1906} 1907 1908static void 1909qla24xx_enable_intrs(struct qla_hw_data *ha) 1910{ 1911 unsigned long flags = 0; 1912 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1913 1914 spin_lock_irqsave(&ha->hardware_lock, flags); 1915 ha->interrupts_on = 1; 1916 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1917 rd_reg_dword(®->ictrl); 1918 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1919} 1920 1921static void 1922qla24xx_disable_intrs(struct qla_hw_data *ha) 1923{ 1924 unsigned long flags = 0; 1925 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1926 1927 if (IS_NOPOLLING_TYPE(ha)) 1928 return; 1929 spin_lock_irqsave(&ha->hardware_lock, flags); 1930 ha->interrupts_on = 0; 1931 wrt_reg_dword(®->ictrl, 0); 1932 rd_reg_dword(®->ictrl); 1933 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1934} 1935 1936static int 1937qla2x00_iospace_config(struct qla_hw_data *ha) 1938{ 1939 resource_size_t pio; 1940 uint16_t msix; 1941 1942 if (pci_request_selected_regions(ha->pdev, ha->bars, 1943 QLA2XXX_DRIVER_NAME)) { 1944 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1945 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1946 pci_name(ha->pdev)); 1947 goto iospace_error_exit; 1948 } 1949 if (!(ha->bars & 1)) 1950 goto skip_pio; 1951 1952 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1953 pio = pci_resource_start(ha->pdev, 0); 1954 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1955 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1956 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1957 "Invalid pci I/O region size (%s).\n", 1958 pci_name(ha->pdev)); 1959 pio = 0; 1960 } 1961 } else { 1962 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1963 "Region #0 no a PIO resource (%s).\n", 1964 pci_name(ha->pdev)); 1965 pio = 0; 1966 } 1967 ha->pio_address = pio; 1968 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1969 "PIO address=%llu.\n", 1970 (unsigned long long)ha->pio_address); 1971 1972skip_pio: 1973 /* Use MMIO operations for all accesses. */ 1974 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1976 "Region #1 not an MMIO resource (%s), aborting.\n", 1977 pci_name(ha->pdev)); 1978 goto iospace_error_exit; 1979 } 1980 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1981 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1982 "Invalid PCI mem region size (%s), aborting.\n", 1983 pci_name(ha->pdev)); 1984 goto iospace_error_exit; 1985 } 1986 1987 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1988 if (!ha->iobase) { 1989 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1990 "Cannot remap MMIO (%s), aborting.\n", 1991 pci_name(ha->pdev)); 1992 goto iospace_error_exit; 1993 } 1994 1995 /* Determine queue resources */ 1996 ha->max_req_queues = ha->max_rsp_queues = 1; 1997 ha->msix_count = QLA_BASE_VECTORS; 1998 1999 /* Check if FW supports MQ or not */ 2000 if (!(ha->fw_attributes & BIT_6)) 2001 goto mqiobase_exit; 2002 2003 if (!ql2xmqsupport || !ql2xnvmeenable || 2004 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2005 goto mqiobase_exit; 2006 2007 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2008 pci_resource_len(ha->pdev, 3)); 2009 if (ha->mqiobase) { 2010 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2011 "MQIO Base=%p.\n", ha->mqiobase); 2012 /* Read MSIX vector size of the board */ 2013 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2014 ha->msix_count = msix + 1; 2015 /* Max queues are bounded by available msix vectors */ 2016 /* MB interrupt uses 1 vector */ 2017 ha->max_req_queues = ha->msix_count - 1; 2018 ha->max_rsp_queues = ha->max_req_queues; 2019 /* Queue pairs is the max value minus the base queue pair */ 2020 ha->max_qpairs = ha->max_rsp_queues - 1; 2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2022 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2023 2024 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2025 "MSI-X vector count: %d.\n", ha->msix_count); 2026 } else 2027 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2028 "BAR 3 not enabled.\n"); 2029 2030mqiobase_exit: 2031 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2032 "MSIX Count: %d.\n", ha->msix_count); 2033 return (0); 2034 2035iospace_error_exit: 2036 return (-ENOMEM); 2037} 2038 2039 2040static int 2041qla83xx_iospace_config(struct qla_hw_data *ha) 2042{ 2043 uint16_t msix; 2044 2045 if (pci_request_selected_regions(ha->pdev, ha->bars, 2046 QLA2XXX_DRIVER_NAME)) { 2047 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2048 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2049 pci_name(ha->pdev)); 2050 2051 goto iospace_error_exit; 2052 } 2053 2054 /* Use MMIO operations for all accesses. */ 2055 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2056 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2057 "Invalid pci I/O region size (%s).\n", 2058 pci_name(ha->pdev)); 2059 goto iospace_error_exit; 2060 } 2061 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2062 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2063 "Invalid PCI mem region size (%s), aborting\n", 2064 pci_name(ha->pdev)); 2065 goto iospace_error_exit; 2066 } 2067 2068 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2069 if (!ha->iobase) { 2070 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2071 "Cannot remap MMIO (%s), aborting.\n", 2072 pci_name(ha->pdev)); 2073 goto iospace_error_exit; 2074 } 2075 2076 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2077 /* 83XX 26XX always use MQ type access for queues 2078 * - mbar 2, a.k.a region 4 */ 2079 ha->max_req_queues = ha->max_rsp_queues = 1; 2080 ha->msix_count = QLA_BASE_VECTORS; 2081 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2082 pci_resource_len(ha->pdev, 4)); 2083 2084 if (!ha->mqiobase) { 2085 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2086 "BAR2/region4 not enabled\n"); 2087 goto mqiobase_exit; 2088 } 2089 2090 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2091 pci_resource_len(ha->pdev, 2)); 2092 if (ha->msixbase) { 2093 /* Read MSIX vector size of the board */ 2094 pci_read_config_word(ha->pdev, 2095 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2096 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2097 /* 2098 * By default, driver uses at least two msix vectors 2099 * (default & rspq) 2100 */ 2101 if (ql2xmqsupport || ql2xnvmeenable) { 2102 /* MB interrupt uses 1 vector */ 2103 ha->max_req_queues = ha->msix_count - 1; 2104 2105 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2106 if (QLA_TGT_MODE_ENABLED()) 2107 ha->max_req_queues--; 2108 2109 ha->max_rsp_queues = ha->max_req_queues; 2110 2111 /* Queue pairs is the max value minus 2112 * the base queue pair */ 2113 ha->max_qpairs = ha->max_req_queues - 1; 2114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2115 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2116 } 2117 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2118 "MSI-X vector count: %d.\n", ha->msix_count); 2119 } else 2120 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2121 "BAR 1 not enabled.\n"); 2122 2123mqiobase_exit: 2124 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2125 "MSIX Count: %d.\n", ha->msix_count); 2126 return 0; 2127 2128iospace_error_exit: 2129 return -ENOMEM; 2130} 2131 2132static struct isp_operations qla2100_isp_ops = { 2133 .pci_config = qla2100_pci_config, 2134 .reset_chip = qla2x00_reset_chip, 2135 .chip_diag = qla2x00_chip_diag, 2136 .config_rings = qla2x00_config_rings, 2137 .reset_adapter = qla2x00_reset_adapter, 2138 .nvram_config = qla2x00_nvram_config, 2139 .update_fw_options = qla2x00_update_fw_options, 2140 .load_risc = qla2x00_load_risc, 2141 .pci_info_str = qla2x00_pci_info_str, 2142 .fw_version_str = qla2x00_fw_version_str, 2143 .intr_handler = qla2100_intr_handler, 2144 .enable_intrs = qla2x00_enable_intrs, 2145 .disable_intrs = qla2x00_disable_intrs, 2146 .abort_command = qla2x00_abort_command, 2147 .target_reset = qla2x00_abort_target, 2148 .lun_reset = qla2x00_lun_reset, 2149 .fabric_login = qla2x00_login_fabric, 2150 .fabric_logout = qla2x00_fabric_logout, 2151 .calc_req_entries = qla2x00_calc_iocbs_32, 2152 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2153 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2154 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2155 .read_nvram = qla2x00_read_nvram_data, 2156 .write_nvram = qla2x00_write_nvram_data, 2157 .fw_dump = qla2100_fw_dump, 2158 .beacon_on = NULL, 2159 .beacon_off = NULL, 2160 .beacon_blink = NULL, 2161 .read_optrom = qla2x00_read_optrom_data, 2162 .write_optrom = qla2x00_write_optrom_data, 2163 .get_flash_version = qla2x00_get_flash_version, 2164 .start_scsi = qla2x00_start_scsi, 2165 .start_scsi_mq = NULL, 2166 .abort_isp = qla2x00_abort_isp, 2167 .iospace_config = qla2x00_iospace_config, 2168 .initialize_adapter = qla2x00_initialize_adapter, 2169}; 2170 2171static struct isp_operations qla2300_isp_ops = { 2172 .pci_config = qla2300_pci_config, 2173 .reset_chip = qla2x00_reset_chip, 2174 .chip_diag = qla2x00_chip_diag, 2175 .config_rings = qla2x00_config_rings, 2176 .reset_adapter = qla2x00_reset_adapter, 2177 .nvram_config = qla2x00_nvram_config, 2178 .update_fw_options = qla2x00_update_fw_options, 2179 .load_risc = qla2x00_load_risc, 2180 .pci_info_str = qla2x00_pci_info_str, 2181 .fw_version_str = qla2x00_fw_version_str, 2182 .intr_handler = qla2300_intr_handler, 2183 .enable_intrs = qla2x00_enable_intrs, 2184 .disable_intrs = qla2x00_disable_intrs, 2185 .abort_command = qla2x00_abort_command, 2186 .target_reset = qla2x00_abort_target, 2187 .lun_reset = qla2x00_lun_reset, 2188 .fabric_login = qla2x00_login_fabric, 2189 .fabric_logout = qla2x00_fabric_logout, 2190 .calc_req_entries = qla2x00_calc_iocbs_32, 2191 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2192 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2193 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2194 .read_nvram = qla2x00_read_nvram_data, 2195 .write_nvram = qla2x00_write_nvram_data, 2196 .fw_dump = qla2300_fw_dump, 2197 .beacon_on = qla2x00_beacon_on, 2198 .beacon_off = qla2x00_beacon_off, 2199 .beacon_blink = qla2x00_beacon_blink, 2200 .read_optrom = qla2x00_read_optrom_data, 2201 .write_optrom = qla2x00_write_optrom_data, 2202 .get_flash_version = qla2x00_get_flash_version, 2203 .start_scsi = qla2x00_start_scsi, 2204 .start_scsi_mq = NULL, 2205 .abort_isp = qla2x00_abort_isp, 2206 .iospace_config = qla2x00_iospace_config, 2207 .initialize_adapter = qla2x00_initialize_adapter, 2208}; 2209 2210static struct isp_operations qla24xx_isp_ops = { 2211 .pci_config = qla24xx_pci_config, 2212 .reset_chip = qla24xx_reset_chip, 2213 .chip_diag = qla24xx_chip_diag, 2214 .config_rings = qla24xx_config_rings, 2215 .reset_adapter = qla24xx_reset_adapter, 2216 .nvram_config = qla24xx_nvram_config, 2217 .update_fw_options = qla24xx_update_fw_options, 2218 .load_risc = qla24xx_load_risc, 2219 .pci_info_str = qla24xx_pci_info_str, 2220 .fw_version_str = qla24xx_fw_version_str, 2221 .intr_handler = qla24xx_intr_handler, 2222 .enable_intrs = qla24xx_enable_intrs, 2223 .disable_intrs = qla24xx_disable_intrs, 2224 .abort_command = qla24xx_abort_command, 2225 .target_reset = qla24xx_abort_target, 2226 .lun_reset = qla24xx_lun_reset, 2227 .fabric_login = qla24xx_login_fabric, 2228 .fabric_logout = qla24xx_fabric_logout, 2229 .calc_req_entries = NULL, 2230 .build_iocbs = NULL, 2231 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2232 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2233 .read_nvram = qla24xx_read_nvram_data, 2234 .write_nvram = qla24xx_write_nvram_data, 2235 .fw_dump = qla24xx_fw_dump, 2236 .beacon_on = qla24xx_beacon_on, 2237 .beacon_off = qla24xx_beacon_off, 2238 .beacon_blink = qla24xx_beacon_blink, 2239 .read_optrom = qla24xx_read_optrom_data, 2240 .write_optrom = qla24xx_write_optrom_data, 2241 .get_flash_version = qla24xx_get_flash_version, 2242 .start_scsi = qla24xx_start_scsi, 2243 .start_scsi_mq = NULL, 2244 .abort_isp = qla2x00_abort_isp, 2245 .iospace_config = qla2x00_iospace_config, 2246 .initialize_adapter = qla2x00_initialize_adapter, 2247}; 2248 2249static struct isp_operations qla25xx_isp_ops = { 2250 .pci_config = qla25xx_pci_config, 2251 .reset_chip = qla24xx_reset_chip, 2252 .chip_diag = qla24xx_chip_diag, 2253 .config_rings = qla24xx_config_rings, 2254 .reset_adapter = qla24xx_reset_adapter, 2255 .nvram_config = qla24xx_nvram_config, 2256 .update_fw_options = qla24xx_update_fw_options, 2257 .load_risc = qla24xx_load_risc, 2258 .pci_info_str = qla24xx_pci_info_str, 2259 .fw_version_str = qla24xx_fw_version_str, 2260 .intr_handler = qla24xx_intr_handler, 2261 .enable_intrs = qla24xx_enable_intrs, 2262 .disable_intrs = qla24xx_disable_intrs, 2263 .abort_command = qla24xx_abort_command, 2264 .target_reset = qla24xx_abort_target, 2265 .lun_reset = qla24xx_lun_reset, 2266 .fabric_login = qla24xx_login_fabric, 2267 .fabric_logout = qla24xx_fabric_logout, 2268 .calc_req_entries = NULL, 2269 .build_iocbs = NULL, 2270 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2271 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2272 .read_nvram = qla25xx_read_nvram_data, 2273 .write_nvram = qla25xx_write_nvram_data, 2274 .fw_dump = qla25xx_fw_dump, 2275 .beacon_on = qla24xx_beacon_on, 2276 .beacon_off = qla24xx_beacon_off, 2277 .beacon_blink = qla24xx_beacon_blink, 2278 .read_optrom = qla25xx_read_optrom_data, 2279 .write_optrom = qla24xx_write_optrom_data, 2280 .get_flash_version = qla24xx_get_flash_version, 2281 .start_scsi = qla24xx_dif_start_scsi, 2282 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2283 .abort_isp = qla2x00_abort_isp, 2284 .iospace_config = qla2x00_iospace_config, 2285 .initialize_adapter = qla2x00_initialize_adapter, 2286}; 2287 2288static struct isp_operations qla81xx_isp_ops = { 2289 .pci_config = qla25xx_pci_config, 2290 .reset_chip = qla24xx_reset_chip, 2291 .chip_diag = qla24xx_chip_diag, 2292 .config_rings = qla24xx_config_rings, 2293 .reset_adapter = qla24xx_reset_adapter, 2294 .nvram_config = qla81xx_nvram_config, 2295 .update_fw_options = qla24xx_update_fw_options, 2296 .load_risc = qla81xx_load_risc, 2297 .pci_info_str = qla24xx_pci_info_str, 2298 .fw_version_str = qla24xx_fw_version_str, 2299 .intr_handler = qla24xx_intr_handler, 2300 .enable_intrs = qla24xx_enable_intrs, 2301 .disable_intrs = qla24xx_disable_intrs, 2302 .abort_command = qla24xx_abort_command, 2303 .target_reset = qla24xx_abort_target, 2304 .lun_reset = qla24xx_lun_reset, 2305 .fabric_login = qla24xx_login_fabric, 2306 .fabric_logout = qla24xx_fabric_logout, 2307 .calc_req_entries = NULL, 2308 .build_iocbs = NULL, 2309 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2310 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2311 .read_nvram = NULL, 2312 .write_nvram = NULL, 2313 .fw_dump = qla81xx_fw_dump, 2314 .beacon_on = qla24xx_beacon_on, 2315 .beacon_off = qla24xx_beacon_off, 2316 .beacon_blink = qla83xx_beacon_blink, 2317 .read_optrom = qla25xx_read_optrom_data, 2318 .write_optrom = qla24xx_write_optrom_data, 2319 .get_flash_version = qla24xx_get_flash_version, 2320 .start_scsi = qla24xx_dif_start_scsi, 2321 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2322 .abort_isp = qla2x00_abort_isp, 2323 .iospace_config = qla2x00_iospace_config, 2324 .initialize_adapter = qla2x00_initialize_adapter, 2325}; 2326 2327static struct isp_operations qla82xx_isp_ops = { 2328 .pci_config = qla82xx_pci_config, 2329 .reset_chip = qla82xx_reset_chip, 2330 .chip_diag = qla24xx_chip_diag, 2331 .config_rings = qla82xx_config_rings, 2332 .reset_adapter = qla24xx_reset_adapter, 2333 .nvram_config = qla81xx_nvram_config, 2334 .update_fw_options = qla24xx_update_fw_options, 2335 .load_risc = qla82xx_load_risc, 2336 .pci_info_str = qla24xx_pci_info_str, 2337 .fw_version_str = qla24xx_fw_version_str, 2338 .intr_handler = qla82xx_intr_handler, 2339 .enable_intrs = qla82xx_enable_intrs, 2340 .disable_intrs = qla82xx_disable_intrs, 2341 .abort_command = qla24xx_abort_command, 2342 .target_reset = qla24xx_abort_target, 2343 .lun_reset = qla24xx_lun_reset, 2344 .fabric_login = qla24xx_login_fabric, 2345 .fabric_logout = qla24xx_fabric_logout, 2346 .calc_req_entries = NULL, 2347 .build_iocbs = NULL, 2348 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2349 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2350 .read_nvram = qla24xx_read_nvram_data, 2351 .write_nvram = qla24xx_write_nvram_data, 2352 .fw_dump = qla82xx_fw_dump, 2353 .beacon_on = qla82xx_beacon_on, 2354 .beacon_off = qla82xx_beacon_off, 2355 .beacon_blink = NULL, 2356 .read_optrom = qla82xx_read_optrom_data, 2357 .write_optrom = qla82xx_write_optrom_data, 2358 .get_flash_version = qla82xx_get_flash_version, 2359 .start_scsi = qla82xx_start_scsi, 2360 .start_scsi_mq = NULL, 2361 .abort_isp = qla82xx_abort_isp, 2362 .iospace_config = qla82xx_iospace_config, 2363 .initialize_adapter = qla2x00_initialize_adapter, 2364}; 2365 2366static struct isp_operations qla8044_isp_ops = { 2367 .pci_config = qla82xx_pci_config, 2368 .reset_chip = qla82xx_reset_chip, 2369 .chip_diag = qla24xx_chip_diag, 2370 .config_rings = qla82xx_config_rings, 2371 .reset_adapter = qla24xx_reset_adapter, 2372 .nvram_config = qla81xx_nvram_config, 2373 .update_fw_options = qla24xx_update_fw_options, 2374 .load_risc = qla82xx_load_risc, 2375 .pci_info_str = qla24xx_pci_info_str, 2376 .fw_version_str = qla24xx_fw_version_str, 2377 .intr_handler = qla8044_intr_handler, 2378 .enable_intrs = qla82xx_enable_intrs, 2379 .disable_intrs = qla82xx_disable_intrs, 2380 .abort_command = qla24xx_abort_command, 2381 .target_reset = qla24xx_abort_target, 2382 .lun_reset = qla24xx_lun_reset, 2383 .fabric_login = qla24xx_login_fabric, 2384 .fabric_logout = qla24xx_fabric_logout, 2385 .calc_req_entries = NULL, 2386 .build_iocbs = NULL, 2387 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2388 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2389 .read_nvram = NULL, 2390 .write_nvram = NULL, 2391 .fw_dump = qla8044_fw_dump, 2392 .beacon_on = qla82xx_beacon_on, 2393 .beacon_off = qla82xx_beacon_off, 2394 .beacon_blink = NULL, 2395 .read_optrom = qla8044_read_optrom_data, 2396 .write_optrom = qla8044_write_optrom_data, 2397 .get_flash_version = qla82xx_get_flash_version, 2398 .start_scsi = qla82xx_start_scsi, 2399 .start_scsi_mq = NULL, 2400 .abort_isp = qla8044_abort_isp, 2401 .iospace_config = qla82xx_iospace_config, 2402 .initialize_adapter = qla2x00_initialize_adapter, 2403}; 2404 2405static struct isp_operations qla83xx_isp_ops = { 2406 .pci_config = qla25xx_pci_config, 2407 .reset_chip = qla24xx_reset_chip, 2408 .chip_diag = qla24xx_chip_diag, 2409 .config_rings = qla24xx_config_rings, 2410 .reset_adapter = qla24xx_reset_adapter, 2411 .nvram_config = qla81xx_nvram_config, 2412 .update_fw_options = qla24xx_update_fw_options, 2413 .load_risc = qla81xx_load_risc, 2414 .pci_info_str = qla24xx_pci_info_str, 2415 .fw_version_str = qla24xx_fw_version_str, 2416 .intr_handler = qla24xx_intr_handler, 2417 .enable_intrs = qla24xx_enable_intrs, 2418 .disable_intrs = qla24xx_disable_intrs, 2419 .abort_command = qla24xx_abort_command, 2420 .target_reset = qla24xx_abort_target, 2421 .lun_reset = qla24xx_lun_reset, 2422 .fabric_login = qla24xx_login_fabric, 2423 .fabric_logout = qla24xx_fabric_logout, 2424 .calc_req_entries = NULL, 2425 .build_iocbs = NULL, 2426 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2427 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2428 .read_nvram = NULL, 2429 .write_nvram = NULL, 2430 .fw_dump = qla83xx_fw_dump, 2431 .beacon_on = qla24xx_beacon_on, 2432 .beacon_off = qla24xx_beacon_off, 2433 .beacon_blink = qla83xx_beacon_blink, 2434 .read_optrom = qla25xx_read_optrom_data, 2435 .write_optrom = qla24xx_write_optrom_data, 2436 .get_flash_version = qla24xx_get_flash_version, 2437 .start_scsi = qla24xx_dif_start_scsi, 2438 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2439 .abort_isp = qla2x00_abort_isp, 2440 .iospace_config = qla83xx_iospace_config, 2441 .initialize_adapter = qla2x00_initialize_adapter, 2442}; 2443 2444static struct isp_operations qlafx00_isp_ops = { 2445 .pci_config = qlafx00_pci_config, 2446 .reset_chip = qlafx00_soft_reset, 2447 .chip_diag = qlafx00_chip_diag, 2448 .config_rings = qlafx00_config_rings, 2449 .reset_adapter = qlafx00_soft_reset, 2450 .nvram_config = NULL, 2451 .update_fw_options = NULL, 2452 .load_risc = NULL, 2453 .pci_info_str = qlafx00_pci_info_str, 2454 .fw_version_str = qlafx00_fw_version_str, 2455 .intr_handler = qlafx00_intr_handler, 2456 .enable_intrs = qlafx00_enable_intrs, 2457 .disable_intrs = qlafx00_disable_intrs, 2458 .abort_command = qla24xx_async_abort_command, 2459 .target_reset = qlafx00_abort_target, 2460 .lun_reset = qlafx00_lun_reset, 2461 .fabric_login = NULL, 2462 .fabric_logout = NULL, 2463 .calc_req_entries = NULL, 2464 .build_iocbs = NULL, 2465 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2466 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2467 .read_nvram = qla24xx_read_nvram_data, 2468 .write_nvram = qla24xx_write_nvram_data, 2469 .fw_dump = NULL, 2470 .beacon_on = qla24xx_beacon_on, 2471 .beacon_off = qla24xx_beacon_off, 2472 .beacon_blink = NULL, 2473 .read_optrom = qla24xx_read_optrom_data, 2474 .write_optrom = qla24xx_write_optrom_data, 2475 .get_flash_version = qla24xx_get_flash_version, 2476 .start_scsi = qlafx00_start_scsi, 2477 .start_scsi_mq = NULL, 2478 .abort_isp = qlafx00_abort_isp, 2479 .iospace_config = qlafx00_iospace_config, 2480 .initialize_adapter = qlafx00_initialize_adapter, 2481}; 2482 2483static struct isp_operations qla27xx_isp_ops = { 2484 .pci_config = qla25xx_pci_config, 2485 .reset_chip = qla24xx_reset_chip, 2486 .chip_diag = qla24xx_chip_diag, 2487 .config_rings = qla24xx_config_rings, 2488 .reset_adapter = qla24xx_reset_adapter, 2489 .nvram_config = qla81xx_nvram_config, 2490 .update_fw_options = qla24xx_update_fw_options, 2491 .load_risc = qla81xx_load_risc, 2492 .pci_info_str = qla24xx_pci_info_str, 2493 .fw_version_str = qla24xx_fw_version_str, 2494 .intr_handler = qla24xx_intr_handler, 2495 .enable_intrs = qla24xx_enable_intrs, 2496 .disable_intrs = qla24xx_disable_intrs, 2497 .abort_command = qla24xx_abort_command, 2498 .target_reset = qla24xx_abort_target, 2499 .lun_reset = qla24xx_lun_reset, 2500 .fabric_login = qla24xx_login_fabric, 2501 .fabric_logout = qla24xx_fabric_logout, 2502 .calc_req_entries = NULL, 2503 .build_iocbs = NULL, 2504 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2505 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2506 .read_nvram = NULL, 2507 .write_nvram = NULL, 2508 .fw_dump = qla27xx_fwdump, 2509 .mpi_fw_dump = qla27xx_mpi_fwdump, 2510 .beacon_on = qla24xx_beacon_on, 2511 .beacon_off = qla24xx_beacon_off, 2512 .beacon_blink = qla83xx_beacon_blink, 2513 .read_optrom = qla25xx_read_optrom_data, 2514 .write_optrom = qla24xx_write_optrom_data, 2515 .get_flash_version = qla24xx_get_flash_version, 2516 .start_scsi = qla24xx_dif_start_scsi, 2517 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2518 .abort_isp = qla2x00_abort_isp, 2519 .iospace_config = qla83xx_iospace_config, 2520 .initialize_adapter = qla2x00_initialize_adapter, 2521}; 2522 2523static inline void 2524qla2x00_set_isp_flags(struct qla_hw_data *ha) 2525{ 2526 ha->device_type = DT_EXTENDED_IDS; 2527 switch (ha->pdev->device) { 2528 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2529 ha->isp_type |= DT_ISP2100; 2530 ha->device_type &= ~DT_EXTENDED_IDS; 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2532 break; 2533 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2534 ha->isp_type |= DT_ISP2200; 2535 ha->device_type &= ~DT_EXTENDED_IDS; 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2537 break; 2538 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2539 ha->isp_type |= DT_ISP2300; 2540 ha->device_type |= DT_ZIO_SUPPORTED; 2541 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2542 break; 2543 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2544 ha->isp_type |= DT_ISP2312; 2545 ha->device_type |= DT_ZIO_SUPPORTED; 2546 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2547 break; 2548 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2549 ha->isp_type |= DT_ISP2322; 2550 ha->device_type |= DT_ZIO_SUPPORTED; 2551 if (ha->pdev->subsystem_vendor == 0x1028 && 2552 ha->pdev->subsystem_device == 0x0170) 2553 ha->device_type |= DT_OEM_001; 2554 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2555 break; 2556 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2557 ha->isp_type |= DT_ISP6312; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2561 ha->isp_type |= DT_ISP6322; 2562 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2563 break; 2564 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2565 ha->isp_type |= DT_ISP2422; 2566 ha->device_type |= DT_ZIO_SUPPORTED; 2567 ha->device_type |= DT_FWI2; 2568 ha->device_type |= DT_IIDMA; 2569 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2570 break; 2571 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2572 ha->isp_type |= DT_ISP2432; 2573 ha->device_type |= DT_ZIO_SUPPORTED; 2574 ha->device_type |= DT_FWI2; 2575 ha->device_type |= DT_IIDMA; 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2577 break; 2578 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2579 ha->isp_type |= DT_ISP8432; 2580 ha->device_type |= DT_ZIO_SUPPORTED; 2581 ha->device_type |= DT_FWI2; 2582 ha->device_type |= DT_IIDMA; 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2584 break; 2585 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2586 ha->isp_type |= DT_ISP5422; 2587 ha->device_type |= DT_FWI2; 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2589 break; 2590 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2591 ha->isp_type |= DT_ISP5432; 2592 ha->device_type |= DT_FWI2; 2593 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2594 break; 2595 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2596 ha->isp_type |= DT_ISP2532; 2597 ha->device_type |= DT_ZIO_SUPPORTED; 2598 ha->device_type |= DT_FWI2; 2599 ha->device_type |= DT_IIDMA; 2600 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2601 break; 2602 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2603 ha->isp_type |= DT_ISP8001; 2604 ha->device_type |= DT_ZIO_SUPPORTED; 2605 ha->device_type |= DT_FWI2; 2606 ha->device_type |= DT_IIDMA; 2607 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2608 break; 2609 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2610 ha->isp_type |= DT_ISP8021; 2611 ha->device_type |= DT_ZIO_SUPPORTED; 2612 ha->device_type |= DT_FWI2; 2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2614 /* Initialize 82XX ISP flags */ 2615 qla82xx_init_flags(ha); 2616 break; 2617 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2618 ha->isp_type |= DT_ISP8044; 2619 ha->device_type |= DT_ZIO_SUPPORTED; 2620 ha->device_type |= DT_FWI2; 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2622 /* Initialize 82XX ISP flags */ 2623 qla82xx_init_flags(ha); 2624 break; 2625 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2626 ha->isp_type |= DT_ISP2031; 2627 ha->device_type |= DT_ZIO_SUPPORTED; 2628 ha->device_type |= DT_FWI2; 2629 ha->device_type |= DT_IIDMA; 2630 ha->device_type |= DT_T10_PI; 2631 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2632 break; 2633 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2634 ha->isp_type |= DT_ISP8031; 2635 ha->device_type |= DT_ZIO_SUPPORTED; 2636 ha->device_type |= DT_FWI2; 2637 ha->device_type |= DT_IIDMA; 2638 ha->device_type |= DT_T10_PI; 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2640 break; 2641 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2642 ha->isp_type |= DT_ISPFX00; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2645 ha->isp_type |= DT_ISP2071; 2646 ha->device_type |= DT_ZIO_SUPPORTED; 2647 ha->device_type |= DT_FWI2; 2648 ha->device_type |= DT_IIDMA; 2649 ha->device_type |= DT_T10_PI; 2650 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2651 break; 2652 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2653 ha->isp_type |= DT_ISP2271; 2654 ha->device_type |= DT_ZIO_SUPPORTED; 2655 ha->device_type |= DT_FWI2; 2656 ha->device_type |= DT_IIDMA; 2657 ha->device_type |= DT_T10_PI; 2658 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2659 break; 2660 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2661 ha->isp_type |= DT_ISP2261; 2662 ha->device_type |= DT_ZIO_SUPPORTED; 2663 ha->device_type |= DT_FWI2; 2664 ha->device_type |= DT_IIDMA; 2665 ha->device_type |= DT_T10_PI; 2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2667 break; 2668 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2669 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2670 ha->isp_type |= DT_ISP2081; 2671 ha->device_type |= DT_ZIO_SUPPORTED; 2672 ha->device_type |= DT_FWI2; 2673 ha->device_type |= DT_IIDMA; 2674 ha->device_type |= DT_T10_PI; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2678 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2679 ha->isp_type |= DT_ISP2281; 2680 ha->device_type |= DT_ZIO_SUPPORTED; 2681 ha->device_type |= DT_FWI2; 2682 ha->device_type |= DT_IIDMA; 2683 ha->device_type |= DT_T10_PI; 2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2685 break; 2686 } 2687 2688 if (IS_QLA82XX(ha)) 2689 ha->port_no = ha->portnum & 1; 2690 else { 2691 /* Get adapter physical port no from interrupt pin register. */ 2692 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2693 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2694 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2695 ha->port_no--; 2696 else 2697 ha->port_no = !(ha->port_no & 1); 2698 } 2699 2700 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2701 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2702 ha->device_type, ha->port_no, ha->fw_srisc_address); 2703} 2704 2705static void 2706qla2xxx_scan_start(struct Scsi_Host *shost) 2707{ 2708 scsi_qla_host_t *vha = shost_priv(shost); 2709 2710 if (vha->hw->flags.running_gold_fw) 2711 return; 2712 2713 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2714 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2715 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2716 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2717} 2718 2719static int 2720qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2721{ 2722 scsi_qla_host_t *vha = shost_priv(shost); 2723 2724 if (test_bit(UNLOADING, &vha->dpc_flags)) 2725 return 1; 2726 if (!vha->host) 2727 return 1; 2728 if (time > vha->hw->loop_reset_delay * HZ) 2729 return 1; 2730 2731 return atomic_read(&vha->loop_state) == LOOP_READY; 2732} 2733 2734static void qla2x00_iocb_work_fn(struct work_struct *work) 2735{ 2736 struct scsi_qla_host *vha = container_of(work, 2737 struct scsi_qla_host, iocb_work); 2738 struct qla_hw_data *ha = vha->hw; 2739 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2740 int i = 2; 2741 unsigned long flags; 2742 2743 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2744 return; 2745 2746 while (!list_empty(&vha->work_list) && i > 0) { 2747 qla2x00_do_work(vha); 2748 i--; 2749 } 2750 2751 spin_lock_irqsave(&vha->work_lock, flags); 2752 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2753 spin_unlock_irqrestore(&vha->work_lock, flags); 2754} 2755 2756/* 2757 * PCI driver interface 2758 */ 2759static int 2760qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2761{ 2762 int ret = -ENODEV; 2763 struct Scsi_Host *host; 2764 scsi_qla_host_t *base_vha = NULL; 2765 struct qla_hw_data *ha; 2766 char pci_info[30]; 2767 char fw_str[30], wq_name[30]; 2768 struct scsi_host_template *sht; 2769 int bars, mem_only = 0; 2770 uint16_t req_length = 0, rsp_length = 0; 2771 struct req_que *req = NULL; 2772 struct rsp_que *rsp = NULL; 2773 int i; 2774 2775 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2776 sht = &qla2xxx_driver_template; 2777 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2778 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2779 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2780 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2781 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2782 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2783 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2784 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2785 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2786 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2787 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2788 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2789 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2796 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2797 mem_only = 1; 2798 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2799 "Mem only adapter.\n"); 2800 } 2801 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2802 "Bars=%d.\n", bars); 2803 2804 if (mem_only) { 2805 if (pci_enable_device_mem(pdev)) 2806 return ret; 2807 } else { 2808 if (pci_enable_device(pdev)) 2809 return ret; 2810 } 2811 2812 if (is_kdump_kernel()) { 2813 ql2xmqsupport = 0; 2814 ql2xallocfwdump = 0; 2815 } 2816 2817 /* This may fail but that's ok */ 2818 pci_enable_pcie_error_reporting(pdev); 2819 2820 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2821 if (!ha) { 2822 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2823 "Unable to allocate memory for ha.\n"); 2824 goto disable_device; 2825 } 2826 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2827 "Memory allocated for ha=%p.\n", ha); 2828 ha->pdev = pdev; 2829 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2830 spin_lock_init(&ha->tgt.q_full_lock); 2831 spin_lock_init(&ha->tgt.sess_lock); 2832 spin_lock_init(&ha->tgt.atio_lock); 2833 2834 atomic_set(&ha->nvme_active_aen_cnt, 0); 2835 2836 /* Clear our data area */ 2837 ha->bars = bars; 2838 ha->mem_only = mem_only; 2839 spin_lock_init(&ha->hardware_lock); 2840 spin_lock_init(&ha->vport_slock); 2841 mutex_init(&ha->selflogin_lock); 2842 mutex_init(&ha->optrom_mutex); 2843 2844 /* Set ISP-type information. */ 2845 qla2x00_set_isp_flags(ha); 2846 2847 /* Set EEH reset type to fundamental if required by hba */ 2848 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2849 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2850 pdev->needs_freset = 1; 2851 2852 ha->prev_topology = 0; 2853 ha->init_cb_size = sizeof(init_cb_t); 2854 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2855 ha->optrom_size = OPTROM_SIZE_2300; 2856 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2857 atomic_set(&ha->num_pend_mbx_stage1, 0); 2858 atomic_set(&ha->num_pend_mbx_stage2, 0); 2859 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2860 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2861 2862 /* Assign ISP specific operations. */ 2863 if (IS_QLA2100(ha)) { 2864 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2865 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2866 req_length = REQUEST_ENTRY_CNT_2100; 2867 rsp_length = RESPONSE_ENTRY_CNT_2100; 2868 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2869 ha->gid_list_info_size = 4; 2870 ha->flash_conf_off = ~0; 2871 ha->flash_data_off = ~0; 2872 ha->nvram_conf_off = ~0; 2873 ha->nvram_data_off = ~0; 2874 ha->isp_ops = &qla2100_isp_ops; 2875 } else if (IS_QLA2200(ha)) { 2876 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2877 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2878 req_length = REQUEST_ENTRY_CNT_2200; 2879 rsp_length = RESPONSE_ENTRY_CNT_2100; 2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2881 ha->gid_list_info_size = 4; 2882 ha->flash_conf_off = ~0; 2883 ha->flash_data_off = ~0; 2884 ha->nvram_conf_off = ~0; 2885 ha->nvram_data_off = ~0; 2886 ha->isp_ops = &qla2100_isp_ops; 2887 } else if (IS_QLA23XX(ha)) { 2888 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2889 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2890 req_length = REQUEST_ENTRY_CNT_2200; 2891 rsp_length = RESPONSE_ENTRY_CNT_2300; 2892 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2893 ha->gid_list_info_size = 6; 2894 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2895 ha->optrom_size = OPTROM_SIZE_2322; 2896 ha->flash_conf_off = ~0; 2897 ha->flash_data_off = ~0; 2898 ha->nvram_conf_off = ~0; 2899 ha->nvram_data_off = ~0; 2900 ha->isp_ops = &qla2300_isp_ops; 2901 } else if (IS_QLA24XX_TYPE(ha)) { 2902 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2903 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2904 req_length = REQUEST_ENTRY_CNT_24XX; 2905 rsp_length = RESPONSE_ENTRY_CNT_2300; 2906 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2907 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2908 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2909 ha->gid_list_info_size = 8; 2910 ha->optrom_size = OPTROM_SIZE_24XX; 2911 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2912 ha->isp_ops = &qla24xx_isp_ops; 2913 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2914 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2915 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2916 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2917 } else if (IS_QLA25XX(ha)) { 2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2919 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2920 req_length = REQUEST_ENTRY_CNT_24XX; 2921 rsp_length = RESPONSE_ENTRY_CNT_2300; 2922 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2923 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2924 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2925 ha->gid_list_info_size = 8; 2926 ha->optrom_size = OPTROM_SIZE_25XX; 2927 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2928 ha->isp_ops = &qla25xx_isp_ops; 2929 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2930 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2931 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2932 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2933 } else if (IS_QLA81XX(ha)) { 2934 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2935 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2936 req_length = REQUEST_ENTRY_CNT_24XX; 2937 rsp_length = RESPONSE_ENTRY_CNT_2300; 2938 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2939 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2940 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2941 ha->gid_list_info_size = 8; 2942 ha->optrom_size = OPTROM_SIZE_81XX; 2943 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2944 ha->isp_ops = &qla81xx_isp_ops; 2945 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2946 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2947 ha->nvram_conf_off = ~0; 2948 ha->nvram_data_off = ~0; 2949 } else if (IS_QLA82XX(ha)) { 2950 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2951 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2952 req_length = REQUEST_ENTRY_CNT_82XX; 2953 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2954 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2955 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2956 ha->gid_list_info_size = 8; 2957 ha->optrom_size = OPTROM_SIZE_82XX; 2958 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2959 ha->isp_ops = &qla82xx_isp_ops; 2960 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2961 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2962 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2963 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2964 } else if (IS_QLA8044(ha)) { 2965 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2966 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2967 req_length = REQUEST_ENTRY_CNT_82XX; 2968 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2969 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2970 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2971 ha->gid_list_info_size = 8; 2972 ha->optrom_size = OPTROM_SIZE_83XX; 2973 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2974 ha->isp_ops = &qla8044_isp_ops; 2975 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2976 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2977 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2978 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2979 } else if (IS_QLA83XX(ha)) { 2980 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2981 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2982 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2983 req_length = REQUEST_ENTRY_CNT_83XX; 2984 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2985 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2988 ha->gid_list_info_size = 8; 2989 ha->optrom_size = OPTROM_SIZE_83XX; 2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2991 ha->isp_ops = &qla83xx_isp_ops; 2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2994 ha->nvram_conf_off = ~0; 2995 ha->nvram_data_off = ~0; 2996 } else if (IS_QLAFX00(ha)) { 2997 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2998 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2999 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3000 req_length = REQUEST_ENTRY_CNT_FX00; 3001 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3002 ha->isp_ops = &qlafx00_isp_ops; 3003 ha->port_down_retry_count = 30; /* default value */ 3004 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3005 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3006 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3007 ha->mr.fw_hbt_en = 1; 3008 ha->mr.host_info_resend = false; 3009 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3010 } else if (IS_QLA27XX(ha)) { 3011 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3012 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3013 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3014 req_length = REQUEST_ENTRY_CNT_83XX; 3015 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3016 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3017 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3018 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3019 ha->gid_list_info_size = 8; 3020 ha->optrom_size = OPTROM_SIZE_83XX; 3021 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3022 ha->isp_ops = &qla27xx_isp_ops; 3023 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3024 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3025 ha->nvram_conf_off = ~0; 3026 ha->nvram_data_off = ~0; 3027 } else if (IS_QLA28XX(ha)) { 3028 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3030 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3031 req_length = REQUEST_ENTRY_CNT_24XX; 3032 rsp_length = RESPONSE_ENTRY_CNT_2300; 3033 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3035 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3036 ha->gid_list_info_size = 8; 3037 ha->optrom_size = OPTROM_SIZE_28XX; 3038 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3039 ha->isp_ops = &qla27xx_isp_ops; 3040 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3041 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3042 ha->nvram_conf_off = ~0; 3043 ha->nvram_data_off = ~0; 3044 } 3045 3046 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3047 "mbx_count=%d, req_length=%d, " 3048 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3049 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3050 "max_fibre_devices=%d.\n", 3051 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3052 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3053 ha->nvram_npiv_size, ha->max_fibre_devices); 3054 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3055 "isp_ops=%p, flash_conf_off=%d, " 3056 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3057 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3058 ha->nvram_conf_off, ha->nvram_data_off); 3059 3060 /* Configure PCI I/O space */ 3061 ret = ha->isp_ops->iospace_config(ha); 3062 if (ret) 3063 goto iospace_config_failed; 3064 3065 ql_log_pci(ql_log_info, pdev, 0x001d, 3066 "Found an ISP%04X irq %d iobase 0x%p.\n", 3067 pdev->device, pdev->irq, ha->iobase); 3068 mutex_init(&ha->vport_lock); 3069 mutex_init(&ha->mq_lock); 3070 init_completion(&ha->mbx_cmd_comp); 3071 complete(&ha->mbx_cmd_comp); 3072 init_completion(&ha->mbx_intr_comp); 3073 init_completion(&ha->dcbx_comp); 3074 init_completion(&ha->lb_portup_comp); 3075 3076 set_bit(0, (unsigned long *) ha->vp_idx_map); 3077 3078 qla2x00_config_dma_addressing(ha); 3079 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3080 "64 Bit addressing is %s.\n", 3081 ha->flags.enable_64bit_addressing ? "enable" : 3082 "disable"); 3083 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3084 if (ret) { 3085 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3086 "Failed to allocate memory for adapter, aborting.\n"); 3087 3088 goto probe_hw_failed; 3089 } 3090 3091 req->max_q_depth = MAX_Q_DEPTH; 3092 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3093 req->max_q_depth = ql2xmaxqdepth; 3094 3095 3096 base_vha = qla2x00_create_host(sht, ha); 3097 if (!base_vha) { 3098 ret = -ENOMEM; 3099 goto probe_hw_failed; 3100 } 3101 3102 pci_set_drvdata(pdev, base_vha); 3103 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3104 3105 host = base_vha->host; 3106 base_vha->req = req; 3107 if (IS_QLA2XXX_MIDTYPE(ha)) 3108 base_vha->mgmt_svr_loop_id = 3109 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3110 else 3111 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3112 base_vha->vp_idx; 3113 3114 /* Setup fcport template structure. */ 3115 ha->mr.fcport.vha = base_vha; 3116 ha->mr.fcport.port_type = FCT_UNKNOWN; 3117 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3118 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3119 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3120 ha->mr.fcport.scan_state = 1; 3121 3122 /* Set the SG table size based on ISP type */ 3123 if (!IS_FWI2_CAPABLE(ha)) { 3124 if (IS_QLA2100(ha)) 3125 host->sg_tablesize = 32; 3126 } else { 3127 if (!IS_QLA82XX(ha)) 3128 host->sg_tablesize = QLA_SG_ALL; 3129 } 3130 host->max_id = ha->max_fibre_devices; 3131 host->cmd_per_lun = 3; 3132 host->unique_id = host->host_no; 3133 3134 if (ql2xenabledif && ql2xenabledif != 2) { 3135 ql_log(ql_log_warn, base_vha, 0x302d, 3136 "Invalid value for ql2xenabledif, resetting it to default (2)\n"); 3137 ql2xenabledif = 2; 3138 } 3139 3140 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3141 host->max_cmd_len = 32; 3142 else 3143 host->max_cmd_len = MAX_CMDSZ; 3144 host->max_channel = MAX_BUSES - 1; 3145 /* Older HBAs support only 16-bit LUNs */ 3146 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3147 ql2xmaxlun > 0xffff) 3148 host->max_lun = 0xffff; 3149 else 3150 host->max_lun = ql2xmaxlun; 3151 host->transportt = qla2xxx_transport_template; 3152 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3153 3154 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3155 "max_id=%d this_id=%d " 3156 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3157 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3158 host->this_id, host->cmd_per_lun, host->unique_id, 3159 host->max_cmd_len, host->max_channel, host->max_lun, 3160 host->transportt, sht->vendor_id); 3161 3162 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3163 3164 /* Set up the irqs */ 3165 ret = qla2x00_request_irqs(ha, rsp); 3166 if (ret) 3167 goto probe_failed; 3168 3169 /* Alloc arrays of request and response ring ptrs */ 3170 ret = qla2x00_alloc_queues(ha, req, rsp); 3171 if (ret) { 3172 ql_log(ql_log_fatal, base_vha, 0x003d, 3173 "Failed to allocate memory for queue pointers..." 3174 "aborting.\n"); 3175 ret = -ENODEV; 3176 goto probe_failed; 3177 } 3178 3179 if (ha->mqenable) { 3180 /* number of hardware queues supported by blk/scsi-mq*/ 3181 host->nr_hw_queues = ha->max_qpairs; 3182 3183 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3184 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3185 } else { 3186 if (ql2xnvmeenable) { 3187 host->nr_hw_queues = ha->max_qpairs; 3188 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3189 "FC-NVMe support is enabled, HW queues=%d\n", 3190 host->nr_hw_queues); 3191 } else { 3192 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3193 "blk/scsi-mq disabled.\n"); 3194 } 3195 } 3196 3197 qlt_probe_one_stage1(base_vha, ha); 3198 3199 pci_save_state(pdev); 3200 3201 /* Assign back pointers */ 3202 rsp->req = req; 3203 req->rsp = rsp; 3204 3205 if (IS_QLAFX00(ha)) { 3206 ha->rsp_q_map[0] = rsp; 3207 ha->req_q_map[0] = req; 3208 set_bit(0, ha->req_qid_map); 3209 set_bit(0, ha->rsp_qid_map); 3210 } 3211 3212 /* FWI2-capable only. */ 3213 req->req_q_in = &ha->iobase->isp24.req_q_in; 3214 req->req_q_out = &ha->iobase->isp24.req_q_out; 3215 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3216 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3217 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3218 IS_QLA28XX(ha)) { 3219 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3220 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3221 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3222 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3223 } 3224 3225 if (IS_QLAFX00(ha)) { 3226 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3227 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3228 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3229 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3230 } 3231 3232 if (IS_P3P_TYPE(ha)) { 3233 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3234 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3235 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3236 } 3237 3238 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3239 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3240 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3241 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3242 "req->req_q_in=%p req->req_q_out=%p " 3243 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3244 req->req_q_in, req->req_q_out, 3245 rsp->rsp_q_in, rsp->rsp_q_out); 3246 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3247 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3248 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3249 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3250 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3251 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3252 3253 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3254 if (unlikely(!ha->wq)) { 3255 ret = -ENOMEM; 3256 goto probe_failed; 3257 } 3258 3259 if (ha->isp_ops->initialize_adapter(base_vha)) { 3260 ql_log(ql_log_fatal, base_vha, 0x00d6, 3261 "Failed to initialize adapter - Adapter flags %x.\n", 3262 base_vha->device_flags); 3263 3264 if (IS_QLA82XX(ha)) { 3265 qla82xx_idc_lock(ha); 3266 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3267 QLA8XXX_DEV_FAILED); 3268 qla82xx_idc_unlock(ha); 3269 ql_log(ql_log_fatal, base_vha, 0x00d7, 3270 "HW State: FAILED.\n"); 3271 } else if (IS_QLA8044(ha)) { 3272 qla8044_idc_lock(ha); 3273 qla8044_wr_direct(base_vha, 3274 QLA8044_CRB_DEV_STATE_INDEX, 3275 QLA8XXX_DEV_FAILED); 3276 qla8044_idc_unlock(ha); 3277 ql_log(ql_log_fatal, base_vha, 0x0150, 3278 "HW State: FAILED.\n"); 3279 } 3280 3281 ret = -ENODEV; 3282 goto probe_failed; 3283 } 3284 3285 if (IS_QLAFX00(ha)) 3286 host->can_queue = QLAFX00_MAX_CANQUEUE; 3287 else 3288 host->can_queue = req->num_outstanding_cmds - 10; 3289 3290 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3291 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3292 host->can_queue, base_vha->req, 3293 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3294 3295 if (ha->mqenable) { 3296 bool startit = false; 3297 3298 if (QLA_TGT_MODE_ENABLED()) 3299 startit = false; 3300 3301 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3302 startit = true; 3303 3304 /* Create start of day qpairs for Block MQ */ 3305 for (i = 0; i < ha->max_qpairs; i++) 3306 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3307 } 3308 qla_init_iocb_limit(base_vha); 3309 3310 if (ha->flags.running_gold_fw) 3311 goto skip_dpc; 3312 3313 /* 3314 * Startup the kernel thread for this host adapter 3315 */ 3316 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3317 "%s_dpc", base_vha->host_str); 3318 if (IS_ERR(ha->dpc_thread)) { 3319 ql_log(ql_log_fatal, base_vha, 0x00ed, 3320 "Failed to start DPC thread.\n"); 3321 ret = PTR_ERR(ha->dpc_thread); 3322 ha->dpc_thread = NULL; 3323 goto probe_failed; 3324 } 3325 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3326 "DPC thread started successfully.\n"); 3327 3328 /* 3329 * If we're not coming up in initiator mode, we might sit for 3330 * a while without waking up the dpc thread, which leads to a 3331 * stuck process warning. So just kick the dpc once here and 3332 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3333 */ 3334 qla2xxx_wake_dpc(base_vha); 3335 3336 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3337 3338 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3339 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3340 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3341 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3342 3343 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3344 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3345 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3346 INIT_WORK(&ha->idc_state_handler, 3347 qla83xx_idc_state_handler_work); 3348 INIT_WORK(&ha->nic_core_unrecoverable, 3349 qla83xx_nic_core_unrecoverable_work); 3350 } 3351 3352skip_dpc: 3353 list_add_tail(&base_vha->list, &ha->vp_list); 3354 base_vha->host->irq = ha->pdev->irq; 3355 3356 /* Initialized the timer */ 3357 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3358 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3359 "Started qla2x00_timer with " 3360 "interval=%d.\n", WATCH_INTERVAL); 3361 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3362 "Detected hba at address=%p.\n", 3363 ha); 3364 3365 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3366 if (ha->fw_attributes & BIT_4) { 3367 int prot = 0, guard; 3368 3369 base_vha->flags.difdix_supported = 1; 3370 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3371 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3372 if (ql2xprotmask) 3373 scsi_host_set_prot(host, ql2xprotmask); 3374 else 3375 scsi_host_set_prot(host, 3376 prot | SHOST_DIF_TYPE1_PROTECTION 3377 | SHOST_DIF_TYPE2_PROTECTION 3378 | SHOST_DIF_TYPE3_PROTECTION 3379 | SHOST_DIX_TYPE1_PROTECTION 3380 | SHOST_DIX_TYPE2_PROTECTION 3381 | SHOST_DIX_TYPE3_PROTECTION); 3382 3383 guard = SHOST_DIX_GUARD_CRC; 3384 3385 if (IS_PI_IPGUARD_CAPABLE(ha) && 3386 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3387 guard |= SHOST_DIX_GUARD_IP; 3388 3389 if (ql2xprotguard) 3390 scsi_host_set_guard(host, ql2xprotguard); 3391 else 3392 scsi_host_set_guard(host, guard); 3393 } else 3394 base_vha->flags.difdix_supported = 0; 3395 } 3396 3397 ha->isp_ops->enable_intrs(ha); 3398 3399 if (IS_QLAFX00(ha)) { 3400 ret = qlafx00_fx_disc(base_vha, 3401 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3402 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3403 QLA_SG_ALL : 128; 3404 } 3405 3406 ret = scsi_add_host(host, &pdev->dev); 3407 if (ret) 3408 goto probe_failed; 3409 3410 base_vha->flags.init_done = 1; 3411 base_vha->flags.online = 1; 3412 ha->prev_minidump_failed = 0; 3413 3414 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3415 "Init done and hba is online.\n"); 3416 3417 if (qla_ini_mode_enabled(base_vha) || 3418 qla_dual_mode_enabled(base_vha)) 3419 scsi_scan_host(host); 3420 else 3421 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3422 "skipping scsi_scan_host() for non-initiator port\n"); 3423 3424 qla2x00_alloc_sysfs_attr(base_vha); 3425 3426 if (IS_QLAFX00(ha)) { 3427 ret = qlafx00_fx_disc(base_vha, 3428 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3429 3430 /* Register system information */ 3431 ret = qlafx00_fx_disc(base_vha, 3432 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3433 } 3434 3435 qla2x00_init_host_attr(base_vha); 3436 3437 qla2x00_dfs_setup(base_vha); 3438 3439 ql_log(ql_log_info, base_vha, 0x00fb, 3440 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3441 ql_log(ql_log_info, base_vha, 0x00fc, 3442 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3443 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3444 sizeof(pci_info)), 3445 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3446 base_vha->host_no, 3447 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3448 3449 qlt_add_target(ha, base_vha); 3450 3451 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3452 3453 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3454 return -ENODEV; 3455 3456 return 0; 3457 3458probe_failed: 3459 if (base_vha->gnl.l) { 3460 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3461 base_vha->gnl.l, base_vha->gnl.ldma); 3462 base_vha->gnl.l = NULL; 3463 } 3464 3465 if (base_vha->timer_active) 3466 qla2x00_stop_timer(base_vha); 3467 base_vha->flags.online = 0; 3468 if (ha->dpc_thread) { 3469 struct task_struct *t = ha->dpc_thread; 3470 3471 ha->dpc_thread = NULL; 3472 kthread_stop(t); 3473 } 3474 3475 qla2x00_free_device(base_vha); 3476 scsi_host_put(base_vha->host); 3477 /* 3478 * Need to NULL out local req/rsp after 3479 * qla2x00_free_device => qla2x00_free_queues frees 3480 * what these are pointing to. Or else we'll 3481 * fall over below in qla2x00_free_req/rsp_que. 3482 */ 3483 req = NULL; 3484 rsp = NULL; 3485 3486probe_hw_failed: 3487 qla2x00_mem_free(ha); 3488 qla2x00_free_req_que(ha, req); 3489 qla2x00_free_rsp_que(ha, rsp); 3490 qla2x00_clear_drv_active(ha); 3491 3492iospace_config_failed: 3493 if (IS_P3P_TYPE(ha)) { 3494 if (!ha->nx_pcibase) 3495 iounmap((device_reg_t *)ha->nx_pcibase); 3496 if (!ql2xdbwr) 3497 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3498 } else { 3499 if (ha->iobase) 3500 iounmap(ha->iobase); 3501 if (ha->cregbase) 3502 iounmap(ha->cregbase); 3503 } 3504 pci_release_selected_regions(ha->pdev, ha->bars); 3505 kfree(ha); 3506 3507disable_device: 3508 pci_disable_device(pdev); 3509 return ret; 3510} 3511 3512static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3513{ 3514 scsi_qla_host_t *vp; 3515 unsigned long flags; 3516 struct qla_hw_data *ha; 3517 3518 if (!base_vha) 3519 return; 3520 3521 ha = base_vha->hw; 3522 3523 spin_lock_irqsave(&ha->vport_slock, flags); 3524 list_for_each_entry(vp, &ha->vp_list, list) 3525 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3526 3527 /* 3528 * Indicate device removal to prevent future board_disable 3529 * and wait until any pending board_disable has completed. 3530 */ 3531 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3532 spin_unlock_irqrestore(&ha->vport_slock, flags); 3533} 3534 3535static void 3536qla2x00_shutdown(struct pci_dev *pdev) 3537{ 3538 scsi_qla_host_t *vha; 3539 struct qla_hw_data *ha; 3540 3541 vha = pci_get_drvdata(pdev); 3542 ha = vha->hw; 3543 3544 ql_log(ql_log_info, vha, 0xfffa, 3545 "Adapter shutdown\n"); 3546 3547 /* 3548 * Prevent future board_disable and wait 3549 * until any pending board_disable has completed. 3550 */ 3551 __qla_set_remove_flag(vha); 3552 cancel_work_sync(&ha->board_disable); 3553 3554 if (!atomic_read(&pdev->enable_cnt)) 3555 return; 3556 3557 /* Notify ISPFX00 firmware */ 3558 if (IS_QLAFX00(ha)) 3559 qlafx00_driver_shutdown(vha, 20); 3560 3561 /* Turn-off FCE trace */ 3562 if (ha->flags.fce_enabled) { 3563 qla2x00_disable_fce_trace(vha, NULL, NULL); 3564 ha->flags.fce_enabled = 0; 3565 } 3566 3567 /* Turn-off EFT trace */ 3568 if (ha->eft) 3569 qla2x00_disable_eft_trace(vha); 3570 3571 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3572 IS_QLA28XX(ha)) { 3573 if (ha->flags.fw_started) 3574 qla2x00_abort_isp_cleanup(vha); 3575 } else { 3576 /* Stop currently executing firmware. */ 3577 qla2x00_try_to_stop_firmware(vha); 3578 } 3579 3580 /* Disable timer */ 3581 if (vha->timer_active) 3582 qla2x00_stop_timer(vha); 3583 3584 /* Turn adapter off line */ 3585 vha->flags.online = 0; 3586 3587 /* turn-off interrupts on the card */ 3588 if (ha->interrupts_on) { 3589 vha->flags.init_done = 0; 3590 ha->isp_ops->disable_intrs(ha); 3591 } 3592 3593 qla2x00_free_irqs(vha); 3594 3595 qla2x00_free_fw_dump(ha); 3596 3597 pci_disable_device(pdev); 3598 ql_log(ql_log_info, vha, 0xfffe, 3599 "Adapter shutdown successfully.\n"); 3600} 3601 3602/* Deletes all the virtual ports for a given ha */ 3603static void 3604qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3605{ 3606 scsi_qla_host_t *vha; 3607 unsigned long flags; 3608 3609 mutex_lock(&ha->vport_lock); 3610 while (ha->cur_vport_count) { 3611 spin_lock_irqsave(&ha->vport_slock, flags); 3612 3613 BUG_ON(base_vha->list.next == &ha->vp_list); 3614 /* This assumes first entry in ha->vp_list is always base vha */ 3615 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3616 scsi_host_get(vha->host); 3617 3618 spin_unlock_irqrestore(&ha->vport_slock, flags); 3619 mutex_unlock(&ha->vport_lock); 3620 3621 qla_nvme_delete(vha); 3622 3623 fc_vport_terminate(vha->fc_vport); 3624 scsi_host_put(vha->host); 3625 3626 mutex_lock(&ha->vport_lock); 3627 } 3628 mutex_unlock(&ha->vport_lock); 3629} 3630 3631/* Stops all deferred work threads */ 3632static void 3633qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3634{ 3635 /* Cancel all work and destroy DPC workqueues */ 3636 if (ha->dpc_lp_wq) { 3637 cancel_work_sync(&ha->idc_aen); 3638 destroy_workqueue(ha->dpc_lp_wq); 3639 ha->dpc_lp_wq = NULL; 3640 } 3641 3642 if (ha->dpc_hp_wq) { 3643 cancel_work_sync(&ha->nic_core_reset); 3644 cancel_work_sync(&ha->idc_state_handler); 3645 cancel_work_sync(&ha->nic_core_unrecoverable); 3646 destroy_workqueue(ha->dpc_hp_wq); 3647 ha->dpc_hp_wq = NULL; 3648 } 3649 3650 /* Kill the kernel thread for this host */ 3651 if (ha->dpc_thread) { 3652 struct task_struct *t = ha->dpc_thread; 3653 3654 /* 3655 * qla2xxx_wake_dpc checks for ->dpc_thread 3656 * so we need to zero it out. 3657 */ 3658 ha->dpc_thread = NULL; 3659 kthread_stop(t); 3660 } 3661} 3662 3663static void 3664qla2x00_unmap_iobases(struct qla_hw_data *ha) 3665{ 3666 if (IS_QLA82XX(ha)) { 3667 3668 iounmap((device_reg_t *)ha->nx_pcibase); 3669 if (!ql2xdbwr) 3670 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3671 } else { 3672 if (ha->iobase) 3673 iounmap(ha->iobase); 3674 3675 if (ha->cregbase) 3676 iounmap(ha->cregbase); 3677 3678 if (ha->mqiobase) 3679 iounmap(ha->mqiobase); 3680 3681 if (ha->msixbase) 3682 iounmap(ha->msixbase); 3683 } 3684} 3685 3686static void 3687qla2x00_clear_drv_active(struct qla_hw_data *ha) 3688{ 3689 if (IS_QLA8044(ha)) { 3690 qla8044_idc_lock(ha); 3691 qla8044_clear_drv_active(ha); 3692 qla8044_idc_unlock(ha); 3693 } else if (IS_QLA82XX(ha)) { 3694 qla82xx_idc_lock(ha); 3695 qla82xx_clear_drv_active(ha); 3696 qla82xx_idc_unlock(ha); 3697 } 3698} 3699 3700static void 3701qla2x00_remove_one(struct pci_dev *pdev) 3702{ 3703 scsi_qla_host_t *base_vha; 3704 struct qla_hw_data *ha; 3705 3706 base_vha = pci_get_drvdata(pdev); 3707 ha = base_vha->hw; 3708 ql_log(ql_log_info, base_vha, 0xb079, 3709 "Removing driver\n"); 3710 __qla_set_remove_flag(base_vha); 3711 cancel_work_sync(&ha->board_disable); 3712 3713 /* 3714 * If the PCI device is disabled then there was a PCI-disconnect and 3715 * qla2x00_disable_board_on_pci_error has taken care of most of the 3716 * resources. 3717 */ 3718 if (!atomic_read(&pdev->enable_cnt)) { 3719 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3720 base_vha->gnl.l, base_vha->gnl.ldma); 3721 base_vha->gnl.l = NULL; 3722 scsi_host_put(base_vha->host); 3723 kfree(ha); 3724 pci_set_drvdata(pdev, NULL); 3725 return; 3726 } 3727 qla2x00_wait_for_hba_ready(base_vha); 3728 3729 /* 3730 * if UNLOADING flag is already set, then continue unload, 3731 * where it was set first. 3732 */ 3733 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3734 return; 3735 3736 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3737 IS_QLA28XX(ha)) { 3738 if (ha->flags.fw_started) 3739 qla2x00_abort_isp_cleanup(base_vha); 3740 } else if (!IS_QLAFX00(ha)) { 3741 if (IS_QLA8031(ha)) { 3742 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3743 "Clearing fcoe driver presence.\n"); 3744 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3745 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3746 "Error while clearing DRV-Presence.\n"); 3747 } 3748 3749 qla2x00_try_to_stop_firmware(base_vha); 3750 } 3751 3752 qla2x00_wait_for_sess_deletion(base_vha); 3753 3754 qla_nvme_delete(base_vha); 3755 3756 dma_free_coherent(&ha->pdev->dev, 3757 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3758 3759 base_vha->gnl.l = NULL; 3760 3761 vfree(base_vha->scan.l); 3762 3763 if (IS_QLAFX00(ha)) 3764 qlafx00_driver_shutdown(base_vha, 20); 3765 3766 qla2x00_delete_all_vps(ha, base_vha); 3767 3768 qla2x00_dfs_remove(base_vha); 3769 3770 qla84xx_put_chip(base_vha); 3771 3772 /* Disable timer */ 3773 if (base_vha->timer_active) 3774 qla2x00_stop_timer(base_vha); 3775 3776 base_vha->flags.online = 0; 3777 3778 /* free DMA memory */ 3779 if (ha->exlogin_buf) 3780 qla2x00_free_exlogin_buffer(ha); 3781 3782 /* free DMA memory */ 3783 if (ha->exchoffld_buf) 3784 qla2x00_free_exchoffld_buffer(ha); 3785 3786 qla2x00_destroy_deferred_work(ha); 3787 3788 qlt_remove_target(ha, base_vha); 3789 3790 qla2x00_free_sysfs_attr(base_vha, true); 3791 3792 fc_remove_host(base_vha->host); 3793 qlt_remove_target_resources(ha); 3794 3795 scsi_remove_host(base_vha->host); 3796 3797 qla2x00_free_device(base_vha); 3798 3799 qla2x00_clear_drv_active(ha); 3800 3801 scsi_host_put(base_vha->host); 3802 3803 qla2x00_unmap_iobases(ha); 3804 3805 pci_release_selected_regions(ha->pdev, ha->bars); 3806 kfree(ha); 3807 3808 pci_disable_pcie_error_reporting(pdev); 3809 3810 pci_disable_device(pdev); 3811} 3812 3813static inline void 3814qla24xx_free_purex_list(struct purex_list *list) 3815{ 3816 struct list_head *item, *next; 3817 ulong flags; 3818 3819 spin_lock_irqsave(&list->lock, flags); 3820 list_for_each_safe(item, next, &list->head) { 3821 list_del(item); 3822 kfree(list_entry(item, struct purex_item, list)); 3823 } 3824 spin_unlock_irqrestore(&list->lock, flags); 3825} 3826 3827static void 3828qla2x00_free_device(scsi_qla_host_t *vha) 3829{ 3830 struct qla_hw_data *ha = vha->hw; 3831 3832 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3833 3834 /* Disable timer */ 3835 if (vha->timer_active) 3836 qla2x00_stop_timer(vha); 3837 3838 qla25xx_delete_queues(vha); 3839 vha->flags.online = 0; 3840 3841 /* turn-off interrupts on the card */ 3842 if (ha->interrupts_on) { 3843 vha->flags.init_done = 0; 3844 ha->isp_ops->disable_intrs(ha); 3845 } 3846 3847 qla2x00_free_fcports(vha); 3848 3849 qla2x00_free_irqs(vha); 3850 3851 /* Flush the work queue and remove it */ 3852 if (ha->wq) { 3853 flush_workqueue(ha->wq); 3854 destroy_workqueue(ha->wq); 3855 ha->wq = NULL; 3856 } 3857 3858 3859 qla24xx_free_purex_list(&vha->purex_list); 3860 3861 qla2x00_mem_free(ha); 3862 3863 qla82xx_md_free(vha); 3864 3865 qla2x00_free_queues(ha); 3866} 3867 3868void qla2x00_free_fcports(struct scsi_qla_host *vha) 3869{ 3870 fc_port_t *fcport, *tfcport; 3871 3872 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3873 qla2x00_free_fcport(fcport); 3874} 3875 3876static inline void 3877qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3878{ 3879 int now; 3880 3881 if (!fcport->rport) 3882 return; 3883 3884 if (fcport->rport) { 3885 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3886 "%s %8phN. rport %p roles %x\n", 3887 __func__, fcport->port_name, fcport->rport, 3888 fcport->rport->roles); 3889 fc_remote_port_delete(fcport->rport); 3890 } 3891 qlt_do_generation_tick(vha, &now); 3892} 3893 3894/* 3895 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3896 * 3897 * Input: ha = adapter block pointer. fcport = port structure pointer. 3898 * 3899 * Return: None. 3900 * 3901 * Context: 3902 */ 3903void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3904 int do_login) 3905{ 3906 if (IS_QLAFX00(vha->hw)) { 3907 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3908 qla2x00_schedule_rport_del(vha, fcport); 3909 return; 3910 } 3911 3912 if (atomic_read(&fcport->state) == FCS_ONLINE && 3913 vha->vp_idx == fcport->vha->vp_idx) { 3914 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3915 qla2x00_schedule_rport_del(vha, fcport); 3916 } 3917 /* 3918 * We may need to retry the login, so don't change the state of the 3919 * port but do the retries. 3920 */ 3921 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3922 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3923 3924 if (!do_login) 3925 return; 3926 3927 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3928} 3929 3930void 3931qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 3932{ 3933 fc_port_t *fcport; 3934 3935 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3936 "Mark all dev lost\n"); 3937 3938 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3939 if (fcport->loop_id != FC_NO_LOOP_ID && 3940 (fcport->flags & FCF_FCP2_DEVICE) && 3941 fcport->port_type == FCT_TARGET && 3942 !qla2x00_reset_active(vha)) { 3943 ql_dbg(ql_dbg_disc, vha, 0x211a, 3944 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 3945 fcport->flags, fcport->port_type, 3946 fcport->d_id.b24, fcport->port_name); 3947 continue; 3948 } 3949 fcport->scan_state = 0; 3950 qlt_schedule_sess_for_deletion(fcport); 3951 } 3952} 3953 3954static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3955{ 3956 int i; 3957 3958 if (IS_FWI2_CAPABLE(ha)) 3959 return; 3960 3961 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3962 set_bit(i, ha->loop_id_map); 3963 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3964 set_bit(BROADCAST, ha->loop_id_map); 3965} 3966 3967/* 3968* qla2x00_mem_alloc 3969* Allocates adapter memory. 3970* 3971* Returns: 3972* 0 = success. 3973* !0 = failure. 3974*/ 3975static int 3976qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3977 struct req_que **req, struct rsp_que **rsp) 3978{ 3979 char name[16]; 3980 3981 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3982 &ha->init_cb_dma, GFP_KERNEL); 3983 if (!ha->init_cb) 3984 goto fail; 3985 3986 if (qlt_mem_alloc(ha) < 0) 3987 goto fail_free_init_cb; 3988 3989 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3990 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3991 if (!ha->gid_list) 3992 goto fail_free_tgt_mem; 3993 3994 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3995 if (!ha->srb_mempool) 3996 goto fail_free_gid_list; 3997 3998 if (IS_P3P_TYPE(ha)) { 3999 /* Allocate cache for CT6 Ctx. */ 4000 if (!ctx_cachep) { 4001 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4002 sizeof(struct ct6_dsd), 0, 4003 SLAB_HWCACHE_ALIGN, NULL); 4004 if (!ctx_cachep) 4005 goto fail_free_srb_mempool; 4006 } 4007 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4008 ctx_cachep); 4009 if (!ha->ctx_mempool) 4010 goto fail_free_srb_mempool; 4011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4012 "ctx_cachep=%p ctx_mempool=%p.\n", 4013 ctx_cachep, ha->ctx_mempool); 4014 } 4015 4016 /* Get memory for cached NVRAM */ 4017 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4018 if (!ha->nvram) 4019 goto fail_free_ctx_mempool; 4020 4021 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4022 ha->pdev->device); 4023 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4024 DMA_POOL_SIZE, 8, 0); 4025 if (!ha->s_dma_pool) 4026 goto fail_free_nvram; 4027 4028 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4029 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4030 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4031 4032 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4033 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4034 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4035 if (!ha->dl_dma_pool) { 4036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4037 "Failed to allocate memory for dl_dma_pool.\n"); 4038 goto fail_s_dma_pool; 4039 } 4040 4041 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4042 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4043 if (!ha->fcp_cmnd_dma_pool) { 4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4045 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4046 goto fail_dl_dma_pool; 4047 } 4048 4049 if (ql2xenabledif) { 4050 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4051 struct dsd_dma *dsd, *nxt; 4052 uint i; 4053 /* Creata a DMA pool of buffers for DIF bundling */ 4054 ha->dif_bundl_pool = dma_pool_create(name, 4055 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4056 if (!ha->dif_bundl_pool) { 4057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4058 "%s: failed create dif_bundl_pool\n", 4059 __func__); 4060 goto fail_dif_bundl_dma_pool; 4061 } 4062 4063 INIT_LIST_HEAD(&ha->pool.good.head); 4064 INIT_LIST_HEAD(&ha->pool.unusable.head); 4065 ha->pool.good.count = 0; 4066 ha->pool.unusable.count = 0; 4067 for (i = 0; i < 128; i++) { 4068 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4069 if (!dsd) { 4070 ql_dbg_pci(ql_dbg_init, ha->pdev, 4071 0xe0ee, "%s: failed alloc dsd\n", 4072 __func__); 4073 return -ENOMEM; 4074 } 4075 ha->dif_bundle_kallocs++; 4076 4077 dsd->dsd_addr = dma_pool_alloc( 4078 ha->dif_bundl_pool, GFP_ATOMIC, 4079 &dsd->dsd_list_dma); 4080 if (!dsd->dsd_addr) { 4081 ql_dbg_pci(ql_dbg_init, ha->pdev, 4082 0xe0ee, 4083 "%s: failed alloc ->dsd_addr\n", 4084 __func__); 4085 kfree(dsd); 4086 ha->dif_bundle_kallocs--; 4087 continue; 4088 } 4089 ha->dif_bundle_dma_allocs++; 4090 4091 /* 4092 * if DMA buffer crosses 4G boundary, 4093 * put it on bad list 4094 */ 4095 if (MSD(dsd->dsd_list_dma) ^ 4096 MSD(dsd->dsd_list_dma + bufsize)) { 4097 list_add_tail(&dsd->list, 4098 &ha->pool.unusable.head); 4099 ha->pool.unusable.count++; 4100 } else { 4101 list_add_tail(&dsd->list, 4102 &ha->pool.good.head); 4103 ha->pool.good.count++; 4104 } 4105 } 4106 4107 /* return the good ones back to the pool */ 4108 list_for_each_entry_safe(dsd, nxt, 4109 &ha->pool.good.head, list) { 4110 list_del(&dsd->list); 4111 dma_pool_free(ha->dif_bundl_pool, 4112 dsd->dsd_addr, dsd->dsd_list_dma); 4113 ha->dif_bundle_dma_allocs--; 4114 kfree(dsd); 4115 ha->dif_bundle_kallocs--; 4116 } 4117 4118 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4119 "%s: dif dma pool (good=%u unusable=%u)\n", 4120 __func__, ha->pool.good.count, 4121 ha->pool.unusable.count); 4122 } 4123 4124 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4125 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4126 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4127 ha->dif_bundl_pool); 4128 } 4129 4130 /* Allocate memory for SNS commands */ 4131 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4132 /* Get consistent memory allocated for SNS commands */ 4133 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4134 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4135 if (!ha->sns_cmd) 4136 goto fail_dma_pool; 4137 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4138 "sns_cmd: %p.\n", ha->sns_cmd); 4139 } else { 4140 /* Get consistent memory allocated for MS IOCB */ 4141 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4142 &ha->ms_iocb_dma); 4143 if (!ha->ms_iocb) 4144 goto fail_dma_pool; 4145 /* Get consistent memory allocated for CT SNS commands */ 4146 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4147 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4148 if (!ha->ct_sns) 4149 goto fail_free_ms_iocb; 4150 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4151 "ms_iocb=%p ct_sns=%p.\n", 4152 ha->ms_iocb, ha->ct_sns); 4153 } 4154 4155 /* Allocate memory for request ring */ 4156 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4157 if (!*req) { 4158 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4159 "Failed to allocate memory for req.\n"); 4160 goto fail_req; 4161 } 4162 (*req)->length = req_len; 4163 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4164 ((*req)->length + 1) * sizeof(request_t), 4165 &(*req)->dma, GFP_KERNEL); 4166 if (!(*req)->ring) { 4167 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4168 "Failed to allocate memory for req_ring.\n"); 4169 goto fail_req_ring; 4170 } 4171 /* Allocate memory for response ring */ 4172 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4173 if (!*rsp) { 4174 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4175 "Failed to allocate memory for rsp.\n"); 4176 goto fail_rsp; 4177 } 4178 (*rsp)->hw = ha; 4179 (*rsp)->length = rsp_len; 4180 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4181 ((*rsp)->length + 1) * sizeof(response_t), 4182 &(*rsp)->dma, GFP_KERNEL); 4183 if (!(*rsp)->ring) { 4184 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4185 "Failed to allocate memory for rsp_ring.\n"); 4186 goto fail_rsp_ring; 4187 } 4188 (*req)->rsp = *rsp; 4189 (*rsp)->req = *req; 4190 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4191 "req=%p req->length=%d req->ring=%p rsp=%p " 4192 "rsp->length=%d rsp->ring=%p.\n", 4193 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4194 (*rsp)->ring); 4195 /* Allocate memory for NVRAM data for vports */ 4196 if (ha->nvram_npiv_size) { 4197 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4198 sizeof(struct qla_npiv_entry), 4199 GFP_KERNEL); 4200 if (!ha->npiv_info) { 4201 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4202 "Failed to allocate memory for npiv_info.\n"); 4203 goto fail_npiv_info; 4204 } 4205 } else 4206 ha->npiv_info = NULL; 4207 4208 /* Get consistent memory allocated for EX-INIT-CB. */ 4209 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4210 IS_QLA28XX(ha)) { 4211 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4212 &ha->ex_init_cb_dma); 4213 if (!ha->ex_init_cb) 4214 goto fail_ex_init_cb; 4215 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4216 "ex_init_cb=%p.\n", ha->ex_init_cb); 4217 } 4218 4219 /* Get consistent memory allocated for Special Features-CB. */ 4220 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4221 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4222 &ha->sf_init_cb_dma); 4223 if (!ha->sf_init_cb) 4224 goto fail_sf_init_cb; 4225 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb)); 4226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4227 "sf_init_cb=%p.\n", ha->sf_init_cb); 4228 } 4229 4230 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4231 4232 /* Get consistent memory allocated for Async Port-Database. */ 4233 if (!IS_FWI2_CAPABLE(ha)) { 4234 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4235 &ha->async_pd_dma); 4236 if (!ha->async_pd) 4237 goto fail_async_pd; 4238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4239 "async_pd=%p.\n", ha->async_pd); 4240 } 4241 4242 INIT_LIST_HEAD(&ha->vp_list); 4243 4244 /* Allocate memory for our loop_id bitmap */ 4245 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4246 sizeof(long), 4247 GFP_KERNEL); 4248 if (!ha->loop_id_map) 4249 goto fail_loop_id_map; 4250 else { 4251 qla2x00_set_reserved_loop_ids(ha); 4252 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4253 "loop_id_map=%p.\n", ha->loop_id_map); 4254 } 4255 4256 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4257 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4258 if (!ha->sfp_data) { 4259 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4260 "Unable to allocate memory for SFP read-data.\n"); 4261 goto fail_sfp_data; 4262 } 4263 4264 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4265 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4266 GFP_KERNEL); 4267 if (!ha->flt) { 4268 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4269 "Unable to allocate memory for FLT.\n"); 4270 goto fail_flt_buffer; 4271 } 4272 4273 return 0; 4274 4275fail_flt_buffer: 4276 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4277 ha->sfp_data, ha->sfp_data_dma); 4278fail_sfp_data: 4279 kfree(ha->loop_id_map); 4280fail_loop_id_map: 4281 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4282fail_async_pd: 4283 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4284fail_sf_init_cb: 4285 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4286fail_ex_init_cb: 4287 kfree(ha->npiv_info); 4288fail_npiv_info: 4289 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4290 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4291 (*rsp)->ring = NULL; 4292 (*rsp)->dma = 0; 4293fail_rsp_ring: 4294 kfree(*rsp); 4295 *rsp = NULL; 4296fail_rsp: 4297 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4298 sizeof(request_t), (*req)->ring, (*req)->dma); 4299 (*req)->ring = NULL; 4300 (*req)->dma = 0; 4301fail_req_ring: 4302 kfree(*req); 4303 *req = NULL; 4304fail_req: 4305 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4306 ha->ct_sns, ha->ct_sns_dma); 4307 ha->ct_sns = NULL; 4308 ha->ct_sns_dma = 0; 4309fail_free_ms_iocb: 4310 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4311 ha->ms_iocb = NULL; 4312 ha->ms_iocb_dma = 0; 4313 4314 if (ha->sns_cmd) 4315 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4316 ha->sns_cmd, ha->sns_cmd_dma); 4317fail_dma_pool: 4318 if (ql2xenabledif) { 4319 struct dsd_dma *dsd, *nxt; 4320 4321 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4322 list) { 4323 list_del(&dsd->list); 4324 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4325 dsd->dsd_list_dma); 4326 ha->dif_bundle_dma_allocs--; 4327 kfree(dsd); 4328 ha->dif_bundle_kallocs--; 4329 ha->pool.unusable.count--; 4330 } 4331 dma_pool_destroy(ha->dif_bundl_pool); 4332 ha->dif_bundl_pool = NULL; 4333 } 4334 4335fail_dif_bundl_dma_pool: 4336 if (IS_QLA82XX(ha) || ql2xenabledif) { 4337 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4338 ha->fcp_cmnd_dma_pool = NULL; 4339 } 4340fail_dl_dma_pool: 4341 if (IS_QLA82XX(ha) || ql2xenabledif) { 4342 dma_pool_destroy(ha->dl_dma_pool); 4343 ha->dl_dma_pool = NULL; 4344 } 4345fail_s_dma_pool: 4346 dma_pool_destroy(ha->s_dma_pool); 4347 ha->s_dma_pool = NULL; 4348fail_free_nvram: 4349 kfree(ha->nvram); 4350 ha->nvram = NULL; 4351fail_free_ctx_mempool: 4352 mempool_destroy(ha->ctx_mempool); 4353 ha->ctx_mempool = NULL; 4354fail_free_srb_mempool: 4355 mempool_destroy(ha->srb_mempool); 4356 ha->srb_mempool = NULL; 4357fail_free_gid_list: 4358 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4359 ha->gid_list, 4360 ha->gid_list_dma); 4361 ha->gid_list = NULL; 4362 ha->gid_list_dma = 0; 4363fail_free_tgt_mem: 4364 qlt_mem_free(ha); 4365fail_free_init_cb: 4366 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4367 ha->init_cb_dma); 4368 ha->init_cb = NULL; 4369 ha->init_cb_dma = 0; 4370fail: 4371 ql_log(ql_log_fatal, NULL, 0x0030, 4372 "Memory allocation failure.\n"); 4373 return -ENOMEM; 4374} 4375 4376int 4377qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4378{ 4379 int rval; 4380 uint16_t size, max_cnt; 4381 uint32_t temp; 4382 struct qla_hw_data *ha = vha->hw; 4383 4384 /* Return if we don't need to alloacate any extended logins */ 4385 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4386 return QLA_SUCCESS; 4387 4388 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4389 return QLA_SUCCESS; 4390 4391 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4392 max_cnt = 0; 4393 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4394 if (rval != QLA_SUCCESS) { 4395 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4396 "Failed to get exlogin status.\n"); 4397 return rval; 4398 } 4399 4400 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4401 temp *= size; 4402 4403 if (temp != ha->exlogin_size) { 4404 qla2x00_free_exlogin_buffer(ha); 4405 ha->exlogin_size = temp; 4406 4407 ql_log(ql_log_info, vha, 0xd024, 4408 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4409 max_cnt, size, temp); 4410 4411 ql_log(ql_log_info, vha, 0xd025, 4412 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4413 4414 /* Get consistent memory for extended logins */ 4415 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4416 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4417 if (!ha->exlogin_buf) { 4418 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4419 "Failed to allocate memory for exlogin_buf_dma.\n"); 4420 return -ENOMEM; 4421 } 4422 } 4423 4424 /* Now configure the dma buffer */ 4425 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4426 if (rval) { 4427 ql_log(ql_log_fatal, vha, 0xd033, 4428 "Setup extended login buffer ****FAILED****.\n"); 4429 qla2x00_free_exlogin_buffer(ha); 4430 } 4431 4432 return rval; 4433} 4434 4435/* 4436* qla2x00_free_exlogin_buffer 4437* 4438* Input: 4439* ha = adapter block pointer 4440*/ 4441void 4442qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4443{ 4444 if (ha->exlogin_buf) { 4445 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4446 ha->exlogin_buf, ha->exlogin_buf_dma); 4447 ha->exlogin_buf = NULL; 4448 ha->exlogin_size = 0; 4449 } 4450} 4451 4452static void 4453qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4454{ 4455 u32 temp; 4456 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb; 4457 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4458 4459 if (max_cnt > vha->hw->max_exchg) 4460 max_cnt = vha->hw->max_exchg; 4461 4462 if (qla_ini_mode_enabled(vha)) { 4463 if (vha->ql2xiniexchg > max_cnt) 4464 vha->ql2xiniexchg = max_cnt; 4465 4466 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4467 *ret_cnt = vha->ql2xiniexchg; 4468 4469 } else if (qla_tgt_mode_enabled(vha)) { 4470 if (vha->ql2xexchoffld > max_cnt) { 4471 vha->ql2xexchoffld = max_cnt; 4472 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4473 } 4474 4475 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4476 *ret_cnt = vha->ql2xexchoffld; 4477 } else if (qla_dual_mode_enabled(vha)) { 4478 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4479 if (temp > max_cnt) { 4480 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4481 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4482 temp = max_cnt; 4483 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4484 } 4485 4486 if (temp > FW_DEF_EXCHANGES_CNT) 4487 *ret_cnt = temp; 4488 } 4489} 4490 4491int 4492qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4493{ 4494 int rval; 4495 u16 size, max_cnt; 4496 u32 actual_cnt, totsz; 4497 struct qla_hw_data *ha = vha->hw; 4498 4499 if (!ha->flags.exchoffld_enabled) 4500 return QLA_SUCCESS; 4501 4502 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4503 return QLA_SUCCESS; 4504 4505 max_cnt = 0; 4506 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4507 if (rval != QLA_SUCCESS) { 4508 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4509 "Failed to get exlogin status.\n"); 4510 return rval; 4511 } 4512 4513 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4514 ql_log(ql_log_info, vha, 0xd014, 4515 "Actual exchange offload count: %d.\n", actual_cnt); 4516 4517 totsz = actual_cnt * size; 4518 4519 if (totsz != ha->exchoffld_size) { 4520 qla2x00_free_exchoffld_buffer(ha); 4521 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4522 ha->exchoffld_size = 0; 4523 ha->flags.exchoffld_enabled = 0; 4524 return QLA_SUCCESS; 4525 } 4526 4527 ha->exchoffld_size = totsz; 4528 4529 ql_log(ql_log_info, vha, 0xd016, 4530 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4531 max_cnt, actual_cnt, size, totsz); 4532 4533 ql_log(ql_log_info, vha, 0xd017, 4534 "Exchange Buffers requested size = 0x%x\n", 4535 ha->exchoffld_size); 4536 4537 /* Get consistent memory for extended logins */ 4538 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4539 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4540 if (!ha->exchoffld_buf) { 4541 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4542 "Failed to allocate memory for Exchange Offload.\n"); 4543 4544 if (ha->max_exchg > 4545 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4546 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4547 } else if (ha->max_exchg > 4548 (FW_DEF_EXCHANGES_CNT + 512)) { 4549 ha->max_exchg -= 512; 4550 } else { 4551 ha->flags.exchoffld_enabled = 0; 4552 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4553 "Disabling Exchange offload due to lack of memory\n"); 4554 } 4555 ha->exchoffld_size = 0; 4556 4557 return -ENOMEM; 4558 } 4559 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4560 /* pathological case */ 4561 qla2x00_free_exchoffld_buffer(ha); 4562 ha->exchoffld_size = 0; 4563 ha->flags.exchoffld_enabled = 0; 4564 ql_log(ql_log_info, vha, 0xd016, 4565 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4566 ha->exchoffld_size, actual_cnt, size, totsz); 4567 return 0; 4568 } 4569 4570 /* Now configure the dma buffer */ 4571 rval = qla_set_exchoffld_mem_cfg(vha); 4572 if (rval) { 4573 ql_log(ql_log_fatal, vha, 0xd02e, 4574 "Setup exchange offload buffer ****FAILED****.\n"); 4575 qla2x00_free_exchoffld_buffer(ha); 4576 } else { 4577 /* re-adjust number of target exchange */ 4578 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4579 4580 if (qla_ini_mode_enabled(vha)) 4581 icb->exchange_count = 0; 4582 else 4583 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4584 } 4585 4586 return rval; 4587} 4588 4589/* 4590* qla2x00_free_exchoffld_buffer 4591* 4592* Input: 4593* ha = adapter block pointer 4594*/ 4595void 4596qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4597{ 4598 if (ha->exchoffld_buf) { 4599 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4600 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4601 ha->exchoffld_buf = NULL; 4602 ha->exchoffld_size = 0; 4603 } 4604} 4605 4606/* 4607* qla2x00_free_fw_dump 4608* Frees fw dump stuff. 4609* 4610* Input: 4611* ha = adapter block pointer 4612*/ 4613static void 4614qla2x00_free_fw_dump(struct qla_hw_data *ha) 4615{ 4616 struct fwdt *fwdt = ha->fwdt; 4617 uint j; 4618 4619 if (ha->fce) 4620 dma_free_coherent(&ha->pdev->dev, 4621 FCE_SIZE, ha->fce, ha->fce_dma); 4622 4623 if (ha->eft) 4624 dma_free_coherent(&ha->pdev->dev, 4625 EFT_SIZE, ha->eft, ha->eft_dma); 4626 4627 if (ha->fw_dump) 4628 vfree(ha->fw_dump); 4629 4630 ha->fce = NULL; 4631 ha->fce_dma = 0; 4632 ha->flags.fce_enabled = 0; 4633 ha->eft = NULL; 4634 ha->eft_dma = 0; 4635 ha->fw_dumped = false; 4636 ha->fw_dump_cap_flags = 0; 4637 ha->fw_dump_reading = 0; 4638 ha->fw_dump = NULL; 4639 ha->fw_dump_len = 0; 4640 4641 for (j = 0; j < 2; j++, fwdt++) { 4642 if (fwdt->template) 4643 vfree(fwdt->template); 4644 fwdt->template = NULL; 4645 fwdt->length = 0; 4646 } 4647} 4648 4649/* 4650* qla2x00_mem_free 4651* Frees all adapter allocated memory. 4652* 4653* Input: 4654* ha = adapter block pointer. 4655*/ 4656static void 4657qla2x00_mem_free(struct qla_hw_data *ha) 4658{ 4659 qla2x00_free_fw_dump(ha); 4660 4661 if (ha->mctp_dump) 4662 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4663 ha->mctp_dump_dma); 4664 ha->mctp_dump = NULL; 4665 4666 mempool_destroy(ha->srb_mempool); 4667 ha->srb_mempool = NULL; 4668 4669 if (ha->dcbx_tlv) 4670 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4671 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4672 ha->dcbx_tlv = NULL; 4673 4674 if (ha->xgmac_data) 4675 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4676 ha->xgmac_data, ha->xgmac_data_dma); 4677 ha->xgmac_data = NULL; 4678 4679 if (ha->sns_cmd) 4680 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4681 ha->sns_cmd, ha->sns_cmd_dma); 4682 ha->sns_cmd = NULL; 4683 ha->sns_cmd_dma = 0; 4684 4685 if (ha->ct_sns) 4686 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4687 ha->ct_sns, ha->ct_sns_dma); 4688 ha->ct_sns = NULL; 4689 ha->ct_sns_dma = 0; 4690 4691 if (ha->sfp_data) 4692 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4693 ha->sfp_data_dma); 4694 ha->sfp_data = NULL; 4695 4696 if (ha->flt) 4697 dma_free_coherent(&ha->pdev->dev, 4698 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4699 ha->flt, ha->flt_dma); 4700 ha->flt = NULL; 4701 ha->flt_dma = 0; 4702 4703 if (ha->ms_iocb) 4704 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4705 ha->ms_iocb = NULL; 4706 ha->ms_iocb_dma = 0; 4707 4708 if (ha->sf_init_cb) 4709 dma_pool_free(ha->s_dma_pool, 4710 ha->sf_init_cb, ha->sf_init_cb_dma); 4711 4712 if (ha->ex_init_cb) 4713 dma_pool_free(ha->s_dma_pool, 4714 ha->ex_init_cb, ha->ex_init_cb_dma); 4715 ha->ex_init_cb = NULL; 4716 ha->ex_init_cb_dma = 0; 4717 4718 if (ha->async_pd) 4719 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4720 ha->async_pd = NULL; 4721 ha->async_pd_dma = 0; 4722 4723 dma_pool_destroy(ha->s_dma_pool); 4724 ha->s_dma_pool = NULL; 4725 4726 if (ha->gid_list) 4727 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4728 ha->gid_list, ha->gid_list_dma); 4729 ha->gid_list = NULL; 4730 ha->gid_list_dma = 0; 4731 4732 if (IS_QLA82XX(ha)) { 4733 if (!list_empty(&ha->gbl_dsd_list)) { 4734 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4735 4736 /* clean up allocated prev pool */ 4737 list_for_each_entry_safe(dsd_ptr, 4738 tdsd_ptr, &ha->gbl_dsd_list, list) { 4739 dma_pool_free(ha->dl_dma_pool, 4740 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4741 list_del(&dsd_ptr->list); 4742 kfree(dsd_ptr); 4743 } 4744 } 4745 } 4746 4747 dma_pool_destroy(ha->dl_dma_pool); 4748 ha->dl_dma_pool = NULL; 4749 4750 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4751 ha->fcp_cmnd_dma_pool = NULL; 4752 4753 mempool_destroy(ha->ctx_mempool); 4754 ha->ctx_mempool = NULL; 4755 4756 if (ql2xenabledif && ha->dif_bundl_pool) { 4757 struct dsd_dma *dsd, *nxt; 4758 4759 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4760 list) { 4761 list_del(&dsd->list); 4762 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4763 dsd->dsd_list_dma); 4764 ha->dif_bundle_dma_allocs--; 4765 kfree(dsd); 4766 ha->dif_bundle_kallocs--; 4767 ha->pool.unusable.count--; 4768 } 4769 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4770 list_del(&dsd->list); 4771 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4772 dsd->dsd_list_dma); 4773 ha->dif_bundle_dma_allocs--; 4774 kfree(dsd); 4775 ha->dif_bundle_kallocs--; 4776 } 4777 } 4778 4779 dma_pool_destroy(ha->dif_bundl_pool); 4780 ha->dif_bundl_pool = NULL; 4781 4782 qlt_mem_free(ha); 4783 4784 if (ha->init_cb) 4785 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4786 ha->init_cb, ha->init_cb_dma); 4787 ha->init_cb = NULL; 4788 ha->init_cb_dma = 0; 4789 4790 vfree(ha->optrom_buffer); 4791 ha->optrom_buffer = NULL; 4792 kfree(ha->nvram); 4793 ha->nvram = NULL; 4794 kfree(ha->npiv_info); 4795 ha->npiv_info = NULL; 4796 kfree(ha->swl); 4797 ha->swl = NULL; 4798 kfree(ha->loop_id_map); 4799 ha->sf_init_cb = NULL; 4800 ha->sf_init_cb_dma = 0; 4801 ha->loop_id_map = NULL; 4802} 4803 4804struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4805 struct qla_hw_data *ha) 4806{ 4807 struct Scsi_Host *host; 4808 struct scsi_qla_host *vha = NULL; 4809 4810 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4811 if (!host) { 4812 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4813 "Failed to allocate host from the scsi layer, aborting.\n"); 4814 return NULL; 4815 } 4816 4817 /* Clear our data area */ 4818 vha = shost_priv(host); 4819 memset(vha, 0, sizeof(scsi_qla_host_t)); 4820 4821 vha->host = host; 4822 vha->host_no = host->host_no; 4823 vha->hw = ha; 4824 4825 vha->qlini_mode = ql2x_ini_mode; 4826 vha->ql2xexchoffld = ql2xexchoffld; 4827 vha->ql2xiniexchg = ql2xiniexchg; 4828 4829 INIT_LIST_HEAD(&vha->vp_fcports); 4830 INIT_LIST_HEAD(&vha->work_list); 4831 INIT_LIST_HEAD(&vha->list); 4832 INIT_LIST_HEAD(&vha->qla_cmd_list); 4833 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4834 INIT_LIST_HEAD(&vha->logo_list); 4835 INIT_LIST_HEAD(&vha->plogi_ack_list); 4836 INIT_LIST_HEAD(&vha->qp_list); 4837 INIT_LIST_HEAD(&vha->gnl.fcports); 4838 INIT_LIST_HEAD(&vha->gpnid_list); 4839 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4840 4841 INIT_LIST_HEAD(&vha->purex_list.head); 4842 spin_lock_init(&vha->purex_list.lock); 4843 4844 spin_lock_init(&vha->work_lock); 4845 spin_lock_init(&vha->cmd_list_lock); 4846 init_waitqueue_head(&vha->fcport_waitQ); 4847 init_waitqueue_head(&vha->vref_waitq); 4848 4849 vha->gnl.size = sizeof(struct get_name_list_extended) * 4850 (ha->max_loop_id + 1); 4851 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4852 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4853 if (!vha->gnl.l) { 4854 ql_log(ql_log_fatal, vha, 0xd04a, 4855 "Alloc failed for name list.\n"); 4856 scsi_host_put(vha->host); 4857 return NULL; 4858 } 4859 4860 /* todo: what about ext login? */ 4861 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4862 vha->scan.l = vmalloc(vha->scan.size); 4863 if (!vha->scan.l) { 4864 ql_log(ql_log_fatal, vha, 0xd04a, 4865 "Alloc failed for scan database.\n"); 4866 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4867 vha->gnl.l, vha->gnl.ldma); 4868 vha->gnl.l = NULL; 4869 scsi_host_put(vha->host); 4870 return NULL; 4871 } 4872 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4873 4874 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", 4875 QLA2XXX_DRIVER_NAME, vha->host_no); 4876 ql_dbg(ql_dbg_init, vha, 0x0041, 4877 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4878 vha->host, vha->hw, vha, 4879 dev_name(&(ha->pdev->dev))); 4880 4881 return vha; 4882} 4883 4884struct qla_work_evt * 4885qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4886{ 4887 struct qla_work_evt *e; 4888 uint8_t bail; 4889 4890 if (test_bit(UNLOADING, &vha->dpc_flags)) 4891 return NULL; 4892 4893 QLA_VHA_MARK_BUSY(vha, bail); 4894 if (bail) 4895 return NULL; 4896 4897 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4898 if (!e) { 4899 QLA_VHA_MARK_NOT_BUSY(vha); 4900 return NULL; 4901 } 4902 4903 INIT_LIST_HEAD(&e->list); 4904 e->type = type; 4905 e->flags = QLA_EVT_FLAG_FREE; 4906 return e; 4907} 4908 4909int 4910qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4911{ 4912 unsigned long flags; 4913 bool q = false; 4914 4915 spin_lock_irqsave(&vha->work_lock, flags); 4916 list_add_tail(&e->list, &vha->work_list); 4917 4918 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4919 q = true; 4920 4921 spin_unlock_irqrestore(&vha->work_lock, flags); 4922 4923 if (q) 4924 queue_work(vha->hw->wq, &vha->iocb_work); 4925 4926 return QLA_SUCCESS; 4927} 4928 4929int 4930qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4931 u32 data) 4932{ 4933 struct qla_work_evt *e; 4934 4935 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4936 if (!e) 4937 return QLA_FUNCTION_FAILED; 4938 4939 e->u.aen.code = code; 4940 e->u.aen.data = data; 4941 return qla2x00_post_work(vha, e); 4942} 4943 4944int 4945qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4946{ 4947 struct qla_work_evt *e; 4948 4949 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4950 if (!e) 4951 return QLA_FUNCTION_FAILED; 4952 4953 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4954 return qla2x00_post_work(vha, e); 4955} 4956 4957#define qla2x00_post_async_work(name, type) \ 4958int qla2x00_post_async_##name##_work( \ 4959 struct scsi_qla_host *vha, \ 4960 fc_port_t *fcport, uint16_t *data) \ 4961{ \ 4962 struct qla_work_evt *e; \ 4963 \ 4964 e = qla2x00_alloc_work(vha, type); \ 4965 if (!e) \ 4966 return QLA_FUNCTION_FAILED; \ 4967 \ 4968 e->u.logio.fcport = fcport; \ 4969 if (data) { \ 4970 e->u.logio.data[0] = data[0]; \ 4971 e->u.logio.data[1] = data[1]; \ 4972 } \ 4973 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4974 return qla2x00_post_work(vha, e); \ 4975} 4976 4977qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4978qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4979qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4980qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4981qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4982 4983int 4984qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4985{ 4986 struct qla_work_evt *e; 4987 4988 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4989 if (!e) 4990 return QLA_FUNCTION_FAILED; 4991 4992 e->u.uevent.code = code; 4993 return qla2x00_post_work(vha, e); 4994} 4995 4996static void 4997qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4998{ 4999 char event_string[40]; 5000 char *envp[] = { event_string, NULL }; 5001 5002 switch (code) { 5003 case QLA_UEVENT_CODE_FW_DUMP: 5004 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5005 vha->host_no); 5006 break; 5007 default: 5008 /* do nothing */ 5009 break; 5010 } 5011 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5012} 5013 5014int 5015qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5016 uint32_t *data, int cnt) 5017{ 5018 struct qla_work_evt *e; 5019 5020 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5021 if (!e) 5022 return QLA_FUNCTION_FAILED; 5023 5024 e->u.aenfx.evtcode = evtcode; 5025 e->u.aenfx.count = cnt; 5026 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5027 return qla2x00_post_work(vha, e); 5028} 5029 5030void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5031{ 5032 unsigned long flags; 5033 5034 if (IS_SW_RESV_ADDR(fcport->d_id)) 5035 return; 5036 5037 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5038 if (fcport->disc_state == DSC_UPD_FCPORT) { 5039 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5040 return; 5041 } 5042 fcport->jiffies_at_registration = jiffies; 5043 fcport->sec_since_registration = 0; 5044 fcport->next_disc_state = DSC_DELETED; 5045 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5046 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5047 5048 queue_work(system_unbound_wq, &fcport->reg_work); 5049} 5050 5051static 5052void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5053{ 5054 unsigned long flags; 5055 fc_port_t *fcport = NULL, *tfcp; 5056 struct qlt_plogi_ack_t *pla = 5057 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5058 uint8_t free_fcport = 0; 5059 5060 ql_dbg(ql_dbg_disc, vha, 0xffff, 5061 "%s %d %8phC enter\n", 5062 __func__, __LINE__, e->u.new_sess.port_name); 5063 5064 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5065 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5066 if (fcport) { 5067 fcport->d_id = e->u.new_sess.id; 5068 if (pla) { 5069 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5070 memcpy(fcport->node_name, 5071 pla->iocb.u.isp24.u.plogi.node_name, 5072 WWN_SIZE); 5073 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5074 /* we took an extra ref_count to prevent PLOGI ACK when 5075 * fcport/sess has not been created. 5076 */ 5077 pla->ref_count--; 5078 } 5079 } else { 5080 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5081 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5082 if (fcport) { 5083 fcport->d_id = e->u.new_sess.id; 5084 fcport->flags |= FCF_FABRIC_DEVICE; 5085 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5086 5087 memcpy(fcport->port_name, e->u.new_sess.port_name, 5088 WWN_SIZE); 5089 5090 fcport->fc4_type = e->u.new_sess.fc4_type; 5091 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5092 fcport->dm_login_expire = jiffies + 5093 QLA_N2N_WAIT_TIME * HZ; 5094 fcport->fc4_type = FS_FC4TYPE_FCP; 5095 fcport->n2n_flag = 1; 5096 if (vha->flags.nvme_enabled) 5097 fcport->fc4_type |= FS_FC4TYPE_NVME; 5098 } 5099 5100 } else { 5101 ql_dbg(ql_dbg_disc, vha, 0xffff, 5102 "%s %8phC mem alloc fail.\n", 5103 __func__, e->u.new_sess.port_name); 5104 5105 if (pla) { 5106 list_del(&pla->list); 5107 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5108 } 5109 return; 5110 } 5111 5112 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5113 /* search again to make sure no one else got ahead */ 5114 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5115 e->u.new_sess.port_name, 1); 5116 if (tfcp) { 5117 /* should rarily happen */ 5118 ql_dbg(ql_dbg_disc, vha, 0xffff, 5119 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5120 __func__, tfcp->port_name, tfcp->disc_state, 5121 tfcp->fw_login_state); 5122 5123 free_fcport = 1; 5124 } else { 5125 list_add_tail(&fcport->list, &vha->vp_fcports); 5126 5127 } 5128 if (pla) { 5129 qlt_plogi_ack_link(vha, pla, fcport, 5130 QLT_PLOGI_LINK_SAME_WWN); 5131 pla->ref_count--; 5132 } 5133 } 5134 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5135 5136 if (fcport) { 5137 fcport->id_changed = 1; 5138 fcport->scan_state = QLA_FCPORT_FOUND; 5139 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5140 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5141 5142 if (pla) { 5143 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5144 u16 wd3_lo; 5145 5146 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5147 fcport->local = 0; 5148 fcport->loop_id = 5149 le16_to_cpu( 5150 pla->iocb.u.isp24.nport_handle); 5151 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5152 wd3_lo = 5153 le16_to_cpu( 5154 pla->iocb.u.isp24.u.prli.wd3_lo); 5155 5156 if (wd3_lo & BIT_7) 5157 fcport->conf_compl_supported = 1; 5158 5159 if ((wd3_lo & BIT_4) == 0) 5160 fcport->port_type = FCT_INITIATOR; 5161 else 5162 fcport->port_type = FCT_TARGET; 5163 } 5164 qlt_plogi_ack_unref(vha, pla); 5165 } else { 5166 fc_port_t *dfcp = NULL; 5167 5168 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5169 tfcp = qla2x00_find_fcport_by_nportid(vha, 5170 &e->u.new_sess.id, 1); 5171 if (tfcp && (tfcp != fcport)) { 5172 /* 5173 * We have a conflict fcport with same NportID. 5174 */ 5175 ql_dbg(ql_dbg_disc, vha, 0xffff, 5176 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5177 __func__, tfcp->port_name, tfcp->disc_state, 5178 tfcp->fw_login_state); 5179 5180 switch (tfcp->disc_state) { 5181 case DSC_DELETED: 5182 break; 5183 case DSC_DELETE_PEND: 5184 fcport->login_pause = 1; 5185 tfcp->conflict = fcport; 5186 break; 5187 default: 5188 fcport->login_pause = 1; 5189 tfcp->conflict = fcport; 5190 dfcp = tfcp; 5191 break; 5192 } 5193 } 5194 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5195 if (dfcp) 5196 qlt_schedule_sess_for_deletion(tfcp); 5197 5198 if (N2N_TOPO(vha->hw)) { 5199 fcport->flags &= ~FCF_FABRIC_DEVICE; 5200 fcport->keep_nport_handle = 1; 5201 if (vha->flags.nvme_enabled) { 5202 fcport->fc4_type = 5203 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5204 fcport->n2n_flag = 1; 5205 } 5206 fcport->fw_login_state = 0; 5207 5208 schedule_delayed_work(&vha->scan.scan_work, 5); 5209 } else { 5210 qla24xx_fcport_handle_login(vha, fcport); 5211 } 5212 } 5213 } 5214 5215 if (free_fcport) { 5216 qla2x00_free_fcport(fcport); 5217 if (pla) { 5218 list_del(&pla->list); 5219 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5220 } 5221 } 5222} 5223 5224static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5225{ 5226 struct srb *sp = e->u.iosb.sp; 5227 int rval; 5228 5229 rval = qla2x00_start_sp(sp); 5230 if (rval != QLA_SUCCESS) { 5231 ql_dbg(ql_dbg_disc, vha, 0x2043, 5232 "%s: %s: Re-issue IOCB failed (%d).\n", 5233 __func__, sp->name, rval); 5234 qla24xx_sp_unmap(vha, sp); 5235 } 5236} 5237 5238void 5239qla2x00_do_work(struct scsi_qla_host *vha) 5240{ 5241 struct qla_work_evt *e, *tmp; 5242 unsigned long flags; 5243 LIST_HEAD(work); 5244 int rc; 5245 5246 spin_lock_irqsave(&vha->work_lock, flags); 5247 list_splice_init(&vha->work_list, &work); 5248 spin_unlock_irqrestore(&vha->work_lock, flags); 5249 5250 list_for_each_entry_safe(e, tmp, &work, list) { 5251 rc = QLA_SUCCESS; 5252 switch (e->type) { 5253 case QLA_EVT_AEN: 5254 fc_host_post_event(vha->host, fc_get_event_number(), 5255 e->u.aen.code, e->u.aen.data); 5256 break; 5257 case QLA_EVT_IDC_ACK: 5258 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5259 break; 5260 case QLA_EVT_ASYNC_LOGIN: 5261 qla2x00_async_login(vha, e->u.logio.fcport, 5262 e->u.logio.data); 5263 break; 5264 case QLA_EVT_ASYNC_LOGOUT: 5265 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5266 break; 5267 case QLA_EVT_ASYNC_ADISC: 5268 qla2x00_async_adisc(vha, e->u.logio.fcport, 5269 e->u.logio.data); 5270 break; 5271 case QLA_EVT_UEVENT: 5272 qla2x00_uevent_emit(vha, e->u.uevent.code); 5273 break; 5274 case QLA_EVT_AENFX: 5275 qlafx00_process_aen(vha, e); 5276 break; 5277 case QLA_EVT_GPNID: 5278 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5279 break; 5280 case QLA_EVT_UNMAP: 5281 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5282 break; 5283 case QLA_EVT_RELOGIN: 5284 qla2x00_relogin(vha); 5285 break; 5286 case QLA_EVT_NEW_SESS: 5287 qla24xx_create_new_sess(vha, e); 5288 break; 5289 case QLA_EVT_GPDB: 5290 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5291 e->u.fcport.opt); 5292 break; 5293 case QLA_EVT_PRLI: 5294 qla24xx_async_prli(vha, e->u.fcport.fcport); 5295 break; 5296 case QLA_EVT_GPSC: 5297 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5298 break; 5299 case QLA_EVT_GNL: 5300 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5301 break; 5302 case QLA_EVT_NACK: 5303 qla24xx_do_nack_work(vha, e); 5304 break; 5305 case QLA_EVT_ASYNC_PRLO: 5306 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5307 break; 5308 case QLA_EVT_ASYNC_PRLO_DONE: 5309 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5310 e->u.logio.data); 5311 break; 5312 case QLA_EVT_GPNFT: 5313 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5314 e->u.gpnft.sp); 5315 break; 5316 case QLA_EVT_GPNFT_DONE: 5317 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5318 break; 5319 case QLA_EVT_GNNFT_DONE: 5320 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5321 break; 5322 case QLA_EVT_GNNID: 5323 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5324 break; 5325 case QLA_EVT_GFPNID: 5326 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5327 break; 5328 case QLA_EVT_SP_RETRY: 5329 qla_sp_retry(vha, e); 5330 break; 5331 case QLA_EVT_IIDMA: 5332 qla_do_iidma_work(vha, e->u.fcport.fcport); 5333 break; 5334 case QLA_EVT_ELS_PLOGI: 5335 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5336 e->u.fcport.fcport, false); 5337 break; 5338 } 5339 5340 if (rc == EAGAIN) { 5341 /* put 'work' at head of 'vha->work_list' */ 5342 spin_lock_irqsave(&vha->work_lock, flags); 5343 list_splice(&work, &vha->work_list); 5344 spin_unlock_irqrestore(&vha->work_lock, flags); 5345 break; 5346 } 5347 list_del_init(&e->list); 5348 if (e->flags & QLA_EVT_FLAG_FREE) 5349 kfree(e); 5350 5351 /* For each work completed decrement vha ref count */ 5352 QLA_VHA_MARK_NOT_BUSY(vha); 5353 } 5354} 5355 5356int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5357{ 5358 struct qla_work_evt *e; 5359 5360 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5361 5362 if (!e) { 5363 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5364 return QLA_FUNCTION_FAILED; 5365 } 5366 5367 return qla2x00_post_work(vha, e); 5368} 5369 5370/* Relogins all the fcports of a vport 5371 * Context: dpc thread 5372 */ 5373void qla2x00_relogin(struct scsi_qla_host *vha) 5374{ 5375 fc_port_t *fcport; 5376 int status, relogin_needed = 0; 5377 struct event_arg ea; 5378 5379 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5380 /* 5381 * If the port is not ONLINE then try to login 5382 * to it if we haven't run out of retries. 5383 */ 5384 if (atomic_read(&fcport->state) != FCS_ONLINE && 5385 fcport->login_retry) { 5386 if (fcport->scan_state != QLA_FCPORT_FOUND || 5387 fcport->disc_state == DSC_LOGIN_COMPLETE) 5388 continue; 5389 5390 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5391 fcport->disc_state == DSC_DELETE_PEND) { 5392 relogin_needed = 1; 5393 } else { 5394 if (vha->hw->current_topology != ISP_CFG_NL) { 5395 memset(&ea, 0, sizeof(ea)); 5396 ea.fcport = fcport; 5397 qla24xx_handle_relogin_event(vha, &ea); 5398 } else if (vha->hw->current_topology == 5399 ISP_CFG_NL && 5400 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5401 (void)qla24xx_fcport_handle_login(vha, 5402 fcport); 5403 } else if (vha->hw->current_topology == 5404 ISP_CFG_NL) { 5405 fcport->login_retry--; 5406 status = 5407 qla2x00_local_device_login(vha, 5408 fcport); 5409 if (status == QLA_SUCCESS) { 5410 fcport->old_loop_id = 5411 fcport->loop_id; 5412 ql_dbg(ql_dbg_disc, vha, 0x2003, 5413 "Port login OK: logged in ID 0x%x.\n", 5414 fcport->loop_id); 5415 qla2x00_update_fcport 5416 (vha, fcport); 5417 } else if (status == 1) { 5418 set_bit(RELOGIN_NEEDED, 5419 &vha->dpc_flags); 5420 /* retry the login again */ 5421 ql_dbg(ql_dbg_disc, vha, 0x2007, 5422 "Retrying %d login again loop_id 0x%x.\n", 5423 fcport->login_retry, 5424 fcport->loop_id); 5425 } else { 5426 fcport->login_retry = 0; 5427 } 5428 5429 if (fcport->login_retry == 0 && 5430 status != QLA_SUCCESS) 5431 qla2x00_clear_loop_id(fcport); 5432 } 5433 } 5434 } 5435 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5436 break; 5437 } 5438 5439 if (relogin_needed) 5440 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5441 5442 ql_dbg(ql_dbg_disc, vha, 0x400e, 5443 "Relogin end.\n"); 5444} 5445 5446/* Schedule work on any of the dpc-workqueues */ 5447void 5448qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5449{ 5450 struct qla_hw_data *ha = base_vha->hw; 5451 5452 switch (work_code) { 5453 case MBA_IDC_AEN: /* 0x8200 */ 5454 if (ha->dpc_lp_wq) 5455 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5456 break; 5457 5458 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5459 if (!ha->flags.nic_core_reset_hdlr_active) { 5460 if (ha->dpc_hp_wq) 5461 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5462 } else 5463 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5464 "NIC Core reset is already active. Skip " 5465 "scheduling it again.\n"); 5466 break; 5467 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5468 if (ha->dpc_hp_wq) 5469 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5470 break; 5471 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5472 if (ha->dpc_hp_wq) 5473 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5474 break; 5475 default: 5476 ql_log(ql_log_warn, base_vha, 0xb05f, 5477 "Unknown work-code=0x%x.\n", work_code); 5478 } 5479 5480 return; 5481} 5482 5483/* Work: Perform NIC Core Unrecoverable state handling */ 5484void 5485qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5486{ 5487 struct qla_hw_data *ha = 5488 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5489 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5490 uint32_t dev_state = 0; 5491 5492 qla83xx_idc_lock(base_vha, 0); 5493 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5494 qla83xx_reset_ownership(base_vha); 5495 if (ha->flags.nic_core_reset_owner) { 5496 ha->flags.nic_core_reset_owner = 0; 5497 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5498 QLA8XXX_DEV_FAILED); 5499 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5500 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5501 } 5502 qla83xx_idc_unlock(base_vha, 0); 5503} 5504 5505/* Work: Execute IDC state handler */ 5506void 5507qla83xx_idc_state_handler_work(struct work_struct *work) 5508{ 5509 struct qla_hw_data *ha = 5510 container_of(work, struct qla_hw_data, idc_state_handler); 5511 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5512 uint32_t dev_state = 0; 5513 5514 qla83xx_idc_lock(base_vha, 0); 5515 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5516 if (dev_state == QLA8XXX_DEV_FAILED || 5517 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5518 qla83xx_idc_state_handler(base_vha); 5519 qla83xx_idc_unlock(base_vha, 0); 5520} 5521 5522static int 5523qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5524{ 5525 int rval = QLA_SUCCESS; 5526 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5527 uint32_t heart_beat_counter1, heart_beat_counter2; 5528 5529 do { 5530 if (time_after(jiffies, heart_beat_wait)) { 5531 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5532 "Nic Core f/w is not alive.\n"); 5533 rval = QLA_FUNCTION_FAILED; 5534 break; 5535 } 5536 5537 qla83xx_idc_lock(base_vha, 0); 5538 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5539 &heart_beat_counter1); 5540 qla83xx_idc_unlock(base_vha, 0); 5541 msleep(100); 5542 qla83xx_idc_lock(base_vha, 0); 5543 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5544 &heart_beat_counter2); 5545 qla83xx_idc_unlock(base_vha, 0); 5546 } while (heart_beat_counter1 == heart_beat_counter2); 5547 5548 return rval; 5549} 5550 5551/* Work: Perform NIC Core Reset handling */ 5552void 5553qla83xx_nic_core_reset_work(struct work_struct *work) 5554{ 5555 struct qla_hw_data *ha = 5556 container_of(work, struct qla_hw_data, nic_core_reset); 5557 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5558 uint32_t dev_state = 0; 5559 5560 if (IS_QLA2031(ha)) { 5561 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5562 ql_log(ql_log_warn, base_vha, 0xb081, 5563 "Failed to dump mctp\n"); 5564 return; 5565 } 5566 5567 if (!ha->flags.nic_core_reset_hdlr_active) { 5568 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5569 qla83xx_idc_lock(base_vha, 0); 5570 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5571 &dev_state); 5572 qla83xx_idc_unlock(base_vha, 0); 5573 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5574 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5575 "Nic Core f/w is alive.\n"); 5576 return; 5577 } 5578 } 5579 5580 ha->flags.nic_core_reset_hdlr_active = 1; 5581 if (qla83xx_nic_core_reset(base_vha)) { 5582 /* NIC Core reset failed. */ 5583 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5584 "NIC Core reset failed.\n"); 5585 } 5586 ha->flags.nic_core_reset_hdlr_active = 0; 5587 } 5588} 5589 5590/* Work: Handle 8200 IDC aens */ 5591void 5592qla83xx_service_idc_aen(struct work_struct *work) 5593{ 5594 struct qla_hw_data *ha = 5595 container_of(work, struct qla_hw_data, idc_aen); 5596 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5597 uint32_t dev_state, idc_control; 5598 5599 qla83xx_idc_lock(base_vha, 0); 5600 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5601 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5602 qla83xx_idc_unlock(base_vha, 0); 5603 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5604 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5605 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5606 "Application requested NIC Core Reset.\n"); 5607 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5608 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5609 QLA_SUCCESS) { 5610 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5611 "Other protocol driver requested NIC Core Reset.\n"); 5612 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5613 } 5614 } else if (dev_state == QLA8XXX_DEV_FAILED || 5615 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5616 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5617 } 5618} 5619 5620static void 5621qla83xx_wait_logic(void) 5622{ 5623 int i; 5624 5625 /* Yield CPU */ 5626 if (!in_interrupt()) { 5627 /* 5628 * Wait about 200ms before retrying again. 5629 * This controls the number of retries for single 5630 * lock operation. 5631 */ 5632 msleep(100); 5633 schedule(); 5634 } else { 5635 for (i = 0; i < 20; i++) 5636 cpu_relax(); /* This a nop instr on i386 */ 5637 } 5638} 5639 5640static int 5641qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5642{ 5643 int rval; 5644 uint32_t data; 5645 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5646 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5647 struct qla_hw_data *ha = base_vha->hw; 5648 5649 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5650 "Trying force recovery of the IDC lock.\n"); 5651 5652 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5653 if (rval) 5654 return rval; 5655 5656 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5657 return QLA_SUCCESS; 5658 } else { 5659 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5660 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5661 data); 5662 if (rval) 5663 return rval; 5664 5665 msleep(200); 5666 5667 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5668 &data); 5669 if (rval) 5670 return rval; 5671 5672 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5673 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5674 ~(idc_lck_rcvry_stage_mask)); 5675 rval = qla83xx_wr_reg(base_vha, 5676 QLA83XX_IDC_LOCK_RECOVERY, data); 5677 if (rval) 5678 return rval; 5679 5680 /* Forcefully perform IDC UnLock */ 5681 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5682 &data); 5683 if (rval) 5684 return rval; 5685 /* Clear lock-id by setting 0xff */ 5686 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5687 0xff); 5688 if (rval) 5689 return rval; 5690 /* Clear lock-recovery by setting 0x0 */ 5691 rval = qla83xx_wr_reg(base_vha, 5692 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5693 if (rval) 5694 return rval; 5695 } else 5696 return QLA_SUCCESS; 5697 } 5698 5699 return rval; 5700} 5701 5702static int 5703qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5704{ 5705 int rval = QLA_SUCCESS; 5706 uint32_t o_drv_lockid, n_drv_lockid; 5707 unsigned long lock_recovery_timeout; 5708 5709 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5710retry_lockid: 5711 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5712 if (rval) 5713 goto exit; 5714 5715 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5716 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5717 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5718 return QLA_SUCCESS; 5719 else 5720 return QLA_FUNCTION_FAILED; 5721 } 5722 5723 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5724 if (rval) 5725 goto exit; 5726 5727 if (o_drv_lockid == n_drv_lockid) { 5728 qla83xx_wait_logic(); 5729 goto retry_lockid; 5730 } else 5731 return QLA_SUCCESS; 5732 5733exit: 5734 return rval; 5735} 5736 5737void 5738qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5739{ 5740 uint32_t data; 5741 uint32_t lock_owner; 5742 struct qla_hw_data *ha = base_vha->hw; 5743 5744 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5745retry_lock: 5746 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5747 == QLA_SUCCESS) { 5748 if (data) { 5749 /* Setting lock-id to our function-number */ 5750 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5751 ha->portnum); 5752 } else { 5753 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5754 &lock_owner); 5755 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5756 "Failed to acquire IDC lock, acquired by %d, " 5757 "retrying...\n", lock_owner); 5758 5759 /* Retry/Perform IDC-Lock recovery */ 5760 if (qla83xx_idc_lock_recovery(base_vha) 5761 == QLA_SUCCESS) { 5762 qla83xx_wait_logic(); 5763 goto retry_lock; 5764 } else 5765 ql_log(ql_log_warn, base_vha, 0xb075, 5766 "IDC Lock recovery FAILED.\n"); 5767 } 5768 5769 } 5770 5771 return; 5772} 5773 5774static bool 5775qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5776 struct purex_entry_24xx *purex) 5777{ 5778 char fwstr[16]; 5779 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5780 struct port_database_24xx *pdb; 5781 5782 /* Domain Controller is always logged-out. */ 5783 /* if RDP request is not from Domain Controller: */ 5784 if (sid != 0xfffc01) 5785 return false; 5786 5787 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5788 5789 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5790 if (!pdb) { 5791 ql_dbg(ql_dbg_init, vha, 0x0181, 5792 "%s: Failed allocate pdb\n", __func__); 5793 } else if (qla24xx_get_port_database(vha, 5794 le16_to_cpu(purex->nport_handle), pdb)) { 5795 ql_dbg(ql_dbg_init, vha, 0x0181, 5796 "%s: Failed get pdb sid=%x\n", __func__, sid); 5797 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5798 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5799 ql_dbg(ql_dbg_init, vha, 0x0181, 5800 "%s: Port not logged in sid=%#x\n", __func__, sid); 5801 } else { 5802 /* RDP request is from logged in port */ 5803 kfree(pdb); 5804 return false; 5805 } 5806 kfree(pdb); 5807 5808 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5809 fwstr[strcspn(fwstr, " ")] = 0; 5810 /* if FW version allows RDP response length upto 2048 bytes: */ 5811 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5812 return false; 5813 5814 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5815 5816 /* RDP response length is to be reduced to maximum 256 bytes */ 5817 return true; 5818} 5819 5820/* 5821 * Function Name: qla24xx_process_purex_iocb 5822 * 5823 * Description: 5824 * Prepare a RDP response and send to Fabric switch 5825 * 5826 * PARAMETERS: 5827 * vha: SCSI qla host 5828 * purex: RDP request received by HBA 5829 */ 5830void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5831 struct purex_item *item) 5832{ 5833 struct qla_hw_data *ha = vha->hw; 5834 struct purex_entry_24xx *purex = 5835 (struct purex_entry_24xx *)&item->iocb; 5836 dma_addr_t rsp_els_dma; 5837 dma_addr_t rsp_payload_dma; 5838 dma_addr_t stat_dma; 5839 dma_addr_t sfp_dma; 5840 struct els_entry_24xx *rsp_els = NULL; 5841 struct rdp_rsp_payload *rsp_payload = NULL; 5842 struct link_statistics *stat = NULL; 5843 uint8_t *sfp = NULL; 5844 uint16_t sfp_flags = 0; 5845 uint rsp_payload_length = sizeof(*rsp_payload); 5846 int rval; 5847 5848 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5849 "%s: Enter\n", __func__); 5850 5851 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5852 "-------- ELS REQ -------\n"); 5853 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5854 purex, sizeof(*purex)); 5855 5856 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5857 rsp_payload_length = 5858 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5859 ql_dbg(ql_dbg_init, vha, 0x0181, 5860 "Reducing RSP payload length to %u bytes...\n", 5861 rsp_payload_length); 5862 } 5863 5864 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5865 &rsp_els_dma, GFP_KERNEL); 5866 if (!rsp_els) { 5867 ql_log(ql_log_warn, vha, 0x0183, 5868 "Failed allocate dma buffer ELS RSP.\n"); 5869 goto dealloc; 5870 } 5871 5872 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5873 &rsp_payload_dma, GFP_KERNEL); 5874 if (!rsp_payload) { 5875 ql_log(ql_log_warn, vha, 0x0184, 5876 "Failed allocate dma buffer ELS RSP payload.\n"); 5877 goto dealloc; 5878 } 5879 5880 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5881 &sfp_dma, GFP_KERNEL); 5882 5883 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 5884 &stat_dma, GFP_KERNEL); 5885 5886 /* Prepare Response IOCB */ 5887 rsp_els->entry_type = ELS_IOCB_TYPE; 5888 rsp_els->entry_count = 1; 5889 rsp_els->sys_define = 0; 5890 rsp_els->entry_status = 0; 5891 rsp_els->handle = 0; 5892 rsp_els->nport_handle = purex->nport_handle; 5893 rsp_els->tx_dsd_count = cpu_to_le16(1); 5894 rsp_els->vp_index = purex->vp_idx; 5895 rsp_els->sof_type = EST_SOFI3; 5896 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 5897 rsp_els->rx_dsd_count = 0; 5898 rsp_els->opcode = purex->els_frame_payload[0]; 5899 5900 rsp_els->d_id[0] = purex->s_id[0]; 5901 rsp_els->d_id[1] = purex->s_id[1]; 5902 rsp_els->d_id[2] = purex->s_id[2]; 5903 5904 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 5905 rsp_els->rx_byte_count = 0; 5906 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 5907 5908 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 5909 rsp_els->tx_len = rsp_els->tx_byte_count; 5910 5911 rsp_els->rx_address = 0; 5912 rsp_els->rx_len = 0; 5913 5914 /* Prepare Response Payload */ 5915 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 5916 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 5917 sizeof(rsp_payload->hdr)); 5918 5919 /* Link service Request Info Descriptor */ 5920 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 5921 rsp_payload->ls_req_info_desc.desc_len = 5922 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 5923 rsp_payload->ls_req_info_desc.req_payload_word_0 = 5924 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5925 5926 /* Link service Request Info Descriptor 2 */ 5927 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 5928 rsp_payload->ls_req_info_desc2.desc_len = 5929 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 5930 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 5931 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5932 5933 5934 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 5935 rsp_payload->sfp_diag_desc.desc_len = 5936 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 5937 5938 if (sfp) { 5939 /* SFP Flags */ 5940 memset(sfp, 0, SFP_RTDI_LEN); 5941 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 5942 if (!rval) { 5943 /* SFP Flags bits 3-0: Port Tx Laser Type */ 5944 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 5945 sfp_flags |= BIT_0; /* short wave */ 5946 else if (sfp[0] & BIT_1) 5947 sfp_flags |= BIT_1; /* long wave 1310nm */ 5948 else if (sfp[1] & BIT_4) 5949 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 5950 } 5951 5952 /* SFP Type */ 5953 memset(sfp, 0, SFP_RTDI_LEN); 5954 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 5955 if (!rval) { 5956 sfp_flags |= BIT_4; /* optical */ 5957 if (sfp[0] == 0x3) 5958 sfp_flags |= BIT_6; /* sfp+ */ 5959 } 5960 5961 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 5962 5963 /* SFP Diagnostics */ 5964 memset(sfp, 0, SFP_RTDI_LEN); 5965 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 5966 if (!rval) { 5967 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 5968 rsp_payload->sfp_diag_desc.temperature = trx[0]; 5969 rsp_payload->sfp_diag_desc.vcc = trx[1]; 5970 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 5971 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 5972 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 5973 } 5974 } 5975 5976 /* Port Speed Descriptor */ 5977 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 5978 rsp_payload->port_speed_desc.desc_len = 5979 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 5980 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 5981 qla25xx_fdmi_port_speed_capability(ha)); 5982 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 5983 qla25xx_fdmi_port_speed_currently(ha)); 5984 5985 /* Link Error Status Descriptor */ 5986 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 5987 rsp_payload->ls_err_desc.desc_len = 5988 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 5989 5990 if (stat) { 5991 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 5992 if (!rval) { 5993 rsp_payload->ls_err_desc.link_fail_cnt = 5994 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 5995 rsp_payload->ls_err_desc.loss_sync_cnt = 5996 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 5997 rsp_payload->ls_err_desc.loss_sig_cnt = 5998 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 5999 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6000 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6001 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6002 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6003 rsp_payload->ls_err_desc.inval_crc_cnt = 6004 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6005 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6006 } 6007 } 6008 6009 /* Portname Descriptor */ 6010 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6011 rsp_payload->port_name_diag_desc.desc_len = 6012 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6013 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6014 vha->node_name, 6015 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6016 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6017 vha->port_name, 6018 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6019 6020 /* F-Port Portname Descriptor */ 6021 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6022 rsp_payload->port_name_direct_desc.desc_len = 6023 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6024 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6025 vha->fabric_node_name, 6026 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6027 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6028 vha->fabric_port_name, 6029 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6030 6031 /* Bufer Credit Descriptor */ 6032 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6033 rsp_payload->buffer_credit_desc.desc_len = 6034 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6035 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6036 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6037 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6038 6039 if (ha->flags.plogi_template_valid) { 6040 uint32_t tmp = 6041 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6042 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6043 } 6044 6045 if (rsp_payload_length < sizeof(*rsp_payload)) 6046 goto send; 6047 6048 /* Optical Element Descriptor, Temperature */ 6049 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6050 rsp_payload->optical_elmt_desc[0].desc_len = 6051 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6052 /* Optical Element Descriptor, Voltage */ 6053 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6054 rsp_payload->optical_elmt_desc[1].desc_len = 6055 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6056 /* Optical Element Descriptor, Tx Bias Current */ 6057 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6058 rsp_payload->optical_elmt_desc[2].desc_len = 6059 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6060 /* Optical Element Descriptor, Tx Power */ 6061 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6062 rsp_payload->optical_elmt_desc[3].desc_len = 6063 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6064 /* Optical Element Descriptor, Rx Power */ 6065 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6066 rsp_payload->optical_elmt_desc[4].desc_len = 6067 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6068 6069 if (sfp) { 6070 memset(sfp, 0, SFP_RTDI_LEN); 6071 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6072 if (!rval) { 6073 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6074 6075 /* Optical Element Descriptor, Temperature */ 6076 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6077 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6078 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6079 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6080 rsp_payload->optical_elmt_desc[0].element_flags = 6081 cpu_to_be32(1 << 28); 6082 6083 /* Optical Element Descriptor, Voltage */ 6084 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6085 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6086 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6087 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6088 rsp_payload->optical_elmt_desc[1].element_flags = 6089 cpu_to_be32(2 << 28); 6090 6091 /* Optical Element Descriptor, Tx Bias Current */ 6092 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6093 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6094 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6095 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6096 rsp_payload->optical_elmt_desc[2].element_flags = 6097 cpu_to_be32(3 << 28); 6098 6099 /* Optical Element Descriptor, Tx Power */ 6100 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6101 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6102 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6103 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6104 rsp_payload->optical_elmt_desc[3].element_flags = 6105 cpu_to_be32(4 << 28); 6106 6107 /* Optical Element Descriptor, Rx Power */ 6108 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6109 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6110 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6111 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6112 rsp_payload->optical_elmt_desc[4].element_flags = 6113 cpu_to_be32(5 << 28); 6114 } 6115 6116 memset(sfp, 0, SFP_RTDI_LEN); 6117 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6118 if (!rval) { 6119 /* Temperature high/low alarm/warning */ 6120 rsp_payload->optical_elmt_desc[0].element_flags |= 6121 cpu_to_be32( 6122 (sfp[0] >> 7 & 1) << 3 | 6123 (sfp[0] >> 6 & 1) << 2 | 6124 (sfp[4] >> 7 & 1) << 1 | 6125 (sfp[4] >> 6 & 1) << 0); 6126 6127 /* Voltage high/low alarm/warning */ 6128 rsp_payload->optical_elmt_desc[1].element_flags |= 6129 cpu_to_be32( 6130 (sfp[0] >> 5 & 1) << 3 | 6131 (sfp[0] >> 4 & 1) << 2 | 6132 (sfp[4] >> 5 & 1) << 1 | 6133 (sfp[4] >> 4 & 1) << 0); 6134 6135 /* Tx Bias Current high/low alarm/warning */ 6136 rsp_payload->optical_elmt_desc[2].element_flags |= 6137 cpu_to_be32( 6138 (sfp[0] >> 3 & 1) << 3 | 6139 (sfp[0] >> 2 & 1) << 2 | 6140 (sfp[4] >> 3 & 1) << 1 | 6141 (sfp[4] >> 2 & 1) << 0); 6142 6143 /* Tx Power high/low alarm/warning */ 6144 rsp_payload->optical_elmt_desc[3].element_flags |= 6145 cpu_to_be32( 6146 (sfp[0] >> 1 & 1) << 3 | 6147 (sfp[0] >> 0 & 1) << 2 | 6148 (sfp[4] >> 1 & 1) << 1 | 6149 (sfp[4] >> 0 & 1) << 0); 6150 6151 /* Rx Power high/low alarm/warning */ 6152 rsp_payload->optical_elmt_desc[4].element_flags |= 6153 cpu_to_be32( 6154 (sfp[1] >> 7 & 1) << 3 | 6155 (sfp[1] >> 6 & 1) << 2 | 6156 (sfp[5] >> 7 & 1) << 1 | 6157 (sfp[5] >> 6 & 1) << 0); 6158 } 6159 } 6160 6161 /* Optical Product Data Descriptor */ 6162 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6163 rsp_payload->optical_prod_desc.desc_len = 6164 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6165 6166 if (sfp) { 6167 memset(sfp, 0, SFP_RTDI_LEN); 6168 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6169 if (!rval) { 6170 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6171 sfp + 0, 6172 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6173 memcpy(rsp_payload->optical_prod_desc.part_number, 6174 sfp + 20, 6175 sizeof(rsp_payload->optical_prod_desc.part_number)); 6176 memcpy(rsp_payload->optical_prod_desc.revision, 6177 sfp + 36, 6178 sizeof(rsp_payload->optical_prod_desc.revision)); 6179 memcpy(rsp_payload->optical_prod_desc.serial_number, 6180 sfp + 48, 6181 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6182 } 6183 6184 memset(sfp, 0, SFP_RTDI_LEN); 6185 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6186 if (!rval) { 6187 memcpy(rsp_payload->optical_prod_desc.date, 6188 sfp + 0, 6189 sizeof(rsp_payload->optical_prod_desc.date)); 6190 } 6191 } 6192 6193send: 6194 ql_dbg(ql_dbg_init, vha, 0x0183, 6195 "Sending ELS Response to RDP Request...\n"); 6196 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6197 "-------- ELS RSP -------\n"); 6198 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6199 rsp_els, sizeof(*rsp_els)); 6200 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6201 "-------- ELS RSP PAYLOAD -------\n"); 6202 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6203 rsp_payload, rsp_payload_length); 6204 6205 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6206 6207 if (rval) { 6208 ql_log(ql_log_warn, vha, 0x0188, 6209 "%s: iocb failed to execute -> %x\n", __func__, rval); 6210 } else if (rsp_els->comp_status) { 6211 ql_log(ql_log_warn, vha, 0x0189, 6212 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6213 __func__, rsp_els->comp_status, 6214 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6215 } else { 6216 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6217 } 6218 6219dealloc: 6220 if (stat) 6221 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6222 stat, stat_dma); 6223 if (sfp) 6224 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6225 sfp, sfp_dma); 6226 if (rsp_payload) 6227 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6228 rsp_payload, rsp_payload_dma); 6229 if (rsp_els) 6230 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6231 rsp_els, rsp_els_dma); 6232} 6233 6234void 6235qla24xx_free_purex_item(struct purex_item *item) 6236{ 6237 if (item == &item->vha->default_item) 6238 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6239 else 6240 kfree(item); 6241} 6242 6243void qla24xx_process_purex_list(struct purex_list *list) 6244{ 6245 struct list_head head = LIST_HEAD_INIT(head); 6246 struct purex_item *item, *next; 6247 ulong flags; 6248 6249 spin_lock_irqsave(&list->lock, flags); 6250 list_splice_init(&list->head, &head); 6251 spin_unlock_irqrestore(&list->lock, flags); 6252 6253 list_for_each_entry_safe(item, next, &head, list) { 6254 list_del(&item->list); 6255 item->process_item(item->vha, item); 6256 qla24xx_free_purex_item(item); 6257 } 6258} 6259 6260void 6261qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6262{ 6263#if 0 6264 uint16_t options = (requester_id << 15) | BIT_7; 6265#endif 6266 uint16_t retry; 6267 uint32_t data; 6268 struct qla_hw_data *ha = base_vha->hw; 6269 6270 /* IDC-unlock implementation using driver-unlock/lock-id 6271 * remote registers 6272 */ 6273 retry = 0; 6274retry_unlock: 6275 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6276 == QLA_SUCCESS) { 6277 if (data == ha->portnum) { 6278 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6279 /* Clearing lock-id by setting 0xff */ 6280 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6281 } else if (retry < 10) { 6282 /* SV: XXX: IDC unlock retrying needed here? */ 6283 6284 /* Retry for IDC-unlock */ 6285 qla83xx_wait_logic(); 6286 retry++; 6287 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6288 "Failed to release IDC lock, retrying=%d\n", retry); 6289 goto retry_unlock; 6290 } 6291 } else if (retry < 10) { 6292 /* Retry for IDC-unlock */ 6293 qla83xx_wait_logic(); 6294 retry++; 6295 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6296 "Failed to read drv-lockid, retrying=%d\n", retry); 6297 goto retry_unlock; 6298 } 6299 6300 return; 6301 6302#if 0 6303 /* XXX: IDC-unlock implementation using access-control mbx */ 6304 retry = 0; 6305retry_unlock2: 6306 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6307 if (retry < 10) { 6308 /* Retry for IDC-unlock */ 6309 qla83xx_wait_logic(); 6310 retry++; 6311 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6312 "Failed to release IDC lock, retrying=%d\n", retry); 6313 goto retry_unlock2; 6314 } 6315 } 6316 6317 return; 6318#endif 6319} 6320 6321int 6322__qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6323{ 6324 int rval = QLA_SUCCESS; 6325 struct qla_hw_data *ha = vha->hw; 6326 uint32_t drv_presence; 6327 6328 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6329 if (rval == QLA_SUCCESS) { 6330 drv_presence |= (1 << ha->portnum); 6331 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6332 drv_presence); 6333 } 6334 6335 return rval; 6336} 6337 6338int 6339qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6340{ 6341 int rval = QLA_SUCCESS; 6342 6343 qla83xx_idc_lock(vha, 0); 6344 rval = __qla83xx_set_drv_presence(vha); 6345 qla83xx_idc_unlock(vha, 0); 6346 6347 return rval; 6348} 6349 6350int 6351__qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6352{ 6353 int rval = QLA_SUCCESS; 6354 struct qla_hw_data *ha = vha->hw; 6355 uint32_t drv_presence; 6356 6357 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6358 if (rval == QLA_SUCCESS) { 6359 drv_presence &= ~(1 << ha->portnum); 6360 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6361 drv_presence); 6362 } 6363 6364 return rval; 6365} 6366 6367int 6368qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6369{ 6370 int rval = QLA_SUCCESS; 6371 6372 qla83xx_idc_lock(vha, 0); 6373 rval = __qla83xx_clear_drv_presence(vha); 6374 qla83xx_idc_unlock(vha, 0); 6375 6376 return rval; 6377} 6378 6379static void 6380qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6381{ 6382 struct qla_hw_data *ha = vha->hw; 6383 uint32_t drv_ack, drv_presence; 6384 unsigned long ack_timeout; 6385 6386 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6387 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6388 while (1) { 6389 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6390 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6391 if ((drv_ack & drv_presence) == drv_presence) 6392 break; 6393 6394 if (time_after_eq(jiffies, ack_timeout)) { 6395 ql_log(ql_log_warn, vha, 0xb067, 6396 "RESET ACK TIMEOUT! drv_presence=0x%x " 6397 "drv_ack=0x%x\n", drv_presence, drv_ack); 6398 /* 6399 * The function(s) which did not ack in time are forced 6400 * to withdraw any further participation in the IDC 6401 * reset. 6402 */ 6403 if (drv_ack != drv_presence) 6404 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6405 drv_ack); 6406 break; 6407 } 6408 6409 qla83xx_idc_unlock(vha, 0); 6410 msleep(1000); 6411 qla83xx_idc_lock(vha, 0); 6412 } 6413 6414 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6415 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6416} 6417 6418static int 6419qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6420{ 6421 int rval = QLA_SUCCESS; 6422 uint32_t idc_control; 6423 6424 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6425 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6426 6427 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6428 __qla83xx_get_idc_control(vha, &idc_control); 6429 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6430 __qla83xx_set_idc_control(vha, 0); 6431 6432 qla83xx_idc_unlock(vha, 0); 6433 rval = qla83xx_restart_nic_firmware(vha); 6434 qla83xx_idc_lock(vha, 0); 6435 6436 if (rval != QLA_SUCCESS) { 6437 ql_log(ql_log_fatal, vha, 0xb06a, 6438 "Failed to restart NIC f/w.\n"); 6439 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6440 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6441 } else { 6442 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6443 "Success in restarting nic f/w.\n"); 6444 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6445 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6446 } 6447 6448 return rval; 6449} 6450 6451/* Assumes idc_lock always held on entry */ 6452int 6453qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6454{ 6455 struct qla_hw_data *ha = base_vha->hw; 6456 int rval = QLA_SUCCESS; 6457 unsigned long dev_init_timeout; 6458 uint32_t dev_state; 6459 6460 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6461 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6462 6463 while (1) { 6464 6465 if (time_after_eq(jiffies, dev_init_timeout)) { 6466 ql_log(ql_log_warn, base_vha, 0xb06e, 6467 "Initialization TIMEOUT!\n"); 6468 /* Init timeout. Disable further NIC Core 6469 * communication. 6470 */ 6471 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6472 QLA8XXX_DEV_FAILED); 6473 ql_log(ql_log_info, base_vha, 0xb06f, 6474 "HW State: FAILED.\n"); 6475 } 6476 6477 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6478 switch (dev_state) { 6479 case QLA8XXX_DEV_READY: 6480 if (ha->flags.nic_core_reset_owner) 6481 qla83xx_idc_audit(base_vha, 6482 IDC_AUDIT_COMPLETION); 6483 ha->flags.nic_core_reset_owner = 0; 6484 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6485 "Reset_owner reset by 0x%x.\n", 6486 ha->portnum); 6487 goto exit; 6488 case QLA8XXX_DEV_COLD: 6489 if (ha->flags.nic_core_reset_owner) 6490 rval = qla83xx_device_bootstrap(base_vha); 6491 else { 6492 /* Wait for AEN to change device-state */ 6493 qla83xx_idc_unlock(base_vha, 0); 6494 msleep(1000); 6495 qla83xx_idc_lock(base_vha, 0); 6496 } 6497 break; 6498 case QLA8XXX_DEV_INITIALIZING: 6499 /* Wait for AEN to change device-state */ 6500 qla83xx_idc_unlock(base_vha, 0); 6501 msleep(1000); 6502 qla83xx_idc_lock(base_vha, 0); 6503 break; 6504 case QLA8XXX_DEV_NEED_RESET: 6505 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6506 qla83xx_need_reset_handler(base_vha); 6507 else { 6508 /* Wait for AEN to change device-state */ 6509 qla83xx_idc_unlock(base_vha, 0); 6510 msleep(1000); 6511 qla83xx_idc_lock(base_vha, 0); 6512 } 6513 /* reset timeout value after need reset handler */ 6514 dev_init_timeout = jiffies + 6515 (ha->fcoe_dev_init_timeout * HZ); 6516 break; 6517 case QLA8XXX_DEV_NEED_QUIESCENT: 6518 /* XXX: DEBUG for now */ 6519 qla83xx_idc_unlock(base_vha, 0); 6520 msleep(1000); 6521 qla83xx_idc_lock(base_vha, 0); 6522 break; 6523 case QLA8XXX_DEV_QUIESCENT: 6524 /* XXX: DEBUG for now */ 6525 if (ha->flags.quiesce_owner) 6526 goto exit; 6527 6528 qla83xx_idc_unlock(base_vha, 0); 6529 msleep(1000); 6530 qla83xx_idc_lock(base_vha, 0); 6531 dev_init_timeout = jiffies + 6532 (ha->fcoe_dev_init_timeout * HZ); 6533 break; 6534 case QLA8XXX_DEV_FAILED: 6535 if (ha->flags.nic_core_reset_owner) 6536 qla83xx_idc_audit(base_vha, 6537 IDC_AUDIT_COMPLETION); 6538 ha->flags.nic_core_reset_owner = 0; 6539 __qla83xx_clear_drv_presence(base_vha); 6540 qla83xx_idc_unlock(base_vha, 0); 6541 qla8xxx_dev_failed_handler(base_vha); 6542 rval = QLA_FUNCTION_FAILED; 6543 qla83xx_idc_lock(base_vha, 0); 6544 goto exit; 6545 case QLA8XXX_BAD_VALUE: 6546 qla83xx_idc_unlock(base_vha, 0); 6547 msleep(1000); 6548 qla83xx_idc_lock(base_vha, 0); 6549 break; 6550 default: 6551 ql_log(ql_log_warn, base_vha, 0xb071, 6552 "Unknown Device State: %x.\n", dev_state); 6553 qla83xx_idc_unlock(base_vha, 0); 6554 qla8xxx_dev_failed_handler(base_vha); 6555 rval = QLA_FUNCTION_FAILED; 6556 qla83xx_idc_lock(base_vha, 0); 6557 goto exit; 6558 } 6559 } 6560 6561exit: 6562 return rval; 6563} 6564 6565void 6566qla2x00_disable_board_on_pci_error(struct work_struct *work) 6567{ 6568 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6569 board_disable); 6570 struct pci_dev *pdev = ha->pdev; 6571 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6572 6573 ql_log(ql_log_warn, base_vha, 0x015b, 6574 "Disabling adapter.\n"); 6575 6576 if (!atomic_read(&pdev->enable_cnt)) { 6577 ql_log(ql_log_info, base_vha, 0xfffc, 6578 "PCI device disabled, no action req for PCI error=%lx\n", 6579 base_vha->pci_flags); 6580 return; 6581 } 6582 6583 /* 6584 * if UNLOADING flag is already set, then continue unload, 6585 * where it was set first. 6586 */ 6587 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6588 return; 6589 6590 qla2x00_wait_for_sess_deletion(base_vha); 6591 6592 qla2x00_delete_all_vps(ha, base_vha); 6593 6594 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6595 6596 qla2x00_dfs_remove(base_vha); 6597 6598 qla84xx_put_chip(base_vha); 6599 6600 if (base_vha->timer_active) 6601 qla2x00_stop_timer(base_vha); 6602 6603 base_vha->flags.online = 0; 6604 6605 qla2x00_destroy_deferred_work(ha); 6606 6607 /* 6608 * Do not try to stop beacon blink as it will issue a mailbox 6609 * command. 6610 */ 6611 qla2x00_free_sysfs_attr(base_vha, false); 6612 6613 fc_remove_host(base_vha->host); 6614 6615 scsi_remove_host(base_vha->host); 6616 6617 base_vha->flags.init_done = 0; 6618 qla25xx_delete_queues(base_vha); 6619 qla2x00_free_fcports(base_vha); 6620 qla2x00_free_irqs(base_vha); 6621 qla2x00_mem_free(ha); 6622 qla82xx_md_free(base_vha); 6623 qla2x00_free_queues(ha); 6624 6625 qla2x00_unmap_iobases(ha); 6626 6627 pci_release_selected_regions(ha->pdev, ha->bars); 6628 pci_disable_pcie_error_reporting(pdev); 6629 pci_disable_device(pdev); 6630 6631 /* 6632 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6633 */ 6634} 6635 6636/************************************************************************** 6637* qla2x00_do_dpc 6638* This kernel thread is a task that is schedule by the interrupt handler 6639* to perform the background processing for interrupts. 6640* 6641* Notes: 6642* This task always run in the context of a kernel thread. It 6643* is kick-off by the driver's detect code and starts up 6644* up one per adapter. It immediately goes to sleep and waits for 6645* some fibre event. When either the interrupt handler or 6646* the timer routine detects a event it will one of the task 6647* bits then wake us up. 6648**************************************************************************/ 6649static int 6650qla2x00_do_dpc(void *data) 6651{ 6652 scsi_qla_host_t *base_vha; 6653 struct qla_hw_data *ha; 6654 uint32_t online; 6655 struct qla_qpair *qpair; 6656 6657 ha = (struct qla_hw_data *)data; 6658 base_vha = pci_get_drvdata(ha->pdev); 6659 6660 set_user_nice(current, MIN_NICE); 6661 6662 set_current_state(TASK_INTERRUPTIBLE); 6663 while (!kthread_should_stop()) { 6664 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6665 "DPC handler sleeping.\n"); 6666 6667 schedule(); 6668 6669 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6670 qla_pci_set_eeh_busy(base_vha); 6671 6672 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6673 goto end_loop; 6674 6675 if (ha->flags.eeh_busy) { 6676 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6677 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6678 goto end_loop; 6679 } 6680 6681 ha->dpc_active = 1; 6682 6683 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6684 "DPC handler waking up, dpc_flags=0x%lx.\n", 6685 base_vha->dpc_flags); 6686 6687 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6688 break; 6689 6690 if (IS_P3P_TYPE(ha)) { 6691 if (IS_QLA8044(ha)) { 6692 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6693 &base_vha->dpc_flags)) { 6694 qla8044_idc_lock(ha); 6695 qla8044_wr_direct(base_vha, 6696 QLA8044_CRB_DEV_STATE_INDEX, 6697 QLA8XXX_DEV_FAILED); 6698 qla8044_idc_unlock(ha); 6699 ql_log(ql_log_info, base_vha, 0x4004, 6700 "HW State: FAILED.\n"); 6701 qla8044_device_state_handler(base_vha); 6702 continue; 6703 } 6704 6705 } else { 6706 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6707 &base_vha->dpc_flags)) { 6708 qla82xx_idc_lock(ha); 6709 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6710 QLA8XXX_DEV_FAILED); 6711 qla82xx_idc_unlock(ha); 6712 ql_log(ql_log_info, base_vha, 0x0151, 6713 "HW State: FAILED.\n"); 6714 qla82xx_device_state_handler(base_vha); 6715 continue; 6716 } 6717 } 6718 6719 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6720 &base_vha->dpc_flags)) { 6721 6722 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6723 "FCoE context reset scheduled.\n"); 6724 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6725 &base_vha->dpc_flags))) { 6726 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6727 /* FCoE-ctx reset failed. 6728 * Escalate to chip-reset 6729 */ 6730 set_bit(ISP_ABORT_NEEDED, 6731 &base_vha->dpc_flags); 6732 } 6733 clear_bit(ABORT_ISP_ACTIVE, 6734 &base_vha->dpc_flags); 6735 } 6736 6737 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6738 "FCoE context reset end.\n"); 6739 } 6740 } else if (IS_QLAFX00(ha)) { 6741 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6742 &base_vha->dpc_flags)) { 6743 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6744 "Firmware Reset Recovery\n"); 6745 if (qlafx00_reset_initialize(base_vha)) { 6746 /* Failed. Abort isp later. */ 6747 if (!test_bit(UNLOADING, 6748 &base_vha->dpc_flags)) { 6749 set_bit(ISP_UNRECOVERABLE, 6750 &base_vha->dpc_flags); 6751 ql_dbg(ql_dbg_dpc, base_vha, 6752 0x4021, 6753 "Reset Recovery Failed\n"); 6754 } 6755 } 6756 } 6757 6758 if (test_and_clear_bit(FX00_TARGET_SCAN, 6759 &base_vha->dpc_flags)) { 6760 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6761 "ISPFx00 Target Scan scheduled\n"); 6762 if (qlafx00_rescan_isp(base_vha)) { 6763 if (!test_bit(UNLOADING, 6764 &base_vha->dpc_flags)) 6765 set_bit(ISP_UNRECOVERABLE, 6766 &base_vha->dpc_flags); 6767 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6768 "ISPFx00 Target Scan Failed\n"); 6769 } 6770 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6771 "ISPFx00 Target Scan End\n"); 6772 } 6773 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6774 &base_vha->dpc_flags)) { 6775 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6776 "ISPFx00 Host Info resend scheduled\n"); 6777 qlafx00_fx_disc(base_vha, 6778 &base_vha->hw->mr.fcport, 6779 FXDISC_REG_HOST_INFO); 6780 } 6781 } 6782 6783 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6784 &base_vha->dpc_flags)) { 6785 /* Semantic: 6786 * - NO-OP -- await next ISP-ABORT. Preferred method 6787 * to minimize disruptions that will occur 6788 * when a forced chip-reset occurs. 6789 * - Force -- ISP-ABORT scheduled. 6790 */ 6791 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6792 } 6793 6794 if (test_and_clear_bit 6795 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6796 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6797 bool do_reset = true; 6798 6799 switch (base_vha->qlini_mode) { 6800 case QLA2XXX_INI_MODE_ENABLED: 6801 break; 6802 case QLA2XXX_INI_MODE_DISABLED: 6803 if (!qla_tgt_mode_enabled(base_vha) && 6804 !ha->flags.fw_started) 6805 do_reset = false; 6806 break; 6807 case QLA2XXX_INI_MODE_DUAL: 6808 if (!qla_dual_mode_enabled(base_vha) && 6809 !ha->flags.fw_started) 6810 do_reset = false; 6811 break; 6812 default: 6813 break; 6814 } 6815 6816 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6817 &base_vha->dpc_flags))) { 6818 base_vha->flags.online = 1; 6819 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6820 "ISP abort scheduled.\n"); 6821 if (ha->isp_ops->abort_isp(base_vha)) { 6822 /* failed. retry later */ 6823 set_bit(ISP_ABORT_NEEDED, 6824 &base_vha->dpc_flags); 6825 } 6826 clear_bit(ABORT_ISP_ACTIVE, 6827 &base_vha->dpc_flags); 6828 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6829 "ISP abort end.\n"); 6830 } 6831 } 6832 6833 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6834 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6835 qla24xx_process_purex_list 6836 (&base_vha->purex_list); 6837 clear_bit(PROCESS_PUREX_IOCB, 6838 &base_vha->dpc_flags); 6839 } 6840 } 6841 6842 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6843 &base_vha->dpc_flags)) { 6844 qla2x00_update_fcports(base_vha); 6845 } 6846 6847 if (IS_QLAFX00(ha)) 6848 goto loop_resync_check; 6849 6850 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6851 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6852 "Quiescence mode scheduled.\n"); 6853 if (IS_P3P_TYPE(ha)) { 6854 if (IS_QLA82XX(ha)) 6855 qla82xx_device_state_handler(base_vha); 6856 if (IS_QLA8044(ha)) 6857 qla8044_device_state_handler(base_vha); 6858 clear_bit(ISP_QUIESCE_NEEDED, 6859 &base_vha->dpc_flags); 6860 if (!ha->flags.quiesce_owner) { 6861 qla2x00_perform_loop_resync(base_vha); 6862 if (IS_QLA82XX(ha)) { 6863 qla82xx_idc_lock(ha); 6864 qla82xx_clear_qsnt_ready( 6865 base_vha); 6866 qla82xx_idc_unlock(ha); 6867 } else if (IS_QLA8044(ha)) { 6868 qla8044_idc_lock(ha); 6869 qla8044_clear_qsnt_ready( 6870 base_vha); 6871 qla8044_idc_unlock(ha); 6872 } 6873 } 6874 } else { 6875 clear_bit(ISP_QUIESCE_NEEDED, 6876 &base_vha->dpc_flags); 6877 qla2x00_quiesce_io(base_vha); 6878 } 6879 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6880 "Quiescence mode end.\n"); 6881 } 6882 6883 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6884 &base_vha->dpc_flags) && 6885 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6886 6887 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6888 "Reset marker scheduled.\n"); 6889 qla2x00_rst_aen(base_vha); 6890 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6891 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6892 "Reset marker end.\n"); 6893 } 6894 6895 /* Retry each device up to login retry count */ 6896 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6897 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6898 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6899 6900 if (!base_vha->relogin_jif || 6901 time_after_eq(jiffies, base_vha->relogin_jif)) { 6902 base_vha->relogin_jif = jiffies + HZ; 6903 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6904 6905 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6906 "Relogin scheduled.\n"); 6907 qla24xx_post_relogin_work(base_vha); 6908 } 6909 } 6910loop_resync_check: 6911 if (!qla2x00_reset_active(base_vha) && 6912 test_and_clear_bit(LOOP_RESYNC_NEEDED, 6913 &base_vha->dpc_flags)) { 6914 /* 6915 * Allow abort_isp to complete before moving on to scanning. 6916 */ 6917 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6918 "Loop resync scheduled.\n"); 6919 6920 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6921 &base_vha->dpc_flags))) { 6922 6923 qla2x00_loop_resync(base_vha); 6924 6925 clear_bit(LOOP_RESYNC_ACTIVE, 6926 &base_vha->dpc_flags); 6927 } 6928 6929 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6930 "Loop resync end.\n"); 6931 } 6932 6933 if (IS_QLAFX00(ha)) 6934 goto intr_on_check; 6935 6936 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6937 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6938 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6939 qla2xxx_flash_npiv_conf(base_vha); 6940 } 6941 6942intr_on_check: 6943 if (!ha->interrupts_on) 6944 ha->isp_ops->enable_intrs(ha); 6945 6946 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6947 &base_vha->dpc_flags)) { 6948 if (ha->beacon_blink_led == 1) 6949 ha->isp_ops->beacon_blink(base_vha); 6950 } 6951 6952 /* qpair online check */ 6953 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6954 &base_vha->dpc_flags)) { 6955 if (ha->flags.eeh_busy || 6956 ha->flags.pci_channel_io_perm_failure) 6957 online = 0; 6958 else 6959 online = 1; 6960 6961 mutex_lock(&ha->mq_lock); 6962 list_for_each_entry(qpair, &base_vha->qp_list, 6963 qp_list_elem) 6964 qpair->online = online; 6965 mutex_unlock(&ha->mq_lock); 6966 } 6967 6968 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6969 &base_vha->dpc_flags)) { 6970 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 6971 6972 if (threshold > ha->orig_fw_xcb_count) 6973 threshold = ha->orig_fw_xcb_count; 6974 6975 ql_log(ql_log_info, base_vha, 0xffffff, 6976 "SET ZIO Activity exchange threshold to %d.\n", 6977 threshold); 6978 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 6979 ql_log(ql_log_info, base_vha, 0xffffff, 6980 "Unable to SET ZIO Activity exchange threshold to %d.\n", 6981 threshold); 6982 } 6983 } 6984 6985 if (!IS_QLAFX00(ha)) 6986 qla2x00_do_dpc_all_vps(base_vha); 6987 6988 if (test_and_clear_bit(N2N_LINK_RESET, 6989 &base_vha->dpc_flags)) { 6990 qla2x00_lip_reset(base_vha); 6991 } 6992 6993 ha->dpc_active = 0; 6994end_loop: 6995 set_current_state(TASK_INTERRUPTIBLE); 6996 } /* End of while(1) */ 6997 __set_current_state(TASK_RUNNING); 6998 6999 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7000 "DPC handler exiting.\n"); 7001 7002 /* 7003 * Make sure that nobody tries to wake us up again. 7004 */ 7005 ha->dpc_active = 0; 7006 7007 /* Cleanup any residual CTX SRBs. */ 7008 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7009 7010 return 0; 7011} 7012 7013void 7014qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7015{ 7016 struct qla_hw_data *ha = vha->hw; 7017 struct task_struct *t = ha->dpc_thread; 7018 7019 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7020 wake_up_process(t); 7021} 7022 7023/* 7024* qla2x00_rst_aen 7025* Processes asynchronous reset. 7026* 7027* Input: 7028* ha = adapter block pointer. 7029*/ 7030static void 7031qla2x00_rst_aen(scsi_qla_host_t *vha) 7032{ 7033 if (vha->flags.online && !vha->flags.reset_active && 7034 !atomic_read(&vha->loop_down_timer) && 7035 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7036 do { 7037 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7038 7039 /* 7040 * Issue marker command only when we are going to start 7041 * the I/O. 7042 */ 7043 vha->marker_needed = 1; 7044 } while (!atomic_read(&vha->loop_down_timer) && 7045 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7046 } 7047} 7048 7049/************************************************************************** 7050* qla2x00_timer 7051* 7052* Description: 7053* One second timer 7054* 7055* Context: Interrupt 7056***************************************************************************/ 7057void 7058qla2x00_timer(struct timer_list *t) 7059{ 7060 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7061 unsigned long cpu_flags = 0; 7062 int start_dpc = 0; 7063 int index; 7064 srb_t *sp; 7065 uint16_t w; 7066 struct qla_hw_data *ha = vha->hw; 7067 struct req_que *req; 7068 7069 if (ha->flags.eeh_busy) { 7070 ql_dbg(ql_dbg_timer, vha, 0x6000, 7071 "EEH = %d, restarting timer.\n", 7072 ha->flags.eeh_busy); 7073 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7074 return; 7075 } 7076 7077 /* 7078 * Hardware read to raise pending EEH errors during mailbox waits. If 7079 * the read returns -1 then disable the board. 7080 */ 7081 if (!pci_channel_offline(ha->pdev)) { 7082 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7083 qla2x00_check_reg16_for_disconnect(vha, w); 7084 } 7085 7086 /* Make sure qla82xx_watchdog is run only for physical port */ 7087 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7088 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7089 start_dpc++; 7090 if (IS_QLA82XX(ha)) 7091 qla82xx_watchdog(vha); 7092 else if (IS_QLA8044(ha)) 7093 qla8044_watchdog(vha); 7094 } 7095 7096 if (!vha->vp_idx && IS_QLAFX00(ha)) 7097 qlafx00_timer_routine(vha); 7098 7099 /* Loop down handler. */ 7100 if (atomic_read(&vha->loop_down_timer) > 0 && 7101 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7102 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7103 && vha->flags.online) { 7104 7105 if (atomic_read(&vha->loop_down_timer) == 7106 vha->loop_down_abort_time) { 7107 7108 ql_log(ql_log_info, vha, 0x6008, 7109 "Loop down - aborting the queues before time expires.\n"); 7110 7111 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7112 atomic_set(&vha->loop_state, LOOP_DEAD); 7113 7114 /* 7115 * Schedule an ISP abort to return any FCP2-device 7116 * commands. 7117 */ 7118 /* NPIV - scan physical port only */ 7119 if (!vha->vp_idx) { 7120 spin_lock_irqsave(&ha->hardware_lock, 7121 cpu_flags); 7122 req = ha->req_q_map[0]; 7123 for (index = 1; 7124 index < req->num_outstanding_cmds; 7125 index++) { 7126 fc_port_t *sfcp; 7127 7128 sp = req->outstanding_cmds[index]; 7129 if (!sp) 7130 continue; 7131 if (sp->cmd_type != TYPE_SRB) 7132 continue; 7133 if (sp->type != SRB_SCSI_CMD) 7134 continue; 7135 sfcp = sp->fcport; 7136 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7137 continue; 7138 7139 if (IS_QLA82XX(ha)) 7140 set_bit(FCOE_CTX_RESET_NEEDED, 7141 &vha->dpc_flags); 7142 else 7143 set_bit(ISP_ABORT_NEEDED, 7144 &vha->dpc_flags); 7145 break; 7146 } 7147 spin_unlock_irqrestore(&ha->hardware_lock, 7148 cpu_flags); 7149 } 7150 start_dpc++; 7151 } 7152 7153 /* if the loop has been down for 4 minutes, reinit adapter */ 7154 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7155 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7156 ql_log(ql_log_warn, vha, 0x6009, 7157 "Loop down - aborting ISP.\n"); 7158 7159 if (IS_QLA82XX(ha)) 7160 set_bit(FCOE_CTX_RESET_NEEDED, 7161 &vha->dpc_flags); 7162 else 7163 set_bit(ISP_ABORT_NEEDED, 7164 &vha->dpc_flags); 7165 } 7166 } 7167 ql_dbg(ql_dbg_timer, vha, 0x600a, 7168 "Loop down - seconds remaining %d.\n", 7169 atomic_read(&vha->loop_down_timer)); 7170 } 7171 /* Check if beacon LED needs to be blinked for physical host only */ 7172 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7173 /* There is no beacon_blink function for ISP82xx */ 7174 if (!IS_P3P_TYPE(ha)) { 7175 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7176 start_dpc++; 7177 } 7178 } 7179 7180 /* Process any deferred work. */ 7181 if (!list_empty(&vha->work_list)) { 7182 unsigned long flags; 7183 bool q = false; 7184 7185 spin_lock_irqsave(&vha->work_lock, flags); 7186 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7187 q = true; 7188 spin_unlock_irqrestore(&vha->work_lock, flags); 7189 if (q) 7190 queue_work(vha->hw->wq, &vha->iocb_work); 7191 } 7192 7193 /* 7194 * FC-NVME 7195 * see if the active AEN count has changed from what was last reported. 7196 */ 7197 index = atomic_read(&ha->nvme_active_aen_cnt); 7198 if (!vha->vp_idx && 7199 (index != ha->nvme_last_rptd_aen) && 7200 ha->zio_mode == QLA_ZIO_MODE_6 && 7201 !ha->flags.host_shutting_down) { 7202 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7203 ql_log(ql_log_info, vha, 0x3002, 7204 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7205 ha->nvme_last_rptd_aen); 7206 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7207 start_dpc++; 7208 } 7209 7210 if (!vha->vp_idx && 7211 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7212 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7213 ql_log(ql_log_info, vha, 0x3002, 7214 "Sched: Set ZIO exchange threshold to %d.\n", 7215 ha->last_zio_threshold); 7216 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7217 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7218 start_dpc++; 7219 } 7220 7221 /* Schedule the DPC routine if needed */ 7222 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7223 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7224 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7225 start_dpc || 7226 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7227 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7228 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7229 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7230 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7231 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7232 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7233 ql_dbg(ql_dbg_timer, vha, 0x600b, 7234 "isp_abort_needed=%d loop_resync_needed=%d " 7235 "fcport_update_needed=%d start_dpc=%d " 7236 "reset_marker_needed=%d", 7237 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7238 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7239 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7240 start_dpc, 7241 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7242 ql_dbg(ql_dbg_timer, vha, 0x600c, 7243 "beacon_blink_needed=%d isp_unrecoverable=%d " 7244 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7245 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7246 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7247 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7248 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7249 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7250 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7251 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7252 qla2xxx_wake_dpc(vha); 7253 } 7254 7255 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7256} 7257 7258/* Firmware interface routines. */ 7259 7260#define FW_ISP21XX 0 7261#define FW_ISP22XX 1 7262#define FW_ISP2300 2 7263#define FW_ISP2322 3 7264#define FW_ISP24XX 4 7265#define FW_ISP25XX 5 7266#define FW_ISP81XX 6 7267#define FW_ISP82XX 7 7268#define FW_ISP2031 8 7269#define FW_ISP8031 9 7270#define FW_ISP27XX 10 7271#define FW_ISP28XX 11 7272 7273#define FW_FILE_ISP21XX "ql2100_fw.bin" 7274#define FW_FILE_ISP22XX "ql2200_fw.bin" 7275#define FW_FILE_ISP2300 "ql2300_fw.bin" 7276#define FW_FILE_ISP2322 "ql2322_fw.bin" 7277#define FW_FILE_ISP24XX "ql2400_fw.bin" 7278#define FW_FILE_ISP25XX "ql2500_fw.bin" 7279#define FW_FILE_ISP81XX "ql8100_fw.bin" 7280#define FW_FILE_ISP82XX "ql8200_fw.bin" 7281#define FW_FILE_ISP2031 "ql2600_fw.bin" 7282#define FW_FILE_ISP8031 "ql8300_fw.bin" 7283#define FW_FILE_ISP27XX "ql2700_fw.bin" 7284#define FW_FILE_ISP28XX "ql2800_fw.bin" 7285 7286 7287static DEFINE_MUTEX(qla_fw_lock); 7288 7289static struct fw_blob qla_fw_blobs[] = { 7290 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7291 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7292 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7293 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7294 { .name = FW_FILE_ISP24XX, }, 7295 { .name = FW_FILE_ISP25XX, }, 7296 { .name = FW_FILE_ISP81XX, }, 7297 { .name = FW_FILE_ISP82XX, }, 7298 { .name = FW_FILE_ISP2031, }, 7299 { .name = FW_FILE_ISP8031, }, 7300 { .name = FW_FILE_ISP27XX, }, 7301 { .name = FW_FILE_ISP28XX, }, 7302 { .name = NULL, }, 7303}; 7304 7305struct fw_blob * 7306qla2x00_request_firmware(scsi_qla_host_t *vha) 7307{ 7308 struct qla_hw_data *ha = vha->hw; 7309 struct fw_blob *blob; 7310 7311 if (IS_QLA2100(ha)) { 7312 blob = &qla_fw_blobs[FW_ISP21XX]; 7313 } else if (IS_QLA2200(ha)) { 7314 blob = &qla_fw_blobs[FW_ISP22XX]; 7315 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7316 blob = &qla_fw_blobs[FW_ISP2300]; 7317 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7318 blob = &qla_fw_blobs[FW_ISP2322]; 7319 } else if (IS_QLA24XX_TYPE(ha)) { 7320 blob = &qla_fw_blobs[FW_ISP24XX]; 7321 } else if (IS_QLA25XX(ha)) { 7322 blob = &qla_fw_blobs[FW_ISP25XX]; 7323 } else if (IS_QLA81XX(ha)) { 7324 blob = &qla_fw_blobs[FW_ISP81XX]; 7325 } else if (IS_QLA82XX(ha)) { 7326 blob = &qla_fw_blobs[FW_ISP82XX]; 7327 } else if (IS_QLA2031(ha)) { 7328 blob = &qla_fw_blobs[FW_ISP2031]; 7329 } else if (IS_QLA8031(ha)) { 7330 blob = &qla_fw_blobs[FW_ISP8031]; 7331 } else if (IS_QLA27XX(ha)) { 7332 blob = &qla_fw_blobs[FW_ISP27XX]; 7333 } else if (IS_QLA28XX(ha)) { 7334 blob = &qla_fw_blobs[FW_ISP28XX]; 7335 } else { 7336 return NULL; 7337 } 7338 7339 if (!blob->name) 7340 return NULL; 7341 7342 mutex_lock(&qla_fw_lock); 7343 if (blob->fw) 7344 goto out; 7345 7346 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7347 ql_log(ql_log_warn, vha, 0x0063, 7348 "Failed to load firmware image (%s).\n", blob->name); 7349 blob->fw = NULL; 7350 blob = NULL; 7351 } 7352 7353out: 7354 mutex_unlock(&qla_fw_lock); 7355 return blob; 7356} 7357 7358static void 7359qla2x00_release_firmware(void) 7360{ 7361 struct fw_blob *blob; 7362 7363 mutex_lock(&qla_fw_lock); 7364 for (blob = qla_fw_blobs; blob->name; blob++) 7365 release_firmware(blob->fw); 7366 mutex_unlock(&qla_fw_lock); 7367} 7368 7369static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7370{ 7371 struct qla_hw_data *ha = vha->hw; 7372 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7373 struct qla_qpair *qpair = NULL; 7374 struct scsi_qla_host *vp; 7375 fc_port_t *fcport; 7376 int i; 7377 unsigned long flags; 7378 7379 ql_dbg(ql_dbg_aer, vha, 0x9000, 7380 "%s\n", __func__); 7381 ha->chip_reset++; 7382 7383 ha->base_qpair->chip_reset = ha->chip_reset; 7384 for (i = 0; i < ha->max_qpairs; i++) { 7385 if (ha->queue_pair_map[i]) 7386 ha->queue_pair_map[i]->chip_reset = 7387 ha->base_qpair->chip_reset; 7388 } 7389 7390 /* 7391 * purge mailbox might take a while. Slot Reset/chip reset 7392 * will take care of the purge 7393 */ 7394 7395 mutex_lock(&ha->mq_lock); 7396 ha->base_qpair->online = 0; 7397 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7398 qpair->online = 0; 7399 wmb(); 7400 mutex_unlock(&ha->mq_lock); 7401 7402 qla2x00_mark_all_devices_lost(vha); 7403 7404 spin_lock_irqsave(&ha->vport_slock, flags); 7405 list_for_each_entry(vp, &ha->vp_list, list) { 7406 atomic_inc(&vp->vref_count); 7407 spin_unlock_irqrestore(&ha->vport_slock, flags); 7408 qla2x00_mark_all_devices_lost(vp); 7409 spin_lock_irqsave(&ha->vport_slock, flags); 7410 atomic_dec(&vp->vref_count); 7411 } 7412 spin_unlock_irqrestore(&ha->vport_slock, flags); 7413 7414 /* Clear all async request states across all VPs. */ 7415 list_for_each_entry(fcport, &vha->vp_fcports, list) 7416 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7417 7418 spin_lock_irqsave(&ha->vport_slock, flags); 7419 list_for_each_entry(vp, &ha->vp_list, list) { 7420 atomic_inc(&vp->vref_count); 7421 spin_unlock_irqrestore(&ha->vport_slock, flags); 7422 list_for_each_entry(fcport, &vp->vp_fcports, list) 7423 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7424 spin_lock_irqsave(&ha->vport_slock, flags); 7425 atomic_dec(&vp->vref_count); 7426 } 7427 spin_unlock_irqrestore(&ha->vport_slock, flags); 7428} 7429 7430 7431static pci_ers_result_t 7432qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7433{ 7434 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7435 struct qla_hw_data *ha = vha->hw; 7436 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7437 7438 ql_log(ql_log_warn, vha, 0x9000, 7439 "PCI error detected, state %x.\n", state); 7440 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7441 7442 if (!atomic_read(&pdev->enable_cnt)) { 7443 ql_log(ql_log_info, vha, 0xffff, 7444 "PCI device is disabled,state %x\n", state); 7445 ret = PCI_ERS_RESULT_NEED_RESET; 7446 goto out; 7447 } 7448 7449 switch (state) { 7450 case pci_channel_io_normal: 7451 ha->flags.eeh_busy = 0; 7452 if (ql2xmqsupport || ql2xnvmeenable) { 7453 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7454 qla2xxx_wake_dpc(vha); 7455 } 7456 ret = PCI_ERS_RESULT_CAN_RECOVER; 7457 break; 7458 case pci_channel_io_frozen: 7459 qla_pci_set_eeh_busy(vha); 7460 ret = PCI_ERS_RESULT_NEED_RESET; 7461 break; 7462 case pci_channel_io_perm_failure: 7463 ha->flags.pci_channel_io_perm_failure = 1; 7464 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7465 if (ql2xmqsupport || ql2xnvmeenable) { 7466 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7467 qla2xxx_wake_dpc(vha); 7468 } 7469 ret = PCI_ERS_RESULT_DISCONNECT; 7470 } 7471out: 7472 ql_dbg(ql_dbg_aer, vha, 0x600d, 7473 "PCI error detected returning [%x].\n", ret); 7474 return ret; 7475} 7476 7477static pci_ers_result_t 7478qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7479{ 7480 int risc_paused = 0; 7481 uint32_t stat; 7482 unsigned long flags; 7483 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7484 struct qla_hw_data *ha = base_vha->hw; 7485 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7486 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7487 7488 ql_log(ql_log_warn, base_vha, 0x9000, 7489 "mmio enabled\n"); 7490 7491 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7492 if (IS_QLA82XX(ha)) 7493 return PCI_ERS_RESULT_RECOVERED; 7494 7495 spin_lock_irqsave(&ha->hardware_lock, flags); 7496 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7497 stat = rd_reg_word(®->hccr); 7498 if (stat & HCCR_RISC_PAUSE) 7499 risc_paused = 1; 7500 } else if (IS_QLA23XX(ha)) { 7501 stat = rd_reg_dword(®->u.isp2300.host_status); 7502 if (stat & HSR_RISC_PAUSED) 7503 risc_paused = 1; 7504 } else if (IS_FWI2_CAPABLE(ha)) { 7505 stat = rd_reg_dword(®24->host_status); 7506 if (stat & HSRX_RISC_PAUSED) 7507 risc_paused = 1; 7508 } 7509 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7510 7511 if (risc_paused) { 7512 ql_log(ql_log_info, base_vha, 0x9003, 7513 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7514 qla2xxx_dump_fw(base_vha); 7515 } 7516 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7517 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7518 "mmio enabled returning.\n"); 7519 return PCI_ERS_RESULT_NEED_RESET; 7520} 7521 7522static pci_ers_result_t 7523qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7524{ 7525 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7526 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7527 struct qla_hw_data *ha = base_vha->hw; 7528 int rc; 7529 struct qla_qpair *qpair = NULL; 7530 7531 ql_log(ql_log_warn, base_vha, 0x9004, 7532 "Slot Reset.\n"); 7533 7534 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7535 /* Workaround: qla2xxx driver which access hardware earlier 7536 * needs error state to be pci_channel_io_online. 7537 * Otherwise mailbox command timesout. 7538 */ 7539 pdev->error_state = pci_channel_io_normal; 7540 7541 pci_restore_state(pdev); 7542 7543 /* pci_restore_state() clears the saved_state flag of the device 7544 * save restored state which resets saved_state flag 7545 */ 7546 pci_save_state(pdev); 7547 7548 if (ha->mem_only) 7549 rc = pci_enable_device_mem(pdev); 7550 else 7551 rc = pci_enable_device(pdev); 7552 7553 if (rc) { 7554 ql_log(ql_log_warn, base_vha, 0x9005, 7555 "Can't re-enable PCI device after reset.\n"); 7556 goto exit_slot_reset; 7557 } 7558 7559 7560 if (ha->isp_ops->pci_config(base_vha)) 7561 goto exit_slot_reset; 7562 7563 mutex_lock(&ha->mq_lock); 7564 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7565 qpair->online = 1; 7566 mutex_unlock(&ha->mq_lock); 7567 7568 ha->flags.eeh_busy = 0; 7569 base_vha->flags.online = 1; 7570 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7571 ha->isp_ops->abort_isp(base_vha); 7572 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7573 7574 if (qla2x00_isp_reg_stat(ha)) { 7575 ha->flags.eeh_busy = 1; 7576 qla_pci_error_cleanup(base_vha); 7577 ql_log(ql_log_warn, base_vha, 0x9005, 7578 "Device unable to recover from PCI error.\n"); 7579 } else { 7580 ret = PCI_ERS_RESULT_RECOVERED; 7581 } 7582 7583exit_slot_reset: 7584 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7585 "Slot Reset returning %x.\n", ret); 7586 7587 return ret; 7588} 7589 7590static void 7591qla2xxx_pci_resume(struct pci_dev *pdev) 7592{ 7593 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7594 struct qla_hw_data *ha = base_vha->hw; 7595 int ret; 7596 7597 ql_log(ql_log_warn, base_vha, 0x900f, 7598 "Pci Resume.\n"); 7599 7600 7601 ret = qla2x00_wait_for_hba_online(base_vha); 7602 if (ret != QLA_SUCCESS) { 7603 ql_log(ql_log_fatal, base_vha, 0x9002, 7604 "The device failed to resume I/O from slot/link_reset.\n"); 7605 } 7606 ha->pci_error_state = QLA_PCI_RESUME; 7607 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7608 "Pci Resume returning.\n"); 7609} 7610 7611void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7612{ 7613 struct qla_hw_data *ha = vha->hw; 7614 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7615 bool do_cleanup = false; 7616 unsigned long flags; 7617 7618 if (ha->flags.eeh_busy) 7619 return; 7620 7621 spin_lock_irqsave(&base_vha->work_lock, flags); 7622 if (!ha->flags.eeh_busy) { 7623 ha->flags.eeh_busy = 1; 7624 do_cleanup = true; 7625 } 7626 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7627 7628 if (do_cleanup) 7629 qla_pci_error_cleanup(base_vha); 7630} 7631 7632/* 7633 * this routine will schedule a task to pause IO from interrupt context 7634 * if caller sees a PCIE error event (register read = 0xf's) 7635 */ 7636void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7637{ 7638 struct qla_hw_data *ha = vha->hw; 7639 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7640 7641 if (ha->flags.eeh_busy) 7642 return; 7643 7644 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7645 qla2xxx_wake_dpc(base_vha); 7646} 7647 7648static void 7649qla_pci_reset_prepare(struct pci_dev *pdev) 7650{ 7651 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7652 struct qla_hw_data *ha = base_vha->hw; 7653 struct qla_qpair *qpair; 7654 7655 ql_log(ql_log_warn, base_vha, 0xffff, 7656 "%s.\n", __func__); 7657 7658 /* 7659 * PCI FLR/function reset is about to reset the 7660 * slot. Stop the chip to stop all DMA access. 7661 * It is assumed that pci_reset_done will be called 7662 * after FLR to resume Chip operation. 7663 */ 7664 ha->flags.eeh_busy = 1; 7665 mutex_lock(&ha->mq_lock); 7666 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7667 qpair->online = 0; 7668 mutex_unlock(&ha->mq_lock); 7669 7670 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7671 qla2x00_abort_isp_cleanup(base_vha); 7672 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7673} 7674 7675static void 7676qla_pci_reset_done(struct pci_dev *pdev) 7677{ 7678 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7679 struct qla_hw_data *ha = base_vha->hw; 7680 struct qla_qpair *qpair; 7681 7682 ql_log(ql_log_warn, base_vha, 0xffff, 7683 "%s.\n", __func__); 7684 7685 /* 7686 * FLR just completed by PCI layer. Resume adapter 7687 */ 7688 ha->flags.eeh_busy = 0; 7689 mutex_lock(&ha->mq_lock); 7690 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7691 qpair->online = 1; 7692 mutex_unlock(&ha->mq_lock); 7693 7694 base_vha->flags.online = 1; 7695 ha->isp_ops->abort_isp(base_vha); 7696 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7697} 7698 7699static int qla2xxx_map_queues(struct Scsi_Host *shost) 7700{ 7701 int rc; 7702 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7703 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7704 7705 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7706 rc = blk_mq_map_queues(qmap); 7707 else 7708 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7709 return rc; 7710} 7711 7712struct scsi_host_template qla2xxx_driver_template = { 7713 .module = THIS_MODULE, 7714 .name = QLA2XXX_DRIVER_NAME, 7715 .queuecommand = qla2xxx_queuecommand, 7716 7717 .eh_timed_out = fc_eh_timed_out, 7718 .eh_abort_handler = qla2xxx_eh_abort, 7719 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7720 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7721 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7722 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7723 7724 .slave_configure = qla2xxx_slave_configure, 7725 7726 .slave_alloc = qla2xxx_slave_alloc, 7727 .slave_destroy = qla2xxx_slave_destroy, 7728 .scan_finished = qla2xxx_scan_finished, 7729 .scan_start = qla2xxx_scan_start, 7730 .change_queue_depth = scsi_change_queue_depth, 7731 .map_queues = qla2xxx_map_queues, 7732 .this_id = -1, 7733 .cmd_per_lun = 3, 7734 .sg_tablesize = SG_ALL, 7735 7736 .max_sectors = 0xFFFF, 7737 .shost_attrs = qla2x00_host_attrs, 7738 7739 .supported_mode = MODE_INITIATOR, 7740 .track_queue_depth = 1, 7741 .cmd_size = sizeof(srb_t), 7742}; 7743 7744static const struct pci_error_handlers qla2xxx_err_handler = { 7745 .error_detected = qla2xxx_pci_error_detected, 7746 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7747 .slot_reset = qla2xxx_pci_slot_reset, 7748 .resume = qla2xxx_pci_resume, 7749 .reset_prepare = qla_pci_reset_prepare, 7750 .reset_done = qla_pci_reset_done, 7751}; 7752 7753static struct pci_device_id qla2xxx_pci_tbl[] = { 7754 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7776 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7777 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7778 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7779 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7780 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7781 { 0 }, 7782}; 7783MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7784 7785static struct pci_driver qla2xxx_pci_driver = { 7786 .name = QLA2XXX_DRIVER_NAME, 7787 .driver = { 7788 .owner = THIS_MODULE, 7789 }, 7790 .id_table = qla2xxx_pci_tbl, 7791 .probe = qla2x00_probe_one, 7792 .remove = qla2x00_remove_one, 7793 .shutdown = qla2x00_shutdown, 7794 .err_handler = &qla2xxx_err_handler, 7795}; 7796 7797static const struct file_operations apidev_fops = { 7798 .owner = THIS_MODULE, 7799 .llseek = noop_llseek, 7800}; 7801 7802/** 7803 * qla2x00_module_init - Module initialization. 7804 **/ 7805static int __init 7806qla2x00_module_init(void) 7807{ 7808 int ret = 0; 7809 7810 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 7811 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7812 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7813 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7814 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7815 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 7816 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7817 BUILD_BUG_ON(sizeof(request_t) != 64); 7818 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 7819 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 7820 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 7821 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7822 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 7823 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7824 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7825 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7826 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7827 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7828 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7829 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7830 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344); 7831 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 7832 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 7833 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 7834 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 7835 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 7836 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7837 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 7838 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 7839 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 7840 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 7841 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 7842 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7843 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 7844 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7845 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 7846 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7847 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7848 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 7849 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 7850 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 7851 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 7852 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 7853 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 7854 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7855 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 7856 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 7857 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 7858 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 7859 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 7860 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 7861 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 7862 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 7863 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 7864 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 7865 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 7866 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 7867 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 7868 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 7869 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 7870 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 7871 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 7872 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 7873 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 7874 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 7875 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 7876 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 7877 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 7878 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7879 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 7880 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 7881 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 7882 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7883 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 7884 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7885 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 7886 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 7887 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 7888 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 7889 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 7890 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 7891 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 7892 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 7893 BUILD_BUG_ON(sizeof(target_id_t) != 2); 7894 7895 /* Allocate cache for SRBs. */ 7896 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7897 SLAB_HWCACHE_ALIGN, NULL); 7898 if (srb_cachep == NULL) { 7899 ql_log(ql_log_fatal, NULL, 0x0001, 7900 "Unable to allocate SRB cache...Failing load!.\n"); 7901 return -ENOMEM; 7902 } 7903 7904 /* Initialize target kmem_cache and mem_pools */ 7905 ret = qlt_init(); 7906 if (ret < 0) { 7907 goto destroy_cache; 7908 } else if (ret > 0) { 7909 /* 7910 * If initiator mode is explictly disabled by qlt_init(), 7911 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7912 * performing scsi_scan_target() during LOOP UP event. 7913 */ 7914 qla2xxx_transport_functions.disable_target_scan = 1; 7915 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7916 } 7917 7918 /* Derive version string. */ 7919 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7920 if (ql2xextended_error_logging) 7921 strcat(qla2x00_version_str, "-debug"); 7922 if (ql2xextended_error_logging == 1) 7923 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7924 7925 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7926 qla_insert_tgt_attrs(); 7927 7928 qla2xxx_transport_template = 7929 fc_attach_transport(&qla2xxx_transport_functions); 7930 if (!qla2xxx_transport_template) { 7931 ql_log(ql_log_fatal, NULL, 0x0002, 7932 "fc_attach_transport failed...Failing load!.\n"); 7933 ret = -ENODEV; 7934 goto qlt_exit; 7935 } 7936 7937 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7938 if (apidev_major < 0) { 7939 ql_log(ql_log_fatal, NULL, 0x0003, 7940 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7941 } 7942 7943 qla2xxx_transport_vport_template = 7944 fc_attach_transport(&qla2xxx_transport_vport_functions); 7945 if (!qla2xxx_transport_vport_template) { 7946 ql_log(ql_log_fatal, NULL, 0x0004, 7947 "fc_attach_transport vport failed...Failing load!.\n"); 7948 ret = -ENODEV; 7949 goto unreg_chrdev; 7950 } 7951 ql_log(ql_log_info, NULL, 0x0005, 7952 "QLogic Fibre Channel HBA Driver: %s.\n", 7953 qla2x00_version_str); 7954 ret = pci_register_driver(&qla2xxx_pci_driver); 7955 if (ret) { 7956 ql_log(ql_log_fatal, NULL, 0x0006, 7957 "pci_register_driver failed...ret=%d Failing load!.\n", 7958 ret); 7959 goto release_vport_transport; 7960 } 7961 return ret; 7962 7963release_vport_transport: 7964 fc_release_transport(qla2xxx_transport_vport_template); 7965 7966unreg_chrdev: 7967 if (apidev_major >= 0) 7968 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7969 fc_release_transport(qla2xxx_transport_template); 7970 7971qlt_exit: 7972 qlt_exit(); 7973 7974destroy_cache: 7975 kmem_cache_destroy(srb_cachep); 7976 return ret; 7977} 7978 7979/** 7980 * qla2x00_module_exit - Module cleanup. 7981 **/ 7982static void __exit 7983qla2x00_module_exit(void) 7984{ 7985 pci_unregister_driver(&qla2xxx_pci_driver); 7986 qla2x00_release_firmware(); 7987 kmem_cache_destroy(ctx_cachep); 7988 fc_release_transport(qla2xxx_transport_vport_template); 7989 if (apidev_major >= 0) 7990 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7991 fc_release_transport(qla2xxx_transport_template); 7992 qlt_exit(); 7993 kmem_cache_destroy(srb_cachep); 7994} 7995 7996module_init(qla2x00_module_init); 7997module_exit(qla2x00_module_exit); 7998 7999MODULE_AUTHOR("QLogic Corporation"); 8000MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8001MODULE_LICENSE("GPL"); 8002MODULE_FIRMWARE(FW_FILE_ISP21XX); 8003MODULE_FIRMWARE(FW_FILE_ISP22XX); 8004MODULE_FIRMWARE(FW_FILE_ISP2300); 8005MODULE_FIRMWARE(FW_FILE_ISP2322); 8006MODULE_FIRMWARE(FW_FILE_ISP24XX); 8007MODULE_FIRMWARE(FW_FILE_ISP25XX); 8008