1/* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41#include <linux/slab.h> 42#include "pm8001_sas.h" 43#include "pm8001_chips.h" 44#include "pm80xx_hwi.h" 45 46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47module_param(logging_level, ulong, 0644); 48MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51module_param(link_rate, ulong, 0644); 52MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58static struct scsi_transport_template *pm8001_stt; 59static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *); 60 61/* 62 * chip info structure to identify chip key functionality as 63 * encryption available/not, no of ports, hw specific function ref 64 */ 65static const struct pm8001_chip_info pm8001_chips[] = { 66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 77}; 78static int pm8001_id; 79 80LIST_HEAD(hba_list); 81 82struct workqueue_struct *pm8001_wq; 83 84/* 85 * The main structure which LLDD must register for scsi core. 86 */ 87static struct scsi_host_template pm8001_sht = { 88 .module = THIS_MODULE, 89 .name = DRV_NAME, 90 .queuecommand = sas_queuecommand, 91 .dma_need_drain = ata_scsi_dma_need_drain, 92 .target_alloc = sas_target_alloc, 93 .slave_configure = sas_slave_configure, 94 .scan_finished = pm8001_scan_finished, 95 .scan_start = pm8001_scan_start, 96 .change_queue_depth = sas_change_queue_depth, 97 .bios_param = sas_bios_param, 98 .can_queue = 1, 99 .this_id = -1, 100 .sg_tablesize = PM8001_MAX_DMA_SG, 101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 102 .eh_device_reset_handler = sas_eh_device_reset_handler, 103 .eh_target_reset_handler = sas_eh_target_reset_handler, 104 .slave_alloc = sas_slave_alloc, 105 .target_destroy = sas_target_destroy, 106 .ioctl = sas_ioctl, 107#ifdef CONFIG_COMPAT 108 .compat_ioctl = sas_ioctl, 109#endif 110 .shost_attrs = pm8001_host_attrs, 111 .track_queue_depth = 1, 112}; 113 114/* 115 * Sas layer call this function to execute specific task. 116 */ 117static struct sas_domain_function_template pm8001_transport_ops = { 118 .lldd_dev_found = pm8001_dev_found, 119 .lldd_dev_gone = pm8001_dev_gone, 120 121 .lldd_execute_task = pm8001_queue_command, 122 .lldd_control_phy = pm8001_phy_control, 123 124 .lldd_abort_task = pm8001_abort_task, 125 .lldd_abort_task_set = pm8001_abort_task_set, 126 .lldd_clear_aca = pm8001_clear_aca, 127 .lldd_clear_task_set = pm8001_clear_task_set, 128 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 129 .lldd_lu_reset = pm8001_lu_reset, 130 .lldd_query_task = pm8001_query_task, 131}; 132 133/** 134 * pm8001_phy_init - initiate our adapter phys 135 * @pm8001_ha: our hba structure. 136 * @phy_id: phy id. 137 */ 138static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 139{ 140 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 141 struct asd_sas_phy *sas_phy = &phy->sas_phy; 142 phy->phy_state = PHY_LINK_DISABLE; 143 phy->pm8001_ha = pm8001_ha; 144 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 145 sas_phy->class = SAS; 146 sas_phy->iproto = SAS_PROTOCOL_ALL; 147 sas_phy->tproto = 0; 148 sas_phy->type = PHY_TYPE_PHYSICAL; 149 sas_phy->role = PHY_ROLE_INITIATOR; 150 sas_phy->oob_mode = OOB_NOT_CONNECTED; 151 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 152 sas_phy->id = phy_id; 153 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 154 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 155 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 156 sas_phy->lldd_phy = phy; 157} 158 159/** 160 * pm8001_free - free hba 161 * @pm8001_ha: our hba structure. 162 */ 163static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 164{ 165 int i; 166 167 if (!pm8001_ha) 168 return; 169 170 for (i = 0; i < USI_MAX_MEMCNT; i++) { 171 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 172 dma_free_coherent(&pm8001_ha->pdev->dev, 173 (pm8001_ha->memoryMap.region[i].total_len + 174 pm8001_ha->memoryMap.region[i].alignment), 175 pm8001_ha->memoryMap.region[i].virt_ptr, 176 pm8001_ha->memoryMap.region[i].phys_addr); 177 } 178 } 179 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 180 flush_workqueue(pm8001_wq); 181 kfree(pm8001_ha->tags); 182 kfree(pm8001_ha); 183} 184 185#ifdef PM8001_USE_TASKLET 186 187/** 188 * tasklet for 64 msi-x interrupt handler 189 * @opaque: the passed general host adapter struct 190 * Note: pm8001_tasklet is common for pm8001 & pm80xx 191 */ 192static void pm8001_tasklet(unsigned long opaque) 193{ 194 struct pm8001_hba_info *pm8001_ha; 195 struct isr_param *irq_vector; 196 197 irq_vector = (struct isr_param *)opaque; 198 pm8001_ha = irq_vector->drv_inst; 199 if (unlikely(!pm8001_ha)) 200 BUG_ON(1); 201 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 202} 203#endif 204 205/** 206 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 207 * It obtains the vector number and calls the equivalent bottom 208 * half or services directly. 209 * @irq: interrupt number 210 * @opaque: the passed outbound queue/vector. Host structure is 211 * retrieved from the same. 212 */ 213static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 214{ 215 struct isr_param *irq_vector; 216 struct pm8001_hba_info *pm8001_ha; 217 irqreturn_t ret = IRQ_HANDLED; 218 irq_vector = (struct isr_param *)opaque; 219 pm8001_ha = irq_vector->drv_inst; 220 221 if (unlikely(!pm8001_ha)) 222 return IRQ_NONE; 223 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 224 return IRQ_NONE; 225#ifdef PM8001_USE_TASKLET 226 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 227#else 228 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 229#endif 230 return ret; 231} 232 233/** 234 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 235 * @irq: interrupt number 236 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 237 */ 238 239static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 240{ 241 struct pm8001_hba_info *pm8001_ha; 242 irqreturn_t ret = IRQ_HANDLED; 243 struct sas_ha_struct *sha = dev_id; 244 pm8001_ha = sha->lldd_ha; 245 if (unlikely(!pm8001_ha)) 246 return IRQ_NONE; 247 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 248 return IRQ_NONE; 249 250#ifdef PM8001_USE_TASKLET 251 tasklet_schedule(&pm8001_ha->tasklet[0]); 252#else 253 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 254#endif 255 return ret; 256} 257 258static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha); 259 260/** 261 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 262 * @pm8001_ha: our hba structure. 263 * @ent: PCI device ID structure to match on 264 */ 265static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 266 const struct pci_device_id *ent) 267{ 268 int i, count = 0, rc = 0; 269 u32 ci_offset, ib_offset, ob_offset, pi_offset; 270 struct inbound_queue_table *circularQ; 271 272 spin_lock_init(&pm8001_ha->lock); 273 spin_lock_init(&pm8001_ha->bitmap_lock); 274 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n", 275 pm8001_ha->chip->n_phy); 276 277 /* Request Interrupt */ 278 rc = pm8001_request_irq(pm8001_ha); 279 if (rc) 280 goto err_out; 281 282 count = pm8001_ha->max_q_num; 283 /* Queues are chosen based on the number of cores/msix availability */ 284 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE; 285 ci_offset = pm8001_ha->ci_offset = ib_offset + count; 286 ob_offset = pm8001_ha->ob_offset = ci_offset + count; 287 pi_offset = pm8001_ha->pi_offset = ob_offset + count; 288 pm8001_ha->max_memcnt = pi_offset + count; 289 290 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 291 pm8001_phy_init(pm8001_ha, i); 292 pm8001_ha->port[i].wide_port_phymap = 0; 293 pm8001_ha->port[i].port_attached = 0; 294 pm8001_ha->port[i].port_state = 0; 295 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 296 } 297 298 /* MPI Memory region 1 for AAP Event Log for fw */ 299 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 300 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 301 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 302 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 303 304 /* MPI Memory region 2 for IOP Event Log for fw */ 305 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 306 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 307 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 308 pm8001_ha->memoryMap.region[IOP].alignment = 32; 309 310 for (i = 0; i < count; i++) { 311 circularQ = &pm8001_ha->inbnd_q_tbl[i]; 312 spin_lock_init(&circularQ->iq_lock); 313 /* MPI Memory region 3 for consumer Index of inbound queues */ 314 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1; 315 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4; 316 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4; 317 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4; 318 319 if ((ent->driver_data) != chip_8001) { 320 /* MPI Memory region 5 inbound queues */ 321 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 322 PM8001_MPI_QUEUE; 323 pm8001_ha->memoryMap.region[ib_offset+i].element_size 324 = 128; 325 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 326 PM8001_MPI_QUEUE * 128; 327 pm8001_ha->memoryMap.region[ib_offset+i].alignment 328 = 128; 329 } else { 330 pm8001_ha->memoryMap.region[ib_offset+i].num_elements = 331 PM8001_MPI_QUEUE; 332 pm8001_ha->memoryMap.region[ib_offset+i].element_size 333 = 64; 334 pm8001_ha->memoryMap.region[ib_offset+i].total_len = 335 PM8001_MPI_QUEUE * 64; 336 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64; 337 } 338 } 339 340 for (i = 0; i < count; i++) { 341 /* MPI Memory region 4 for producer Index of outbound queues */ 342 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1; 343 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4; 344 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4; 345 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4; 346 347 if (ent->driver_data != chip_8001) { 348 /* MPI Memory region 6 Outbound queues */ 349 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 350 PM8001_MPI_QUEUE; 351 pm8001_ha->memoryMap.region[ob_offset+i].element_size 352 = 128; 353 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 354 PM8001_MPI_QUEUE * 128; 355 pm8001_ha->memoryMap.region[ob_offset+i].alignment 356 = 128; 357 } else { 358 /* MPI Memory region 6 Outbound queues */ 359 pm8001_ha->memoryMap.region[ob_offset+i].num_elements = 360 PM8001_MPI_QUEUE; 361 pm8001_ha->memoryMap.region[ob_offset+i].element_size 362 = 64; 363 pm8001_ha->memoryMap.region[ob_offset+i].total_len = 364 PM8001_MPI_QUEUE * 64; 365 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64; 366 } 367 368 } 369 /* Memory region write DMA*/ 370 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 371 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 372 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 373 374 /* Memory region for fw flash */ 375 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 376 377 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 378 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 379 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 380 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 381 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 382 if (pm8001_mem_alloc(pm8001_ha->pdev, 383 &pm8001_ha->memoryMap.region[i].virt_ptr, 384 &pm8001_ha->memoryMap.region[i].phys_addr, 385 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 386 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 387 pm8001_ha->memoryMap.region[i].total_len, 388 pm8001_ha->memoryMap.region[i].alignment) != 0) { 389 pm8001_dbg(pm8001_ha, FAIL, 390 "Mem%d alloc failed\n", 391 i); 392 goto err_out; 393 } 394 } 395 396 /* Memory region for devices*/ 397 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES 398 * sizeof(struct pm8001_device), GFP_KERNEL); 399 if (!pm8001_ha->devices) { 400 rc = -ENOMEM; 401 goto err_out_nodev; 402 } 403 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 404 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 405 pm8001_ha->devices[i].id = i; 406 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 407 atomic_set(&pm8001_ha->devices[i].running_req, 0); 408 } 409 pm8001_ha->flags = PM8001F_INIT_TIME; 410 /* Initialize tags */ 411 pm8001_tag_init(pm8001_ha); 412 return 0; 413 414err_out_nodev: 415 for (i = 0; i < pm8001_ha->max_memcnt; i++) { 416 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 417 pci_free_consistent(pm8001_ha->pdev, 418 (pm8001_ha->memoryMap.region[i].total_len + 419 pm8001_ha->memoryMap.region[i].alignment), 420 pm8001_ha->memoryMap.region[i].virt_ptr, 421 pm8001_ha->memoryMap.region[i].phys_addr); 422 } 423 } 424err_out: 425 return 1; 426} 427 428/** 429 * pm8001_ioremap - remap the pci high physical address to kernal virtual 430 * address so that we can access them. 431 * @pm8001_ha:our hba structure. 432 */ 433static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 434{ 435 u32 bar; 436 u32 logicalBar = 0; 437 struct pci_dev *pdev; 438 439 pdev = pm8001_ha->pdev; 440 /* map pci mem (PMC pci base 0-3)*/ 441 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 442 /* 443 ** logical BARs for SPC: 444 ** bar 0 and 1 - logical BAR0 445 ** bar 2 and 3 - logical BAR1 446 ** bar4 - logical BAR2 447 ** bar5 - logical BAR3 448 ** Skip the appropriate assignments: 449 */ 450 if ((bar == 1) || (bar == 3)) 451 continue; 452 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 453 pm8001_ha->io_mem[logicalBar].membase = 454 pci_resource_start(pdev, bar); 455 pm8001_ha->io_mem[logicalBar].memsize = 456 pci_resource_len(pdev, bar); 457 pm8001_ha->io_mem[logicalBar].memvirtaddr = 458 ioremap(pm8001_ha->io_mem[logicalBar].membase, 459 pm8001_ha->io_mem[logicalBar].memsize); 460 pm8001_dbg(pm8001_ha, INIT, 461 "PCI: bar %d, logicalBar %d\n", 462 bar, logicalBar); 463 pm8001_dbg(pm8001_ha, INIT, 464 "base addr %llx virt_addr=%llx len=%d\n", 465 (u64)pm8001_ha->io_mem[logicalBar].membase, 466 (u64)(unsigned long) 467 pm8001_ha->io_mem[logicalBar].memvirtaddr, 468 pm8001_ha->io_mem[logicalBar].memsize); 469 } else { 470 pm8001_ha->io_mem[logicalBar].membase = 0; 471 pm8001_ha->io_mem[logicalBar].memsize = 0; 472 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 473 } 474 logicalBar++; 475 } 476 return 0; 477} 478 479/** 480 * pm8001_pci_alloc - initialize our ha card structure 481 * @pdev: pci device. 482 * @ent: ent 483 * @shost: scsi host struct which has been initialized before. 484 */ 485static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 486 const struct pci_device_id *ent, 487 struct Scsi_Host *shost) 488 489{ 490 struct pm8001_hba_info *pm8001_ha; 491 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 492 int j; 493 494 pm8001_ha = sha->lldd_ha; 495 if (!pm8001_ha) 496 return NULL; 497 498 pm8001_ha->pdev = pdev; 499 pm8001_ha->dev = &pdev->dev; 500 pm8001_ha->chip_id = ent->driver_data; 501 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 502 pm8001_ha->irq = pdev->irq; 503 pm8001_ha->sas = sha; 504 pm8001_ha->shost = shost; 505 pm8001_ha->id = pm8001_id++; 506 pm8001_ha->logging_level = logging_level; 507 pm8001_ha->non_fatal_count = 0; 508 if (link_rate >= 1 && link_rate <= 15) 509 pm8001_ha->link_rate = (link_rate << 8); 510 else { 511 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 512 LINKRATE_60 | LINKRATE_120; 513 pm8001_dbg(pm8001_ha, FAIL, 514 "Setting link rate to default value\n"); 515 } 516 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 517 /* IOMB size is 128 for 8088/89 controllers */ 518 if (pm8001_ha->chip_id != chip_8001) 519 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 520 else 521 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 522 523#ifdef PM8001_USE_TASKLET 524 /* Tasklet for non msi-x interrupt handler */ 525 if ((!pdev->msix_cap || !pci_msi_enabled()) 526 || (pm8001_ha->chip_id == chip_8001)) 527 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 528 (unsigned long)&(pm8001_ha->irq_vector[0])); 529 else 530 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 531 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 532 (unsigned long)&(pm8001_ha->irq_vector[j])); 533#endif 534 pm8001_ioremap(pm8001_ha); 535 if (!pm8001_alloc(pm8001_ha, ent)) 536 return pm8001_ha; 537 pm8001_free(pm8001_ha); 538 return NULL; 539} 540 541/** 542 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 543 * @pdev: pci device. 544 */ 545static int pci_go_44(struct pci_dev *pdev) 546{ 547 int rc; 548 549 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 550 if (rc) { 551 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 552 if (rc) 553 dev_printk(KERN_ERR, &pdev->dev, 554 "32-bit DMA enable failed\n"); 555 } 556 return rc; 557} 558 559/** 560 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 561 * @shost: scsi host which has been allocated outside. 562 * @chip_info: our ha struct. 563 */ 564static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 565 const struct pm8001_chip_info *chip_info) 566{ 567 int phy_nr, port_nr; 568 struct asd_sas_phy **arr_phy; 569 struct asd_sas_port **arr_port; 570 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 571 572 phy_nr = chip_info->n_phy; 573 port_nr = phy_nr; 574 memset(sha, 0x00, sizeof(*sha)); 575 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 576 if (!arr_phy) 577 goto exit; 578 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 579 if (!arr_port) 580 goto exit_free2; 581 582 sha->sas_phy = arr_phy; 583 sha->sas_port = arr_port; 584 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 585 if (!sha->lldd_ha) 586 goto exit_free1; 587 588 shost->transportt = pm8001_stt; 589 shost->max_id = PM8001_MAX_DEVICES; 590 shost->max_lun = 8; 591 shost->max_channel = 0; 592 shost->unique_id = pm8001_id; 593 shost->max_cmd_len = 16; 594 shost->can_queue = PM8001_CAN_QUEUE; 595 shost->cmd_per_lun = 32; 596 return 0; 597exit_free1: 598 kfree(arr_port); 599exit_free2: 600 kfree(arr_phy); 601exit: 602 return -1; 603} 604 605/** 606 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 607 * @shost: scsi host which has been allocated outside 608 * @chip_info: our ha struct. 609 */ 610static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 611 const struct pm8001_chip_info *chip_info) 612{ 613 int i = 0; 614 struct pm8001_hba_info *pm8001_ha; 615 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 616 617 pm8001_ha = sha->lldd_ha; 618 for (i = 0; i < chip_info->n_phy; i++) { 619 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 620 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 621 sha->sas_phy[i]->sas_addr = 622 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 623 } 624 sha->sas_ha_name = DRV_NAME; 625 sha->dev = pm8001_ha->dev; 626 sha->strict_wide_ports = 1; 627 sha->lldd_module = THIS_MODULE; 628 sha->sas_addr = &pm8001_ha->sas_addr[0]; 629 sha->num_phys = chip_info->n_phy; 630 sha->core.shost = shost; 631} 632 633/** 634 * pm8001_init_sas_add - initialize sas address 635 * @pm8001_ha: our ha struct. 636 * 637 * Currently we just set the fixed SAS address to our HBA,for manufacture, 638 * it should read from the EEPROM 639 */ 640static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 641{ 642 u8 i, j; 643 u8 sas_add[8]; 644#ifdef PM8001_READ_VPD 645 /* For new SPC controllers WWN is stored in flash vpd 646 * For SPC/SPCve controllers WWN is stored in EEPROM 647 * For Older SPC WWN is stored in NVMD 648 */ 649 DECLARE_COMPLETION_ONSTACK(completion); 650 struct pm8001_ioctl_payload payload; 651 u16 deviceid; 652 int rc; 653 654 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 655 pm8001_ha->nvmd_completion = &completion; 656 657 if (pm8001_ha->chip_id == chip_8001) { 658 if (deviceid == 0x8081 || deviceid == 0x0042) { 659 payload.minor_function = 4; 660 payload.rd_length = 4096; 661 } else { 662 payload.minor_function = 0; 663 payload.rd_length = 128; 664 } 665 } else if ((pm8001_ha->chip_id == chip_8070 || 666 pm8001_ha->chip_id == chip_8072) && 667 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 668 payload.minor_function = 4; 669 payload.rd_length = 4096; 670 } else { 671 payload.minor_function = 1; 672 payload.rd_length = 4096; 673 } 674 payload.offset = 0; 675 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL); 676 if (!payload.func_specific) { 677 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n"); 678 return; 679 } 680 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 681 if (rc) { 682 kfree(payload.func_specific); 683 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 684 return; 685 } 686 wait_for_completion(&completion); 687 688 for (i = 0, j = 0; i <= 7; i++, j++) { 689 if (pm8001_ha->chip_id == chip_8001) { 690 if (deviceid == 0x8081) 691 pm8001_ha->sas_addr[j] = 692 payload.func_specific[0x704 + i]; 693 else if (deviceid == 0x0042) 694 pm8001_ha->sas_addr[j] = 695 payload.func_specific[0x010 + i]; 696 } else if ((pm8001_ha->chip_id == chip_8070 || 697 pm8001_ha->chip_id == chip_8072) && 698 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 699 pm8001_ha->sas_addr[j] = 700 payload.func_specific[0x010 + i]; 701 } else 702 pm8001_ha->sas_addr[j] = 703 payload.func_specific[0x804 + i]; 704 } 705 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 706 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 707 if (i && ((i % 4) == 0)) 708 sas_add[7] = sas_add[7] + 4; 709 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 710 sas_add, SAS_ADDR_SIZE); 711 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i, 712 pm8001_ha->phy[i].dev_sas_addr); 713 } 714 kfree(payload.func_specific); 715#else 716 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 717 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 718 pm8001_ha->phy[i].dev_sas_addr = 719 cpu_to_be64((u64) 720 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 721 } 722 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 723 SAS_ADDR_SIZE); 724#endif 725} 726 727/* 728 * pm8001_get_phy_settings_info : Read phy setting values. 729 * @pm8001_ha : our hba. 730 */ 731static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 732{ 733 734#ifdef PM8001_READ_VPD 735 /*OPTION ROM FLASH read for the SPC cards */ 736 DECLARE_COMPLETION_ONSTACK(completion); 737 struct pm8001_ioctl_payload payload; 738 int rc; 739 740 pm8001_ha->nvmd_completion = &completion; 741 /* SAS ADDRESS read from flash / EEPROM */ 742 payload.minor_function = 6; 743 payload.offset = 0; 744 payload.rd_length = 4096; 745 payload.func_specific = kzalloc(4096, GFP_KERNEL); 746 if (!payload.func_specific) 747 return -ENOMEM; 748 /* Read phy setting values from flash */ 749 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 750 if (rc) { 751 kfree(payload.func_specific); 752 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n"); 753 return -ENOMEM; 754 } 755 wait_for_completion(&completion); 756 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 757 kfree(payload.func_specific); 758#endif 759 return 0; 760} 761 762struct pm8001_mpi3_phy_pg_trx_config { 763 u32 LaneLosCfg; 764 u32 LanePgaCfg1; 765 u32 LanePisoCfg1; 766 u32 LanePisoCfg2; 767 u32 LanePisoCfg3; 768 u32 LanePisoCfg4; 769 u32 LanePisoCfg5; 770 u32 LanePisoCfg6; 771 u32 LaneBctCtrl; 772}; 773 774/** 775 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 776 * @pm8001_ha : our adapter 777 * @phycfg : PHY config page to populate 778 */ 779static 780void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 781 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 782{ 783 phycfg->LaneLosCfg = 0x00000132; 784 phycfg->LanePgaCfg1 = 0x00203949; 785 phycfg->LanePisoCfg1 = 0x000000FF; 786 phycfg->LanePisoCfg2 = 0xFF000001; 787 phycfg->LanePisoCfg3 = 0xE7011300; 788 phycfg->LanePisoCfg4 = 0x631C40C0; 789 phycfg->LanePisoCfg5 = 0xF8102036; 790 phycfg->LanePisoCfg6 = 0xF74A1000; 791 phycfg->LaneBctCtrl = 0x00FB33F8; 792} 793 794/** 795 * pm8001_get_external_phy_settings : Retrieves the external PHY settings 796 * @pm8001_ha : our adapter 797 * @phycfg : PHY config page to populate 798 */ 799static 800void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 801 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 802{ 803 phycfg->LaneLosCfg = 0x00000132; 804 phycfg->LanePgaCfg1 = 0x00203949; 805 phycfg->LanePisoCfg1 = 0x000000FF; 806 phycfg->LanePisoCfg2 = 0xFF000001; 807 phycfg->LanePisoCfg3 = 0xE7011300; 808 phycfg->LanePisoCfg4 = 0x63349140; 809 phycfg->LanePisoCfg5 = 0xF8102036; 810 phycfg->LanePisoCfg6 = 0xF80D9300; 811 phycfg->LaneBctCtrl = 0x00FB33F8; 812} 813 814/** 815 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 816 * @pm8001_ha : our adapter 817 * @phymask : The PHY mask 818 */ 819static 820void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 821{ 822 switch (pm8001_ha->pdev->subsystem_device) { 823 case 0x0070: /* H1280 - 8 external 0 internal */ 824 case 0x0072: /* H12F0 - 16 external 0 internal */ 825 *phymask = 0x0000; 826 break; 827 828 case 0x0071: /* H1208 - 0 external 8 internal */ 829 case 0x0073: /* H120F - 0 external 16 internal */ 830 *phymask = 0xFFFF; 831 break; 832 833 case 0x0080: /* H1244 - 4 external 4 internal */ 834 *phymask = 0x00F0; 835 break; 836 837 case 0x0081: /* H1248 - 4 external 8 internal */ 838 *phymask = 0x0FF0; 839 break; 840 841 case 0x0082: /* H1288 - 8 external 8 internal */ 842 *phymask = 0xFF00; 843 break; 844 845 default: 846 pm8001_dbg(pm8001_ha, INIT, 847 "Unknown subsystem device=0x%.04x\n", 848 pm8001_ha->pdev->subsystem_device); 849 } 850} 851 852/** 853 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings 854 * @pm8001_ha : our adapter 855 */ 856static 857int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 858{ 859 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 860 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 861 int phymask = 0; 862 int i = 0; 863 864 memset(&phycfg_int, 0, sizeof(phycfg_int)); 865 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 866 867 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 868 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 869 pm8001_get_phy_mask(pm8001_ha, &phymask); 870 871 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 872 if (phymask & (1 << i)) {/* Internal PHY */ 873 pm8001_set_phy_profile_single(pm8001_ha, i, 874 sizeof(phycfg_int) / sizeof(u32), 875 (u32 *)&phycfg_int); 876 877 } else { /* External PHY */ 878 pm8001_set_phy_profile_single(pm8001_ha, i, 879 sizeof(phycfg_ext) / sizeof(u32), 880 (u32 *)&phycfg_ext); 881 } 882 } 883 884 return 0; 885} 886 887/** 888 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 889 * @pm8001_ha : our hba. 890 */ 891static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 892{ 893 switch (pm8001_ha->pdev->subsystem_vendor) { 894 case PCI_VENDOR_ID_ATTO: 895 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 896 return 0; 897 else 898 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 899 900 case PCI_VENDOR_ID_ADAPTEC2: 901 case 0: 902 return 0; 903 904 default: 905 return pm8001_get_phy_settings_info(pm8001_ha); 906 } 907} 908 909#ifdef PM8001_USE_MSIX 910/** 911 * pm8001_setup_msix - enable MSI-X interrupt 912 * @pm8001_ha: our ha struct. 913 */ 914static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 915{ 916 u32 number_of_intr; 917 int rc, cpu_online_count; 918 unsigned int allocated_irq_vectors; 919 920 /* SPCv controllers supports 64 msi-x */ 921 if (pm8001_ha->chip_id == chip_8001) { 922 number_of_intr = 1; 923 } else { 924 number_of_intr = PM8001_MAX_MSIX_VEC; 925 } 926 927 cpu_online_count = num_online_cpus(); 928 number_of_intr = min_t(int, cpu_online_count, number_of_intr); 929 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 930 number_of_intr, PCI_IRQ_MSIX); 931 allocated_irq_vectors = rc; 932 if (rc < 0) 933 return rc; 934 935 /* Assigns the number of interrupts */ 936 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr); 937 pm8001_ha->number_of_intr = number_of_intr; 938 939 /* Maximum queue number updating in HBA structure */ 940 pm8001_ha->max_q_num = number_of_intr; 941 942 pm8001_dbg(pm8001_ha, INIT, 943 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 944 rc, pm8001_ha->number_of_intr); 945 return 0; 946} 947 948static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha) 949{ 950 u32 i = 0, j = 0; 951 int flag = 0, rc = 0; 952 953 if (pm8001_ha->chip_id != chip_8001) 954 flag &= ~IRQF_SHARED; 955 956 pm8001_dbg(pm8001_ha, INIT, 957 "pci_enable_msix request number of intr %d\n", 958 pm8001_ha->number_of_intr); 959 960 for (i = 0; i < pm8001_ha->number_of_intr; i++) { 961 snprintf(pm8001_ha->intr_drvname[i], 962 sizeof(pm8001_ha->intr_drvname[0]), 963 "%s-%d", pm8001_ha->name, i); 964 pm8001_ha->irq_vector[i].irq_id = i; 965 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 966 967 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 968 pm8001_interrupt_handler_msix, flag, 969 pm8001_ha->intr_drvname[i], 970 &(pm8001_ha->irq_vector[i])); 971 if (rc) { 972 for (j = 0; j < i; j++) { 973 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 974 &(pm8001_ha->irq_vector[i])); 975 } 976 pci_free_irq_vectors(pm8001_ha->pdev); 977 break; 978 } 979 } 980 981 return rc; 982} 983#endif 984 985/** 986 * pm8001_request_irq - register interrupt 987 * @pm8001_ha: our ha struct. 988 */ 989static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 990{ 991 struct pci_dev *pdev = pm8001_ha->pdev; 992#ifdef PM8001_USE_MSIX 993 int rc; 994 995 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) { 996 rc = pm8001_setup_msix(pm8001_ha); 997 if (rc) { 998 pm8001_dbg(pm8001_ha, FAIL, 999 "pm8001_setup_irq failed [ret: %d]\n", rc); 1000 return rc; 1001 } 1002 1003 if (pdev->msix_cap && pci_msi_enabled()) 1004 return pm8001_request_msix(pm8001_ha); 1005 } 1006 1007 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n"); 1008#endif 1009 1010 /* initialize the INT-X interrupt */ 1011 pm8001_ha->irq_vector[0].irq_id = 0; 1012 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 1013 1014 return request_irq(pdev->irq, pm8001_interrupt_handler_intx, 1015 IRQF_SHARED, pm8001_ha->name, 1016 SHOST_TO_SAS_HA(pm8001_ha->shost)); 1017} 1018 1019/** 1020 * pm8001_pci_probe - probe supported device 1021 * @pdev: pci device which kernel has been prepared for. 1022 * @ent: pci device id 1023 * 1024 * This function is the main initialization function, when register a new 1025 * pci driver it is invoked, all struct an hardware initilization should be done 1026 * here, also, register interrupt 1027 */ 1028static int pm8001_pci_probe(struct pci_dev *pdev, 1029 const struct pci_device_id *ent) 1030{ 1031 unsigned int rc; 1032 u32 pci_reg; 1033 u8 i = 0; 1034 struct pm8001_hba_info *pm8001_ha; 1035 struct Scsi_Host *shost = NULL; 1036 const struct pm8001_chip_info *chip; 1037 struct sas_ha_struct *sha; 1038 1039 dev_printk(KERN_INFO, &pdev->dev, 1040 "pm80xx: driver version %s\n", DRV_VERSION); 1041 rc = pci_enable_device(pdev); 1042 if (rc) 1043 goto err_out_enable; 1044 pci_set_master(pdev); 1045 /* 1046 * Enable pci slot busmaster by setting pci command register. 1047 * This is required by FW for Cyclone card. 1048 */ 1049 1050 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1051 pci_reg |= 0x157; 1052 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1053 rc = pci_request_regions(pdev, DRV_NAME); 1054 if (rc) 1055 goto err_out_disable; 1056 rc = pci_go_44(pdev); 1057 if (rc) 1058 goto err_out_regions; 1059 1060 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1061 if (!shost) { 1062 rc = -ENOMEM; 1063 goto err_out_regions; 1064 } 1065 chip = &pm8001_chips[ent->driver_data]; 1066 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1067 if (!sha) { 1068 rc = -ENOMEM; 1069 goto err_out_free_host; 1070 } 1071 SHOST_TO_SAS_HA(shost) = sha; 1072 1073 rc = pm8001_prep_sas_ha_init(shost, chip); 1074 if (rc) { 1075 rc = -ENOMEM; 1076 goto err_out_free; 1077 } 1078 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1079 /* ent->driver variable is used to differentiate between controllers */ 1080 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1081 if (!pm8001_ha) { 1082 rc = -ENOMEM; 1083 goto err_out_free; 1084 } 1085 1086 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1087 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1088 if (rc) { 1089 pm8001_dbg(pm8001_ha, FAIL, 1090 "chip_init failed [ret: %d]\n", rc); 1091 goto err_out_ha_free; 1092 } 1093 1094 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev); 1095 if (rc) 1096 goto err_out_enable; 1097 1098 rc = scsi_add_host(shost, &pdev->dev); 1099 if (rc) 1100 goto err_out_ha_free; 1101 1102 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1103 if (pm8001_ha->chip_id != chip_8001) { 1104 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1105 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1106 /* setup thermal configuration. */ 1107 pm80xx_set_thermal_config(pm8001_ha); 1108 } 1109 1110 pm8001_init_sas_add(pm8001_ha); 1111 /* phy setting support for motherboard controller */ 1112 rc = pm8001_configure_phy_settings(pm8001_ha); 1113 if (rc) 1114 goto err_out_shost; 1115 1116 pm8001_post_sas_ha_init(shost, chip); 1117 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1118 if (rc) { 1119 pm8001_dbg(pm8001_ha, FAIL, 1120 "sas_register_ha failed [ret: %d]\n", rc); 1121 goto err_out_shost; 1122 } 1123 list_add_tail(&pm8001_ha->list, &hba_list); 1124 pm8001_ha->flags = PM8001F_RUN_TIME; 1125 scsi_scan_host(pm8001_ha->shost); 1126 return 0; 1127 1128err_out_shost: 1129 scsi_remove_host(pm8001_ha->shost); 1130err_out_ha_free: 1131 pm8001_free(pm8001_ha); 1132err_out_free: 1133 kfree(sha); 1134err_out_free_host: 1135 scsi_host_put(shost); 1136err_out_regions: 1137 pci_release_regions(pdev); 1138err_out_disable: 1139 pci_disable_device(pdev); 1140err_out_enable: 1141 return rc; 1142} 1143 1144/* 1145 * pm8001_init_ccb_tag - allocate memory to CCB and tag. 1146 * @pm8001_ha: our hba card information. 1147 * @shost: scsi host which has been allocated outside. 1148 */ 1149static int 1150pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost, 1151 struct pci_dev *pdev) 1152{ 1153 int i = 0; 1154 u32 max_out_io, ccb_count; 1155 u32 can_queue; 1156 1157 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io; 1158 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io); 1159 1160 /* Update to the scsi host*/ 1161 can_queue = ccb_count - PM8001_RESERVE_SLOT; 1162 shost->can_queue = can_queue; 1163 1164 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL); 1165 if (!pm8001_ha->tags) 1166 goto err_out; 1167 1168 /* Memory region for ccb_info*/ 1169 pm8001_ha->ccb_info = (struct pm8001_ccb_info *) 1170 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL); 1171 if (!pm8001_ha->ccb_info) { 1172 pm8001_dbg(pm8001_ha, FAIL, 1173 "Unable to allocate memory for ccb\n"); 1174 goto err_out_noccb; 1175 } 1176 for (i = 0; i < ccb_count; i++) { 1177 pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev, 1178 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG, 1179 &pm8001_ha->ccb_info[i].ccb_dma_handle); 1180 if (!pm8001_ha->ccb_info[i].buf_prd) { 1181 pm8001_dbg(pm8001_ha, FAIL, 1182 "pm80xx: ccb prd memory allocation error\n"); 1183 goto err_out; 1184 } 1185 pm8001_ha->ccb_info[i].task = NULL; 1186 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 1187 pm8001_ha->ccb_info[i].device = NULL; 1188 ++pm8001_ha->tags_num; 1189 } 1190 return 0; 1191 1192err_out_noccb: 1193 kfree(pm8001_ha->devices); 1194err_out: 1195 return -ENOMEM; 1196} 1197 1198static void pm8001_pci_remove(struct pci_dev *pdev) 1199{ 1200 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1201 struct pm8001_hba_info *pm8001_ha; 1202 int i, j; 1203 pm8001_ha = sha->lldd_ha; 1204 sas_unregister_ha(sha); 1205 sas_remove_host(pm8001_ha->shost); 1206 list_del(&pm8001_ha->list); 1207 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1208 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1209 1210#ifdef PM8001_USE_MSIX 1211 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1212 synchronize_irq(pci_irq_vector(pdev, i)); 1213 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1214 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1215 pci_free_irq_vectors(pdev); 1216#else 1217 free_irq(pm8001_ha->irq, sha); 1218#endif 1219#ifdef PM8001_USE_TASKLET 1220 /* For non-msix and msix interrupts */ 1221 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1222 (pm8001_ha->chip_id == chip_8001)) 1223 tasklet_kill(&pm8001_ha->tasklet[0]); 1224 else 1225 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1226 tasklet_kill(&pm8001_ha->tasklet[j]); 1227#endif 1228 scsi_host_put(pm8001_ha->shost); 1229 pm8001_free(pm8001_ha); 1230 kfree(sha->sas_phy); 1231 kfree(sha->sas_port); 1232 kfree(sha); 1233 pci_release_regions(pdev); 1234 pci_disable_device(pdev); 1235} 1236 1237/** 1238 * pm8001_pci_suspend - power management suspend main entry point 1239 * @pdev: PCI device struct 1240 * @state: PM state change to (usually PCI_D3) 1241 * 1242 * Returns 0 success, anything else error. 1243 */ 1244static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1245{ 1246 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1247 struct pm8001_hba_info *pm8001_ha; 1248 int i, j; 1249 u32 device_state; 1250 pm8001_ha = sha->lldd_ha; 1251 sas_suspend_ha(sha); 1252 flush_workqueue(pm8001_wq); 1253 scsi_block_requests(pm8001_ha->shost); 1254 if (!pdev->pm_cap) { 1255 dev_err(&pdev->dev, " PCI PM not supported\n"); 1256 return -ENODEV; 1257 } 1258 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1259 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1260#ifdef PM8001_USE_MSIX 1261 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1262 synchronize_irq(pci_irq_vector(pdev, i)); 1263 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1264 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1265 pci_free_irq_vectors(pdev); 1266#else 1267 free_irq(pm8001_ha->irq, sha); 1268#endif 1269#ifdef PM8001_USE_TASKLET 1270 /* For non-msix and msix interrupts */ 1271 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1272 (pm8001_ha->chip_id == chip_8001)) 1273 tasklet_kill(&pm8001_ha->tasklet[0]); 1274 else 1275 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1276 tasklet_kill(&pm8001_ha->tasklet[j]); 1277#endif 1278 device_state = pci_choose_state(pdev, state); 1279 pm8001_printk("pdev=0x%p, slot=%s, entering " 1280 "operating state [D%d]\n", pdev, 1281 pm8001_ha->name, device_state); 1282 pci_save_state(pdev); 1283 pci_disable_device(pdev); 1284 pci_set_power_state(pdev, device_state); 1285 return 0; 1286} 1287 1288/** 1289 * pm8001_pci_resume - power management resume main entry point 1290 * @pdev: PCI device struct 1291 * 1292 * Returns 0 success, anything else error. 1293 */ 1294static int pm8001_pci_resume(struct pci_dev *pdev) 1295{ 1296 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1297 struct pm8001_hba_info *pm8001_ha; 1298 int rc; 1299 u8 i = 0, j; 1300 u32 device_state; 1301 DECLARE_COMPLETION_ONSTACK(completion); 1302 pm8001_ha = sha->lldd_ha; 1303 device_state = pdev->current_state; 1304 1305 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1306 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1307 1308 pci_set_power_state(pdev, PCI_D0); 1309 pci_enable_wake(pdev, PCI_D0, 0); 1310 pci_restore_state(pdev); 1311 rc = pci_enable_device(pdev); 1312 if (rc) { 1313 pm8001_printk("slot=%s Enable device failed during resume\n", 1314 pm8001_ha->name); 1315 goto err_out_enable; 1316 } 1317 1318 pci_set_master(pdev); 1319 rc = pci_go_44(pdev); 1320 if (rc) 1321 goto err_out_disable; 1322 sas_prep_resume_ha(sha); 1323 /* chip soft rst only for spc */ 1324 if (pm8001_ha->chip_id == chip_8001) { 1325 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1326 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n"); 1327 } 1328 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1329 if (rc) 1330 goto err_out_disable; 1331 1332 /* disable all the interrupt bits */ 1333 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1334 1335 rc = pm8001_request_irq(pm8001_ha); 1336 if (rc) 1337 goto err_out_disable; 1338#ifdef PM8001_USE_TASKLET 1339 /* Tasklet for non msi-x interrupt handler */ 1340 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1341 (pm8001_ha->chip_id == chip_8001)) 1342 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1343 (unsigned long)&(pm8001_ha->irq_vector[0])); 1344 else 1345 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1346 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1347 (unsigned long)&(pm8001_ha->irq_vector[j])); 1348#endif 1349 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1350 if (pm8001_ha->chip_id != chip_8001) { 1351 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1352 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1353 } 1354 1355 /* Chip documentation for the 8070 and 8072 SPCv */ 1356 /* states that a 500ms minimum delay is required */ 1357 /* before issuing commands. Otherwise, the firmware */ 1358 /* will enter an unrecoverable state. */ 1359 1360 if (pm8001_ha->chip_id == chip_8070 || 1361 pm8001_ha->chip_id == chip_8072) { 1362 mdelay(500); 1363 } 1364 1365 /* Spin up the PHYs */ 1366 1367 pm8001_ha->flags = PM8001F_RUN_TIME; 1368 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1369 pm8001_ha->phy[i].enable_completion = &completion; 1370 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1371 wait_for_completion(&completion); 1372 } 1373 sas_resume_ha(sha); 1374 return 0; 1375 1376err_out_disable: 1377 scsi_remove_host(pm8001_ha->shost); 1378 pci_disable_device(pdev); 1379err_out_enable: 1380 return rc; 1381} 1382 1383/* update of pci device, vendor id and driver data with 1384 * unique value for each of the controller 1385 */ 1386static struct pci_device_id pm8001_pci_table[] = { 1387 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1388 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1389 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1390 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1391 /* Support for SPC/SPCv/SPCve controllers */ 1392 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1393 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1394 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1395 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1396 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1397 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1398 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1399 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1400 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1401 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1402 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1403 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1404 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1405 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1406 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1407 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1408 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1409 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1410 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1411 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1412 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1413 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1414 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1415 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1416 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1417 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1418 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1419 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1420 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1421 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1422 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1423 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1424 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1425 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1426 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1427 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1428 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1429 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1430 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1431 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1432 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1433 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1434 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1435 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1436 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1438 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1440 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1442 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1444 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1445 { PCI_VENDOR_ID_ATTO, 0x8070, 1446 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1447 { PCI_VENDOR_ID_ATTO, 0x8070, 1448 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1449 { PCI_VENDOR_ID_ATTO, 0x8072, 1450 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1451 { PCI_VENDOR_ID_ATTO, 0x8072, 1452 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1453 { PCI_VENDOR_ID_ATTO, 0x8070, 1454 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1455 { PCI_VENDOR_ID_ATTO, 0x8072, 1456 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1457 { PCI_VENDOR_ID_ATTO, 0x8072, 1458 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1459 {} /* terminate list */ 1460}; 1461 1462static struct pci_driver pm8001_pci_driver = { 1463 .name = DRV_NAME, 1464 .id_table = pm8001_pci_table, 1465 .probe = pm8001_pci_probe, 1466 .remove = pm8001_pci_remove, 1467 .suspend = pm8001_pci_suspend, 1468 .resume = pm8001_pci_resume, 1469}; 1470 1471/** 1472 * pm8001_init - initialize scsi transport template 1473 */ 1474static int __init pm8001_init(void) 1475{ 1476 int rc = -ENOMEM; 1477 1478 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1479 if (!pm8001_wq) 1480 goto err; 1481 1482 pm8001_id = 0; 1483 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1484 if (!pm8001_stt) 1485 goto err_wq; 1486 rc = pci_register_driver(&pm8001_pci_driver); 1487 if (rc) 1488 goto err_tp; 1489 return 0; 1490 1491err_tp: 1492 sas_release_transport(pm8001_stt); 1493err_wq: 1494 destroy_workqueue(pm8001_wq); 1495err: 1496 return rc; 1497} 1498 1499static void __exit pm8001_exit(void) 1500{ 1501 pci_unregister_driver(&pm8001_pci_driver); 1502 sas_release_transport(pm8001_stt); 1503 destroy_workqueue(pm8001_wq); 1504} 1505 1506module_init(pm8001_init); 1507module_exit(pm8001_exit); 1508 1509MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1510MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1511MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1512MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1513MODULE_DESCRIPTION( 1514 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1515 "SAS/SATA controller driver"); 1516MODULE_VERSION(DRV_VERSION); 1517MODULE_LICENSE("GPL"); 1518MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1519 1520