1/* bnx2fc_hwi.c: QLogic Linux FCoE offload driver. 2 * This file contains the code that low level functions that interact 3 * with 57712 FCoE firmware. 4 * 5 * Copyright (c) 2008-2013 Broadcom Corporation 6 * Copyright (c) 2014-2016 QLogic Corporation 7 * Copyright (c) 2016-2017 Cavium Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation. 12 * 13 * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com) 14 */ 15 16#include "bnx2fc.h" 17 18DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); 19 20static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba, 21 struct fcoe_kcqe *new_cqe_kcqe); 22static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba, 23 struct fcoe_kcqe *ofld_kcqe); 24static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba, 25 struct fcoe_kcqe *ofld_kcqe); 26static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code); 27static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba, 28 struct fcoe_kcqe *destroy_kcqe); 29 30int bnx2fc_send_stat_req(struct bnx2fc_hba *hba) 31{ 32 struct fcoe_kwqe_stat stat_req; 33 struct kwqe *kwqe_arr[2]; 34 int num_kwqes = 1; 35 int rc = 0; 36 37 memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat)); 38 stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT; 39 stat_req.hdr.flags = 40 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 41 42 stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma; 43 stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32); 44 45 kwqe_arr[0] = (struct kwqe *) &stat_req; 46 47 if (hba->cnic && hba->cnic->submit_kwqes) 48 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 49 50 return rc; 51} 52 53/** 54 * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w 55 * 56 * @hba: adapter structure pointer 57 * 58 * Send down FCoE firmware init KWQEs which initiates the initial handshake 59 * with the f/w. 60 * 61 */ 62int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba) 63{ 64 struct fcoe_kwqe_init1 fcoe_init1; 65 struct fcoe_kwqe_init2 fcoe_init2; 66 struct fcoe_kwqe_init3 fcoe_init3; 67 struct kwqe *kwqe_arr[3]; 68 int num_kwqes = 3; 69 int rc = 0; 70 71 if (!hba->cnic) { 72 printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n"); 73 return -ENODEV; 74 } 75 76 /* fill init1 KWQE */ 77 memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1)); 78 fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1; 79 fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE << 80 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 81 82 fcoe_init1.num_tasks = hba->max_tasks; 83 fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX; 84 fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX; 85 fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ; 86 fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX; 87 fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma; 88 fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32); 89 fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma; 90 fcoe_init1.task_list_pbl_addr_hi = 91 (u32) ((u64) hba->task_ctx_bd_dma >> 32); 92 fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU; 93 94 fcoe_init1.flags = (PAGE_SHIFT << 95 FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT); 96 97 fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG; 98 99 /* fill init2 KWQE */ 100 memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2)); 101 fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2; 102 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE << 103 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 104 105 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION; 106 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION; 107 108 109 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma; 110 fcoe_init2.hash_tbl_pbl_addr_hi = (u32) 111 ((u64) hba->hash_tbl_pbl_dma >> 32); 112 113 fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma; 114 fcoe_init2.t2_hash_tbl_addr_hi = (u32) 115 ((u64) hba->t2_hash_tbl_dma >> 32); 116 117 fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma; 118 fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32) 119 ((u64) hba->t2_hash_tbl_ptr_dma >> 32); 120 121 fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS; 122 123 /* fill init3 KWQE */ 124 memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3)); 125 fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3; 126 fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE << 127 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 128 fcoe_init3.error_bit_map_lo = 0xffffffff; 129 fcoe_init3.error_bit_map_hi = 0xffffffff; 130 131 /* 132 * enable both cached connection and cached tasks 133 * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both 134 */ 135 fcoe_init3.perf_config = 3; 136 137 kwqe_arr[0] = (struct kwqe *) &fcoe_init1; 138 kwqe_arr[1] = (struct kwqe *) &fcoe_init2; 139 kwqe_arr[2] = (struct kwqe *) &fcoe_init3; 140 141 if (hba->cnic && hba->cnic->submit_kwqes) 142 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 143 144 return rc; 145} 146int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba) 147{ 148 struct fcoe_kwqe_destroy fcoe_destroy; 149 struct kwqe *kwqe_arr[2]; 150 int num_kwqes = 1; 151 int rc = -1; 152 153 /* fill destroy KWQE */ 154 memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy)); 155 fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY; 156 fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE << 157 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 158 kwqe_arr[0] = (struct kwqe *) &fcoe_destroy; 159 160 if (hba->cnic && hba->cnic->submit_kwqes) 161 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 162 return rc; 163} 164 165/** 166 * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process 167 * 168 * @port: port structure pointer 169 * @tgt: bnx2fc_rport structure pointer 170 */ 171int bnx2fc_send_session_ofld_req(struct fcoe_port *port, 172 struct bnx2fc_rport *tgt) 173{ 174 struct fc_lport *lport = port->lport; 175 struct bnx2fc_interface *interface = port->priv; 176 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 177 struct bnx2fc_hba *hba = interface->hba; 178 struct kwqe *kwqe_arr[4]; 179 struct fcoe_kwqe_conn_offload1 ofld_req1; 180 struct fcoe_kwqe_conn_offload2 ofld_req2; 181 struct fcoe_kwqe_conn_offload3 ofld_req3; 182 struct fcoe_kwqe_conn_offload4 ofld_req4; 183 struct fc_rport_priv *rdata = tgt->rdata; 184 struct fc_rport *rport = tgt->rport; 185 int num_kwqes = 4; 186 u32 port_id; 187 int rc = 0; 188 u16 conn_id; 189 190 /* Initialize offload request 1 structure */ 191 memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1)); 192 193 ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1; 194 ofld_req1.hdr.flags = 195 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 196 197 198 conn_id = (u16)tgt->fcoe_conn_id; 199 ofld_req1.fcoe_conn_id = conn_id; 200 201 202 ofld_req1.sq_addr_lo = (u32) tgt->sq_dma; 203 ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32); 204 205 ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma; 206 ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32); 207 208 ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma; 209 ofld_req1.rq_first_pbe_addr_hi = 210 (u32)((u64) tgt->rq_dma >> 32); 211 212 ofld_req1.rq_prod = 0x8000; 213 214 /* Initialize offload request 2 structure */ 215 memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2)); 216 217 ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2; 218 ofld_req2.hdr.flags = 219 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 220 221 ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size; 222 223 ofld_req2.cq_addr_lo = (u32) tgt->cq_dma; 224 ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32); 225 226 ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma; 227 ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32); 228 229 ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma; 230 ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32); 231 232 /* Initialize offload request 3 structure */ 233 memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3)); 234 235 ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3; 236 ofld_req3.hdr.flags = 237 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 238 239 ofld_req3.vlan_tag = interface->vlan_id << 240 FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT; 241 ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT; 242 243 port_id = fc_host_port_id(lport->host); 244 if (port_id == 0) { 245 BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n"); 246 return -EINVAL; 247 } 248 249 /* 250 * Store s_id of the initiator for further reference. This will 251 * be used during disable/destroy during linkdown processing as 252 * when the lport is reset, the port_id also is reset to 0 253 */ 254 tgt->sid = port_id; 255 ofld_req3.s_id[0] = (port_id & 0x000000FF); 256 ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8; 257 ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16; 258 259 port_id = rport->port_id; 260 ofld_req3.d_id[0] = (port_id & 0x000000FF); 261 ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8; 262 ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16; 263 264 ofld_req3.tx_total_conc_seqs = rdata->max_seq; 265 266 ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq; 267 ofld_req3.rx_max_fc_pay_len = lport->mfs; 268 269 ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS; 270 ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS; 271 ofld_req3.rx_open_seqs_exch_c3 = 1; 272 273 ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma; 274 ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32); 275 276 /* set mul_n_port_ids supported flag to 0, until it is supported */ 277 ofld_req3.flags = 0; 278 /* 279 ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) << 280 FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT); 281 */ 282 /* Info from PLOGI response */ 283 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) << 284 FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT); 285 286 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) << 287 FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT); 288 289 /* 290 * Info from PRLI response, this info is used for sequence level error 291 * recovery support 292 */ 293 if (tgt->dev_type == TYPE_TAPE) { 294 ofld_req3.flags |= 1 << 295 FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT; 296 ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED) 297 ? 1 : 0) << 298 FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT); 299 } 300 301 /* vlan flag */ 302 ofld_req3.flags |= (interface->vlan_enabled << 303 FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT); 304 305 /* C2_VALID and ACK flags are not set as they are not supported */ 306 307 308 /* Initialize offload request 4 structure */ 309 memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4)); 310 ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4; 311 ofld_req4.hdr.flags = 312 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 313 314 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20; 315 316 317 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5]; 318 /* local mac */ 319 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4]; 320 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3]; 321 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2]; 322 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1]; 323 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0]; 324 ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 325 /* fcf mac */ 326 ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 327 ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 328 ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 329 ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 330 ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 331 332 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma; 333 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32); 334 335 ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma; 336 ofld_req4.confq_pbl_base_addr_hi = 337 (u32)((u64) tgt->confq_pbl_dma >> 32); 338 339 kwqe_arr[0] = (struct kwqe *) &ofld_req1; 340 kwqe_arr[1] = (struct kwqe *) &ofld_req2; 341 kwqe_arr[2] = (struct kwqe *) &ofld_req3; 342 kwqe_arr[3] = (struct kwqe *) &ofld_req4; 343 344 if (hba->cnic && hba->cnic->submit_kwqes) 345 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 346 347 return rc; 348} 349 350/** 351 * bnx2fc_send_session_enable_req - initiates FCoE Session enablement 352 * 353 * @port: port structure pointer 354 * @tgt: bnx2fc_rport structure pointer 355 */ 356int bnx2fc_send_session_enable_req(struct fcoe_port *port, 357 struct bnx2fc_rport *tgt) 358{ 359 struct kwqe *kwqe_arr[2]; 360 struct bnx2fc_interface *interface = port->priv; 361 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 362 struct bnx2fc_hba *hba = interface->hba; 363 struct fcoe_kwqe_conn_enable_disable enbl_req; 364 struct fc_lport *lport = port->lport; 365 struct fc_rport *rport = tgt->rport; 366 int num_kwqes = 1; 367 int rc = 0; 368 u32 port_id; 369 370 memset(&enbl_req, 0x00, 371 sizeof(struct fcoe_kwqe_conn_enable_disable)); 372 enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN; 373 enbl_req.hdr.flags = 374 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 375 376 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5]; 377 /* local mac */ 378 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4]; 379 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3]; 380 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2]; 381 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1]; 382 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0]; 383 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN); 384 385 enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 386 enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 387 enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 388 enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 389 enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 390 enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 391 392 port_id = fc_host_port_id(lport->host); 393 if (port_id != tgt->sid) { 394 printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x," 395 "sid = 0x%x\n", port_id, tgt->sid); 396 port_id = tgt->sid; 397 } 398 enbl_req.s_id[0] = (port_id & 0x000000FF); 399 enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8; 400 enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16; 401 402 port_id = rport->port_id; 403 enbl_req.d_id[0] = (port_id & 0x000000FF); 404 enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8; 405 enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16; 406 enbl_req.vlan_tag = interface->vlan_id << 407 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT; 408 enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT; 409 enbl_req.vlan_flag = interface->vlan_enabled; 410 enbl_req.context_id = tgt->context_id; 411 enbl_req.conn_id = tgt->fcoe_conn_id; 412 413 kwqe_arr[0] = (struct kwqe *) &enbl_req; 414 415 if (hba->cnic && hba->cnic->submit_kwqes) 416 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 417 return rc; 418} 419 420/** 421 * bnx2fc_send_session_disable_req - initiates FCoE Session disable 422 * 423 * @port: port structure pointer 424 * @tgt: bnx2fc_rport structure pointer 425 */ 426int bnx2fc_send_session_disable_req(struct fcoe_port *port, 427 struct bnx2fc_rport *tgt) 428{ 429 struct bnx2fc_interface *interface = port->priv; 430 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 431 struct bnx2fc_hba *hba = interface->hba; 432 struct fcoe_kwqe_conn_enable_disable disable_req; 433 struct kwqe *kwqe_arr[2]; 434 struct fc_rport *rport = tgt->rport; 435 int num_kwqes = 1; 436 int rc = 0; 437 u32 port_id; 438 439 memset(&disable_req, 0x00, 440 sizeof(struct fcoe_kwqe_conn_enable_disable)); 441 disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN; 442 disable_req.hdr.flags = 443 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 444 445 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5]; 446 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4]; 447 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3]; 448 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2]; 449 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1]; 450 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0]; 451 452 disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 453 disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 454 disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 455 disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 456 disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 457 disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 458 459 port_id = tgt->sid; 460 disable_req.s_id[0] = (port_id & 0x000000FF); 461 disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8; 462 disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16; 463 464 465 port_id = rport->port_id; 466 disable_req.d_id[0] = (port_id & 0x000000FF); 467 disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8; 468 disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16; 469 disable_req.context_id = tgt->context_id; 470 disable_req.conn_id = tgt->fcoe_conn_id; 471 disable_req.vlan_tag = interface->vlan_id << 472 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT; 473 disable_req.vlan_tag |= 474 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT; 475 disable_req.vlan_flag = interface->vlan_enabled; 476 477 kwqe_arr[0] = (struct kwqe *) &disable_req; 478 479 if (hba->cnic && hba->cnic->submit_kwqes) 480 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 481 482 return rc; 483} 484 485/** 486 * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy 487 * 488 * @hba: adapter structure pointer 489 * @tgt: bnx2fc_rport structure pointer 490 */ 491int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba, 492 struct bnx2fc_rport *tgt) 493{ 494 struct fcoe_kwqe_conn_destroy destroy_req; 495 struct kwqe *kwqe_arr[2]; 496 int num_kwqes = 1; 497 int rc = 0; 498 499 memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy)); 500 destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN; 501 destroy_req.hdr.flags = 502 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 503 504 destroy_req.context_id = tgt->context_id; 505 destroy_req.conn_id = tgt->fcoe_conn_id; 506 507 kwqe_arr[0] = (struct kwqe *) &destroy_req; 508 509 if (hba->cnic && hba->cnic->submit_kwqes) 510 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 511 512 return rc; 513} 514 515static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport) 516{ 517 struct bnx2fc_lport *blport; 518 519 spin_lock_bh(&hba->hba_lock); 520 list_for_each_entry(blport, &hba->vports, list) { 521 if (blport->lport == lport) { 522 spin_unlock_bh(&hba->hba_lock); 523 return true; 524 } 525 } 526 spin_unlock_bh(&hba->hba_lock); 527 return false; 528 529} 530 531 532static void bnx2fc_unsol_els_work(struct work_struct *work) 533{ 534 struct bnx2fc_unsol_els *unsol_els; 535 struct fc_lport *lport; 536 struct bnx2fc_hba *hba; 537 struct fc_frame *fp; 538 539 unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work); 540 lport = unsol_els->lport; 541 fp = unsol_els->fp; 542 hba = unsol_els->hba; 543 if (is_valid_lport(hba, lport)) 544 fc_exch_recv(lport, fp); 545 kfree(unsol_els); 546} 547 548void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt, 549 unsigned char *buf, 550 u32 frame_len, u16 l2_oxid) 551{ 552 struct fcoe_port *port = tgt->port; 553 struct fc_lport *lport = port->lport; 554 struct bnx2fc_interface *interface = port->priv; 555 struct bnx2fc_unsol_els *unsol_els; 556 struct fc_frame_header *fh; 557 struct fc_frame *fp; 558 struct sk_buff *skb; 559 u32 payload_len; 560 u32 crc; 561 u8 op; 562 563 564 unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC); 565 if (!unsol_els) { 566 BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n"); 567 return; 568 } 569 570 BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n", 571 l2_oxid, frame_len); 572 573 payload_len = frame_len - sizeof(struct fc_frame_header); 574 575 fp = fc_frame_alloc(lport, payload_len); 576 if (!fp) { 577 printk(KERN_ERR PFX "fc_frame_alloc failure\n"); 578 kfree(unsol_els); 579 return; 580 } 581 582 fh = (struct fc_frame_header *) fc_frame_header_get(fp); 583 /* Copy FC Frame header and payload into the frame */ 584 memcpy(fh, buf, frame_len); 585 586 if (l2_oxid != FC_XID_UNKNOWN) 587 fh->fh_ox_id = htons(l2_oxid); 588 589 skb = fp_skb(fp); 590 591 if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) || 592 (fh->fh_r_ctl == FC_RCTL_ELS_REP)) { 593 594 if (fh->fh_type == FC_TYPE_ELS) { 595 op = fc_frame_payload_op(fp); 596 if ((op == ELS_TEST) || (op == ELS_ESTC) || 597 (op == ELS_FAN) || (op == ELS_CSU)) { 598 /* 599 * No need to reply for these 600 * ELS requests 601 */ 602 printk(KERN_ERR PFX "dropping ELS 0x%x\n", op); 603 kfree_skb(skb); 604 kfree(unsol_els); 605 return; 606 } 607 } 608 crc = fcoe_fc_crc(fp); 609 fc_frame_init(fp); 610 fr_dev(fp) = lport; 611 fr_sof(fp) = FC_SOF_I3; 612 fr_eof(fp) = FC_EOF_T; 613 fr_crc(fp) = cpu_to_le32(~crc); 614 unsol_els->lport = lport; 615 unsol_els->hba = interface->hba; 616 unsol_els->fp = fp; 617 INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work); 618 queue_work(bnx2fc_wq, &unsol_els->unsol_els_work); 619 } else { 620 BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl); 621 kfree_skb(skb); 622 kfree(unsol_els); 623 } 624} 625 626static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe) 627{ 628 u8 num_rq; 629 struct fcoe_err_report_entry *err_entry; 630 unsigned char *rq_data; 631 unsigned char *buf = NULL, *buf1; 632 int i; 633 u16 xid; 634 u32 frame_len, len; 635 struct bnx2fc_cmd *io_req = NULL; 636 struct bnx2fc_interface *interface = tgt->port->priv; 637 struct bnx2fc_hba *hba = interface->hba; 638 int rc = 0; 639 u64 err_warn_bit_map; 640 u8 err_warn = 0xff; 641 642 643 BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe); 644 switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) { 645 case FCOE_UNSOLICITED_FRAME_CQE_TYPE: 646 frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >> 647 FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT; 648 649 num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ; 650 651 spin_lock_bh(&tgt->tgt_lock); 652 rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq); 653 spin_unlock_bh(&tgt->tgt_lock); 654 655 if (rq_data) { 656 buf = rq_data; 657 } else { 658 buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ), 659 GFP_ATOMIC); 660 661 if (!buf1) { 662 BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n"); 663 break; 664 } 665 666 for (i = 0; i < num_rq; i++) { 667 spin_lock_bh(&tgt->tgt_lock); 668 rq_data = (unsigned char *) 669 bnx2fc_get_next_rqe(tgt, 1); 670 spin_unlock_bh(&tgt->tgt_lock); 671 len = BNX2FC_RQ_BUF_SZ; 672 memcpy(buf1, rq_data, len); 673 buf1 += len; 674 } 675 } 676 bnx2fc_process_l2_frame_compl(tgt, buf, frame_len, 677 FC_XID_UNKNOWN); 678 679 if (buf != rq_data) 680 kfree(buf); 681 spin_lock_bh(&tgt->tgt_lock); 682 bnx2fc_return_rqe(tgt, num_rq); 683 spin_unlock_bh(&tgt->tgt_lock); 684 break; 685 686 case FCOE_ERROR_DETECTION_CQE_TYPE: 687 /* 688 * In case of error reporting CQE a single RQ entry 689 * is consumed. 690 */ 691 spin_lock_bh(&tgt->tgt_lock); 692 num_rq = 1; 693 err_entry = (struct fcoe_err_report_entry *) 694 bnx2fc_get_next_rqe(tgt, 1); 695 xid = err_entry->fc_hdr.ox_id; 696 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid); 697 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n", 698 err_entry->data.err_warn_bitmap_hi, 699 err_entry->data.err_warn_bitmap_lo); 700 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n", 701 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off); 702 703 if (xid > hba->max_xid) { 704 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", 705 xid); 706 goto ret_err_rqe; 707 } 708 709 710 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 711 if (!io_req) 712 goto ret_err_rqe; 713 714 if (io_req->cmd_type != BNX2FC_SCSI_CMD) { 715 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n"); 716 goto ret_err_rqe; 717 } 718 719 if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP, 720 &io_req->req_flags)) { 721 BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in " 722 "progress.. ignore unsol err\n"); 723 goto ret_err_rqe; 724 } 725 726 err_warn_bit_map = (u64) 727 ((u64)err_entry->data.err_warn_bitmap_hi << 32) | 728 (u64)err_entry->data.err_warn_bitmap_lo; 729 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) { 730 if (err_warn_bit_map & (u64)((u64)1 << i)) { 731 err_warn = i; 732 break; 733 } 734 } 735 736 /* 737 * If ABTS is already in progress, and FW error is 738 * received after that, do not cancel the timeout_work 739 * and let the error recovery continue by explicitly 740 * logging out the target, when the ABTS eventually 741 * times out. 742 */ 743 if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) { 744 printk(KERN_ERR PFX "err_warn: io_req (0x%x) already " 745 "in ABTS processing\n", xid); 746 goto ret_err_rqe; 747 } 748 BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn); 749 if (tgt->dev_type != TYPE_TAPE) 750 goto skip_rec; 751 switch (err_warn) { 752 case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION: 753 case FCOE_ERROR_CODE_DATA_OOO_RO: 754 case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT: 755 case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET: 756 case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ: 757 case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET: 758 BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n", 759 xid); 760 memcpy(&io_req->err_entry, err_entry, 761 sizeof(struct fcoe_err_report_entry)); 762 if (!test_bit(BNX2FC_FLAG_SRR_SENT, 763 &io_req->req_flags)) { 764 spin_unlock_bh(&tgt->tgt_lock); 765 rc = bnx2fc_send_rec(io_req); 766 spin_lock_bh(&tgt->tgt_lock); 767 768 if (rc) 769 goto skip_rec; 770 } else 771 printk(KERN_ERR PFX "SRR in progress\n"); 772 goto ret_err_rqe; 773 break; 774 default: 775 break; 776 } 777 778skip_rec: 779 set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags); 780 /* 781 * Cancel the timeout_work, as we received IO 782 * completion with FW error. 783 */ 784 if (cancel_delayed_work(&io_req->timeout_work)) 785 kref_put(&io_req->refcount, bnx2fc_cmd_release); 786 787 rc = bnx2fc_initiate_abts(io_req); 788 if (rc != SUCCESS) { 789 printk(KERN_ERR PFX "err_warn: initiate_abts " 790 "failed xid = 0x%x. issue cleanup\n", 791 io_req->xid); 792 bnx2fc_initiate_cleanup(io_req); 793 } 794ret_err_rqe: 795 bnx2fc_return_rqe(tgt, 1); 796 spin_unlock_bh(&tgt->tgt_lock); 797 break; 798 799 case FCOE_WARNING_DETECTION_CQE_TYPE: 800 /* 801 *In case of warning reporting CQE a single RQ entry 802 * is consumes. 803 */ 804 spin_lock_bh(&tgt->tgt_lock); 805 num_rq = 1; 806 err_entry = (struct fcoe_err_report_entry *) 807 bnx2fc_get_next_rqe(tgt, 1); 808 xid = cpu_to_be16(err_entry->fc_hdr.ox_id); 809 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid); 810 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x", 811 err_entry->data.err_warn_bitmap_hi, 812 err_entry->data.err_warn_bitmap_lo); 813 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x", 814 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off); 815 816 if (xid > hba->max_xid) { 817 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid); 818 goto ret_warn_rqe; 819 } 820 821 err_warn_bit_map = (u64) 822 ((u64)err_entry->data.err_warn_bitmap_hi << 32) | 823 (u64)err_entry->data.err_warn_bitmap_lo; 824 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) { 825 if (err_warn_bit_map & ((u64)1 << i)) { 826 err_warn = i; 827 break; 828 } 829 } 830 BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn); 831 832 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 833 if (!io_req) 834 goto ret_warn_rqe; 835 836 if (io_req->cmd_type != BNX2FC_SCSI_CMD) { 837 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n"); 838 goto ret_warn_rqe; 839 } 840 841 memcpy(&io_req->err_entry, err_entry, 842 sizeof(struct fcoe_err_report_entry)); 843 844 if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION) 845 /* REC_TOV is not a warning code */ 846 BUG_ON(1); 847 else 848 BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n"); 849ret_warn_rqe: 850 bnx2fc_return_rqe(tgt, 1); 851 spin_unlock_bh(&tgt->tgt_lock); 852 break; 853 854 default: 855 printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n"); 856 break; 857 } 858} 859 860void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe, 861 unsigned char *rq_data, u8 num_rq, 862 struct fcoe_task_ctx_entry *task) 863{ 864 struct fcoe_port *port = tgt->port; 865 struct bnx2fc_interface *interface = port->priv; 866 struct bnx2fc_hba *hba = interface->hba; 867 struct bnx2fc_cmd *io_req; 868 869 u16 xid; 870 u8 cmd_type; 871 u8 rx_state = 0; 872 873 spin_lock_bh(&tgt->tgt_lock); 874 875 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID; 876 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 877 878 if (io_req == NULL) { 879 printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n"); 880 spin_unlock_bh(&tgt->tgt_lock); 881 return; 882 } 883 884 /* Timestamp IO completion time */ 885 cmd_type = io_req->cmd_type; 886 887 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags & 888 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >> 889 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT); 890 891 /* Process other IO completion types */ 892 switch (cmd_type) { 893 case BNX2FC_SCSI_CMD: 894 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) { 895 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq, 896 rq_data); 897 spin_unlock_bh(&tgt->tgt_lock); 898 return; 899 } 900 901 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED) 902 bnx2fc_process_abts_compl(io_req, task, num_rq); 903 else if (rx_state == 904 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED) 905 bnx2fc_process_cleanup_compl(io_req, task, num_rq); 906 else 907 printk(KERN_ERR PFX "Invalid rx state - %d\n", 908 rx_state); 909 break; 910 911 case BNX2FC_TASK_MGMT_CMD: 912 BNX2FC_IO_DBG(io_req, "Processing TM complete\n"); 913 bnx2fc_process_tm_compl(io_req, task, num_rq, rq_data); 914 break; 915 916 case BNX2FC_ABTS: 917 /* 918 * ABTS request received by firmware. ABTS response 919 * will be delivered to the task belonging to the IO 920 * that was aborted 921 */ 922 BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n"); 923 kref_put(&io_req->refcount, bnx2fc_cmd_release); 924 break; 925 926 case BNX2FC_ELS: 927 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) 928 bnx2fc_process_els_compl(io_req, task, num_rq); 929 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED) 930 bnx2fc_process_abts_compl(io_req, task, num_rq); 931 else if (rx_state == 932 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED) 933 bnx2fc_process_cleanup_compl(io_req, task, num_rq); 934 else 935 printk(KERN_ERR PFX "Invalid rx state = %d\n", 936 rx_state); 937 break; 938 939 case BNX2FC_CLEANUP: 940 BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n"); 941 kref_put(&io_req->refcount, bnx2fc_cmd_release); 942 break; 943 944 case BNX2FC_SEQ_CLEANUP: 945 BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n", 946 io_req->xid); 947 bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state); 948 kref_put(&io_req->refcount, bnx2fc_cmd_release); 949 break; 950 951 default: 952 printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type); 953 break; 954 } 955 spin_unlock_bh(&tgt->tgt_lock); 956} 957 958void bnx2fc_arm_cq(struct bnx2fc_rport *tgt) 959{ 960 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db; 961 u32 msg; 962 963 wmb(); 964 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit << 965 FCOE_CQE_TOGGLE_BIT_SHIFT); 966 msg = *((u32 *)rx_db); 967 writel(cpu_to_le32(msg), tgt->ctx_base); 968 969} 970 971static struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe, 972 unsigned char *rq_data, u8 num_rq, 973 struct fcoe_task_ctx_entry *task) 974{ 975 struct bnx2fc_work *work; 976 work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC); 977 if (!work) 978 return NULL; 979 980 INIT_LIST_HEAD(&work->list); 981 work->tgt = tgt; 982 work->wqe = wqe; 983 work->num_rq = num_rq; 984 work->task = task; 985 if (rq_data) 986 memcpy(work->rq_data, rq_data, BNX2FC_RQ_BUF_SZ); 987 988 return work; 989} 990 991/* Pending work request completion */ 992static bool bnx2fc_pending_work(struct bnx2fc_rport *tgt, unsigned int wqe) 993{ 994 unsigned int cpu = wqe % num_possible_cpus(); 995 struct bnx2fc_percpu_s *fps; 996 struct bnx2fc_work *work; 997 struct fcoe_task_ctx_entry *task; 998 struct fcoe_task_ctx_entry *task_page; 999 struct fcoe_port *port = tgt->port; 1000 struct bnx2fc_interface *interface = port->priv; 1001 struct bnx2fc_hba *hba = interface->hba; 1002 unsigned char *rq_data = NULL; 1003 unsigned char rq_data_buff[BNX2FC_RQ_BUF_SZ]; 1004 int task_idx, index; 1005 u16 xid; 1006 u8 num_rq; 1007 int i; 1008 1009 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID; 1010 if (xid >= hba->max_tasks) { 1011 pr_err(PFX "ERROR:xid out of range\n"); 1012 return false; 1013 } 1014 1015 task_idx = xid / BNX2FC_TASKS_PER_PAGE; 1016 index = xid % BNX2FC_TASKS_PER_PAGE; 1017 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx]; 1018 task = &task_page[index]; 1019 1020 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags & 1021 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >> 1022 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT); 1023 1024 memset(rq_data_buff, 0, BNX2FC_RQ_BUF_SZ); 1025 1026 if (!num_rq) 1027 goto num_rq_zero; 1028 1029 rq_data = bnx2fc_get_next_rqe(tgt, 1); 1030 1031 if (num_rq > 1) { 1032 /* We do not need extra sense data */ 1033 for (i = 1; i < num_rq; i++) 1034 bnx2fc_get_next_rqe(tgt, 1); 1035 } 1036 1037 if (rq_data) 1038 memcpy(rq_data_buff, rq_data, BNX2FC_RQ_BUF_SZ); 1039 1040 /* return RQ entries */ 1041 for (i = 0; i < num_rq; i++) 1042 bnx2fc_return_rqe(tgt, 1); 1043 1044num_rq_zero: 1045 1046 fps = &per_cpu(bnx2fc_percpu, cpu); 1047 spin_lock_bh(&fps->fp_work_lock); 1048 if (fps->iothread) { 1049 work = bnx2fc_alloc_work(tgt, wqe, rq_data_buff, 1050 num_rq, task); 1051 if (work) { 1052 list_add_tail(&work->list, &fps->work_list); 1053 wake_up_process(fps->iothread); 1054 spin_unlock_bh(&fps->fp_work_lock); 1055 return true; 1056 } 1057 } 1058 spin_unlock_bh(&fps->fp_work_lock); 1059 bnx2fc_process_cq_compl(tgt, wqe, 1060 rq_data_buff, num_rq, task); 1061 1062 return true; 1063} 1064 1065int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt) 1066{ 1067 struct fcoe_cqe *cq; 1068 u32 cq_cons; 1069 struct fcoe_cqe *cqe; 1070 u32 num_free_sqes = 0; 1071 u32 num_cqes = 0; 1072 u16 wqe; 1073 1074 /* 1075 * cq_lock is a low contention lock used to protect 1076 * the CQ data structure from being freed up during 1077 * the upload operation 1078 */ 1079 spin_lock_bh(&tgt->cq_lock); 1080 1081 if (!tgt->cq) { 1082 printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n"); 1083 spin_unlock_bh(&tgt->cq_lock); 1084 return 0; 1085 } 1086 cq = tgt->cq; 1087 cq_cons = tgt->cq_cons_idx; 1088 cqe = &cq[cq_cons]; 1089 1090 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) == 1091 (tgt->cq_curr_toggle_bit << 1092 FCOE_CQE_TOGGLE_BIT_SHIFT)) { 1093 1094 /* new entry on the cq */ 1095 if (wqe & FCOE_CQE_CQE_TYPE) { 1096 /* Unsolicited event notification */ 1097 bnx2fc_process_unsol_compl(tgt, wqe); 1098 } else { 1099 if (bnx2fc_pending_work(tgt, wqe)) 1100 num_free_sqes++; 1101 } 1102 cqe++; 1103 tgt->cq_cons_idx++; 1104 num_cqes++; 1105 1106 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) { 1107 tgt->cq_cons_idx = 0; 1108 cqe = cq; 1109 tgt->cq_curr_toggle_bit = 1110 1 - tgt->cq_curr_toggle_bit; 1111 } 1112 } 1113 if (num_cqes) { 1114 /* Arm CQ only if doorbell is mapped */ 1115 if (tgt->ctx_base) 1116 bnx2fc_arm_cq(tgt); 1117 atomic_add(num_free_sqes, &tgt->free_sqes); 1118 } 1119 spin_unlock_bh(&tgt->cq_lock); 1120 return 0; 1121} 1122 1123/** 1124 * bnx2fc_fastpath_notification - process global event queue (KCQ) 1125 * 1126 * @hba: adapter structure pointer 1127 * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry 1128 * 1129 * Fast path event notification handler 1130 */ 1131static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba, 1132 struct fcoe_kcqe *new_cqe_kcqe) 1133{ 1134 u32 conn_id = new_cqe_kcqe->fcoe_conn_id; 1135 struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id]; 1136 1137 if (!tgt) { 1138 printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id); 1139 return; 1140 } 1141 1142 bnx2fc_process_new_cqes(tgt); 1143} 1144 1145/** 1146 * bnx2fc_process_ofld_cmpl - process FCoE session offload completion 1147 * 1148 * @hba: adapter structure pointer 1149 * @ofld_kcqe: connection offload kcqe pointer 1150 * 1151 * handle session offload completion, enable the session if offload is 1152 * successful. 1153 */ 1154static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba, 1155 struct fcoe_kcqe *ofld_kcqe) 1156{ 1157 struct bnx2fc_rport *tgt; 1158 struct bnx2fc_interface *interface; 1159 u32 conn_id; 1160 u32 context_id; 1161 1162 conn_id = ofld_kcqe->fcoe_conn_id; 1163 context_id = ofld_kcqe->fcoe_conn_context_id; 1164 tgt = hba->tgt_ofld_list[conn_id]; 1165 if (!tgt) { 1166 printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n"); 1167 return; 1168 } 1169 BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n", 1170 ofld_kcqe->fcoe_conn_context_id); 1171 interface = tgt->port->priv; 1172 if (hba != interface->hba) { 1173 printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n"); 1174 goto ofld_cmpl_err; 1175 } 1176 /* 1177 * cnic has allocated a context_id for this session; use this 1178 * while enabling the session. 1179 */ 1180 tgt->context_id = context_id; 1181 if (ofld_kcqe->completion_status) { 1182 if (ofld_kcqe->completion_status == 1183 FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) { 1184 printk(KERN_ERR PFX "unable to allocate FCoE context " 1185 "resources\n"); 1186 set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags); 1187 } 1188 } else { 1189 /* FW offload request successfully completed */ 1190 set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags); 1191 } 1192ofld_cmpl_err: 1193 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags); 1194 wake_up_interruptible(&tgt->ofld_wait); 1195} 1196 1197/** 1198 * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion 1199 * 1200 * @hba: adapter structure pointer 1201 * @ofld_kcqe: connection offload kcqe pointer 1202 * 1203 * handle session enable completion, mark the rport as ready 1204 */ 1205 1206static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba, 1207 struct fcoe_kcqe *ofld_kcqe) 1208{ 1209 struct bnx2fc_rport *tgt; 1210 struct bnx2fc_interface *interface; 1211 u32 conn_id; 1212 u32 context_id; 1213 1214 context_id = ofld_kcqe->fcoe_conn_context_id; 1215 conn_id = ofld_kcqe->fcoe_conn_id; 1216 tgt = hba->tgt_ofld_list[conn_id]; 1217 if (!tgt) { 1218 printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n"); 1219 return; 1220 } 1221 1222 BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n", 1223 ofld_kcqe->fcoe_conn_context_id); 1224 1225 /* 1226 * context_id should be the same for this target during offload 1227 * and enable 1228 */ 1229 if (tgt->context_id != context_id) { 1230 printk(KERN_ERR PFX "context id mis-match\n"); 1231 return; 1232 } 1233 interface = tgt->port->priv; 1234 if (hba != interface->hba) { 1235 printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n"); 1236 goto enbl_cmpl_err; 1237 } 1238 if (!ofld_kcqe->completion_status) 1239 /* enable successful - rport ready for issuing IOs */ 1240 set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags); 1241 1242enbl_cmpl_err: 1243 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags); 1244 wake_up_interruptible(&tgt->ofld_wait); 1245} 1246 1247static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba, 1248 struct fcoe_kcqe *disable_kcqe) 1249{ 1250 1251 struct bnx2fc_rport *tgt; 1252 u32 conn_id; 1253 1254 conn_id = disable_kcqe->fcoe_conn_id; 1255 tgt = hba->tgt_ofld_list[conn_id]; 1256 if (!tgt) { 1257 printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n"); 1258 return; 1259 } 1260 1261 BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id); 1262 1263 if (disable_kcqe->completion_status) { 1264 printk(KERN_ERR PFX "Disable failed with cmpl status %d\n", 1265 disable_kcqe->completion_status); 1266 set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags); 1267 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1268 wake_up_interruptible(&tgt->upld_wait); 1269 } else { 1270 /* disable successful */ 1271 BNX2FC_TGT_DBG(tgt, "disable successful\n"); 1272 clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags); 1273 clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags); 1274 set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags); 1275 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1276 wake_up_interruptible(&tgt->upld_wait); 1277 } 1278} 1279 1280static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba, 1281 struct fcoe_kcqe *destroy_kcqe) 1282{ 1283 struct bnx2fc_rport *tgt; 1284 u32 conn_id; 1285 1286 conn_id = destroy_kcqe->fcoe_conn_id; 1287 tgt = hba->tgt_ofld_list[conn_id]; 1288 if (!tgt) { 1289 printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n"); 1290 return; 1291 } 1292 1293 BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id); 1294 1295 if (destroy_kcqe->completion_status) { 1296 printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n", 1297 destroy_kcqe->completion_status); 1298 return; 1299 } else { 1300 /* destroy successful */ 1301 BNX2FC_TGT_DBG(tgt, "upload successful\n"); 1302 clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags); 1303 set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags); 1304 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1305 wake_up_interruptible(&tgt->upld_wait); 1306 } 1307} 1308 1309static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code) 1310{ 1311 switch (err_code) { 1312 case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE: 1313 printk(KERN_ERR PFX "init_failure due to invalid opcode\n"); 1314 break; 1315 1316 case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE: 1317 printk(KERN_ERR PFX "init failed due to ctx alloc failure\n"); 1318 break; 1319 1320 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR: 1321 printk(KERN_ERR PFX "init_failure due to NIC error\n"); 1322 break; 1323 case FCOE_KCQE_COMPLETION_STATUS_ERROR: 1324 printk(KERN_ERR PFX "init failure due to compl status err\n"); 1325 break; 1326 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION: 1327 printk(KERN_ERR PFX "init failure due to HSI mismatch\n"); 1328 break; 1329 default: 1330 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code); 1331 } 1332} 1333 1334/** 1335 * bnx2fc_indicae_kcqe - process KCQE 1336 * 1337 * @context: adapter structure pointer 1338 * @kcq: kcqe pointer 1339 * @num_cqe: Number of completion queue elements 1340 * 1341 * Generic KCQ event handler 1342 */ 1343void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[], 1344 u32 num_cqe) 1345{ 1346 struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context; 1347 int i = 0; 1348 struct fcoe_kcqe *kcqe = NULL; 1349 1350 while (i < num_cqe) { 1351 kcqe = (struct fcoe_kcqe *) kcq[i++]; 1352 1353 switch (kcqe->op_code) { 1354 case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION: 1355 bnx2fc_fastpath_notification(hba, kcqe); 1356 break; 1357 1358 case FCOE_KCQE_OPCODE_OFFLOAD_CONN: 1359 bnx2fc_process_ofld_cmpl(hba, kcqe); 1360 break; 1361 1362 case FCOE_KCQE_OPCODE_ENABLE_CONN: 1363 bnx2fc_process_enable_conn_cmpl(hba, kcqe); 1364 break; 1365 1366 case FCOE_KCQE_OPCODE_INIT_FUNC: 1367 if (kcqe->completion_status != 1368 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) { 1369 bnx2fc_init_failure(hba, 1370 kcqe->completion_status); 1371 } else { 1372 set_bit(ADAPTER_STATE_UP, &hba->adapter_state); 1373 bnx2fc_get_link_state(hba); 1374 printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n", 1375 (u8)hba->pcidev->bus->number); 1376 } 1377 break; 1378 1379 case FCOE_KCQE_OPCODE_DESTROY_FUNC: 1380 if (kcqe->completion_status != 1381 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) { 1382 1383 printk(KERN_ERR PFX "DESTROY failed\n"); 1384 } else { 1385 printk(KERN_ERR PFX "DESTROY success\n"); 1386 } 1387 set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags); 1388 wake_up_interruptible(&hba->destroy_wait); 1389 break; 1390 1391 case FCOE_KCQE_OPCODE_DISABLE_CONN: 1392 bnx2fc_process_conn_disable_cmpl(hba, kcqe); 1393 break; 1394 1395 case FCOE_KCQE_OPCODE_DESTROY_CONN: 1396 bnx2fc_process_conn_destroy_cmpl(hba, kcqe); 1397 break; 1398 1399 case FCOE_KCQE_OPCODE_STAT_FUNC: 1400 if (kcqe->completion_status != 1401 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) 1402 printk(KERN_ERR PFX "STAT failed\n"); 1403 complete(&hba->stat_req_done); 1404 break; 1405 1406 case FCOE_KCQE_OPCODE_FCOE_ERROR: 1407 default: 1408 printk(KERN_ERR PFX "unknown opcode 0x%x\n", 1409 kcqe->op_code); 1410 } 1411 } 1412} 1413 1414void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid) 1415{ 1416 struct fcoe_sqe *sqe; 1417 1418 sqe = &tgt->sq[tgt->sq_prod_idx]; 1419 1420 /* Fill SQ WQE */ 1421 sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT; 1422 sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT; 1423 1424 /* Advance SQ Prod Idx */ 1425 if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) { 1426 tgt->sq_prod_idx = 0; 1427 tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit; 1428 } 1429} 1430 1431void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt) 1432{ 1433 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db; 1434 u32 msg; 1435 1436 wmb(); 1437 sq_db->prod = tgt->sq_prod_idx | 1438 (tgt->sq_curr_toggle_bit << 15); 1439 msg = *((u32 *)sq_db); 1440 writel(cpu_to_le32(msg), tgt->ctx_base); 1441 1442} 1443 1444int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt) 1445{ 1446 u32 context_id = tgt->context_id; 1447 struct fcoe_port *port = tgt->port; 1448 u32 reg_off; 1449 resource_size_t reg_base; 1450 struct bnx2fc_interface *interface = port->priv; 1451 struct bnx2fc_hba *hba = interface->hba; 1452 1453 reg_base = pci_resource_start(hba->pcidev, 1454 BNX2X_DOORBELL_PCI_BAR); 1455 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF); 1456 tgt->ctx_base = ioremap(reg_base + reg_off, 4); 1457 if (!tgt->ctx_base) 1458 return -ENOMEM; 1459 return 0; 1460} 1461 1462char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items) 1463{ 1464 char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ); 1465 1466 if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX) 1467 return NULL; 1468 1469 tgt->rq_cons_idx += num_items; 1470 1471 if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX) 1472 tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX; 1473 1474 return buf; 1475} 1476 1477void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items) 1478{ 1479 /* return the rq buffer */ 1480 u32 next_prod_idx = tgt->rq_prod_idx + num_items; 1481 if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) { 1482 /* Wrap around RQ */ 1483 next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX; 1484 } 1485 tgt->rq_prod_idx = next_prod_idx; 1486 tgt->conn_db->rq_prod = tgt->rq_prod_idx; 1487} 1488 1489void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req, 1490 struct fcoe_task_ctx_entry *task, 1491 struct bnx2fc_cmd *orig_io_req, 1492 u32 offset) 1493{ 1494 struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd; 1495 struct bnx2fc_rport *tgt = seq_clnp_req->tgt; 1496 struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl; 1497 struct fcoe_ext_mul_sges_ctx *sgl; 1498 u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP; 1499 u8 orig_task_type; 1500 u16 orig_xid = orig_io_req->xid; 1501 u32 context_id = tgt->context_id; 1502 u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma; 1503 u32 orig_offset = offset; 1504 int bd_count; 1505 int i; 1506 1507 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1508 1509 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE) 1510 orig_task_type = FCOE_TASK_TYPE_WRITE; 1511 else 1512 orig_task_type = FCOE_TASK_TYPE_READ; 1513 1514 /* Tx flags */ 1515 task->txwr_rxrd.const_ctx.tx_flags = 1516 FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP << 1517 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1518 /* init flags */ 1519 task->txwr_rxrd.const_ctx.init_flags = task_type << 1520 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1521 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1522 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1523 task->rxwr_txrd.const_ctx.init_flags = context_id << 1524 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1525 task->rxwr_txrd.const_ctx.init_flags = context_id << 1526 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1527 1528 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid; 1529 1530 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0; 1531 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset; 1532 1533 bd_count = orig_io_req->bd_tbl->bd_valid; 1534 1535 /* obtain the appropriate bd entry from relative offset */ 1536 for (i = 0; i < bd_count; i++) { 1537 if (offset < bd[i].buf_len) 1538 break; 1539 offset -= bd[i].buf_len; 1540 } 1541 phys_addr += (i * sizeof(struct fcoe_bd_ctx)); 1542 1543 if (orig_task_type == FCOE_TASK_TYPE_WRITE) { 1544 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1545 (u32)phys_addr; 1546 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1547 (u32)((u64)phys_addr >> 32); 1548 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1549 bd_count; 1550 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off = 1551 offset; /* adjusted offset */ 1552 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i; 1553 } else { 1554 1555 /* Multiple SGEs were used for this IO */ 1556 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1557 sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr; 1558 sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32); 1559 sgl->mul_sgl.sgl_size = bd_count; 1560 sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */ 1561 sgl->mul_sgl.cur_sge_idx = i; 1562 1563 memset(&task->rxwr_only.rx_seq_ctx, 0, 1564 sizeof(struct fcoe_rx_seq_ctx)); 1565 task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset; 1566 task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset; 1567 } 1568} 1569void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req, 1570 struct fcoe_task_ctx_entry *task, 1571 u16 orig_xid) 1572{ 1573 u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP; 1574 struct bnx2fc_rport *tgt = io_req->tgt; 1575 u32 context_id = tgt->context_id; 1576 1577 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1578 1579 /* Tx Write Rx Read */ 1580 /* init flags */ 1581 task->txwr_rxrd.const_ctx.init_flags = task_type << 1582 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1583 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1584 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1585 if (tgt->dev_type == TYPE_TAPE) 1586 task->txwr_rxrd.const_ctx.init_flags |= 1587 FCOE_TASK_DEV_TYPE_TAPE << 1588 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1589 else 1590 task->txwr_rxrd.const_ctx.init_flags |= 1591 FCOE_TASK_DEV_TYPE_DISK << 1592 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1593 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid; 1594 1595 /* Tx flags */ 1596 task->txwr_rxrd.const_ctx.tx_flags = 1597 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP << 1598 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1599 1600 /* Rx Read Tx Write */ 1601 task->rxwr_txrd.const_ctx.init_flags = context_id << 1602 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1603 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1604 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1605} 1606 1607void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req, 1608 struct fcoe_task_ctx_entry *task) 1609{ 1610 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req); 1611 struct bnx2fc_rport *tgt = io_req->tgt; 1612 struct fc_frame_header *fc_hdr; 1613 struct fcoe_ext_mul_sges_ctx *sgl; 1614 u8 task_type = 0; 1615 u64 *hdr; 1616 u64 temp_hdr[3]; 1617 u32 context_id; 1618 1619 1620 /* Obtain task_type */ 1621 if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) || 1622 (io_req->cmd_type == BNX2FC_ELS)) { 1623 task_type = FCOE_TASK_TYPE_MIDPATH; 1624 } else if (io_req->cmd_type == BNX2FC_ABTS) { 1625 task_type = FCOE_TASK_TYPE_ABTS; 1626 } 1627 1628 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1629 1630 /* Setup the task from io_req for easy reference */ 1631 io_req->task = task; 1632 1633 BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n", 1634 io_req->cmd_type, task_type); 1635 1636 /* Tx only */ 1637 if ((task_type == FCOE_TASK_TYPE_MIDPATH) || 1638 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) { 1639 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1640 (u32)mp_req->mp_req_bd_dma; 1641 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1642 (u32)((u64)mp_req->mp_req_bd_dma >> 32); 1643 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1; 1644 } 1645 1646 /* Tx Write Rx Read */ 1647 /* init flags */ 1648 task->txwr_rxrd.const_ctx.init_flags = task_type << 1649 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1650 if (tgt->dev_type == TYPE_TAPE) 1651 task->txwr_rxrd.const_ctx.init_flags |= 1652 FCOE_TASK_DEV_TYPE_TAPE << 1653 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1654 else 1655 task->txwr_rxrd.const_ctx.init_flags |= 1656 FCOE_TASK_DEV_TYPE_DISK << 1657 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1658 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1659 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1660 1661 /* tx flags */ 1662 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT << 1663 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1664 1665 /* Rx Write Tx Read */ 1666 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len; 1667 1668 /* rx flags */ 1669 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1670 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1671 1672 context_id = tgt->context_id; 1673 task->rxwr_txrd.const_ctx.init_flags = context_id << 1674 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1675 1676 fc_hdr = &(mp_req->req_fc_hdr); 1677 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1678 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid); 1679 fc_hdr->fh_rx_id = htons(0xffff); 1680 task->rxwr_txrd.var_ctx.rx_id = 0xffff; 1681 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) { 1682 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid); 1683 } 1684 1685 /* Fill FC Header into middle path buffer */ 1686 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr; 1687 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr)); 1688 hdr[0] = cpu_to_be64(temp_hdr[0]); 1689 hdr[1] = cpu_to_be64(temp_hdr[1]); 1690 hdr[2] = cpu_to_be64(temp_hdr[2]); 1691 1692 /* Rx Only */ 1693 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1694 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1695 1696 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma; 1697 sgl->mul_sgl.cur_sge_addr.hi = 1698 (u32)((u64)mp_req->mp_resp_bd_dma >> 32); 1699 sgl->mul_sgl.sgl_size = 1; 1700 } 1701} 1702 1703void bnx2fc_init_task(struct bnx2fc_cmd *io_req, 1704 struct fcoe_task_ctx_entry *task) 1705{ 1706 u8 task_type; 1707 struct scsi_cmnd *sc_cmd = io_req->sc_cmd; 1708 struct io_bdt *bd_tbl = io_req->bd_tbl; 1709 struct bnx2fc_rport *tgt = io_req->tgt; 1710 struct fcoe_cached_sge_ctx *cached_sge; 1711 struct fcoe_ext_mul_sges_ctx *sgl; 1712 int dev_type = tgt->dev_type; 1713 u64 *fcp_cmnd; 1714 u64 tmp_fcp_cmnd[4]; 1715 u32 context_id; 1716 int cnt, i; 1717 int bd_count; 1718 1719 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1720 1721 /* Setup the task from io_req for easy reference */ 1722 io_req->task = task; 1723 1724 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE) 1725 task_type = FCOE_TASK_TYPE_WRITE; 1726 else 1727 task_type = FCOE_TASK_TYPE_READ; 1728 1729 /* Tx only */ 1730 bd_count = bd_tbl->bd_valid; 1731 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge; 1732 if (task_type == FCOE_TASK_TYPE_WRITE) { 1733 if ((dev_type == TYPE_DISK) && (bd_count == 1)) { 1734 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1735 1736 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo = 1737 cached_sge->cur_buf_addr.lo = 1738 fcoe_bd_tbl->buf_addr_lo; 1739 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi = 1740 cached_sge->cur_buf_addr.hi = 1741 fcoe_bd_tbl->buf_addr_hi; 1742 task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem = 1743 cached_sge->cur_buf_rem = 1744 fcoe_bd_tbl->buf_len; 1745 1746 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1747 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1748 } else { 1749 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1750 (u32)bd_tbl->bd_tbl_dma; 1751 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1752 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1753 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1754 bd_tbl->bd_valid; 1755 } 1756 } 1757 1758 /*Tx Write Rx Read */ 1759 /* Init state to NORMAL */ 1760 task->txwr_rxrd.const_ctx.init_flags |= task_type << 1761 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1762 if (dev_type == TYPE_TAPE) { 1763 task->txwr_rxrd.const_ctx.init_flags |= 1764 FCOE_TASK_DEV_TYPE_TAPE << 1765 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1766 io_req->rec_retry = 0; 1767 io_req->rec_retry = 0; 1768 } else 1769 task->txwr_rxrd.const_ctx.init_flags |= 1770 FCOE_TASK_DEV_TYPE_DISK << 1771 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1772 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1773 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1774 /* tx flags */ 1775 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL << 1776 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1777 1778 /* Set initial seq counter */ 1779 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1; 1780 1781 /* Fill FCP_CMND IU */ 1782 fcp_cmnd = (u64 *) 1783 task->txwr_rxrd.union_ctx.fcp_cmd.opaque; 1784 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd); 1785 1786 /* swap fcp_cmnd */ 1787 cnt = sizeof(struct fcp_cmnd) / sizeof(u64); 1788 1789 for (i = 0; i < cnt; i++) { 1790 *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]); 1791 fcp_cmnd++; 1792 } 1793 1794 /* Rx Write Tx Read */ 1795 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len; 1796 1797 context_id = tgt->context_id; 1798 task->rxwr_txrd.const_ctx.init_flags = context_id << 1799 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1800 1801 /* rx flags */ 1802 /* Set state to "waiting for the first packet" */ 1803 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1804 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1805 1806 task->rxwr_txrd.var_ctx.rx_id = 0xffff; 1807 1808 /* Rx Only */ 1809 if (task_type != FCOE_TASK_TYPE_READ) 1810 return; 1811 1812 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1813 bd_count = bd_tbl->bd_valid; 1814 1815 if (dev_type == TYPE_DISK) { 1816 if (bd_count == 1) { 1817 1818 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1819 1820 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo; 1821 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi; 1822 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len; 1823 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1824 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1825 } else if (bd_count == 2) { 1826 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1827 1828 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo; 1829 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi; 1830 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len; 1831 1832 fcoe_bd_tbl++; 1833 cached_sge->second_buf_addr.lo = 1834 fcoe_bd_tbl->buf_addr_lo; 1835 cached_sge->second_buf_addr.hi = 1836 fcoe_bd_tbl->buf_addr_hi; 1837 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len; 1838 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1839 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1840 } else { 1841 1842 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma; 1843 sgl->mul_sgl.cur_sge_addr.hi = 1844 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1845 sgl->mul_sgl.sgl_size = bd_count; 1846 } 1847 } else { 1848 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma; 1849 sgl->mul_sgl.cur_sge_addr.hi = 1850 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1851 sgl->mul_sgl.sgl_size = bd_count; 1852 } 1853} 1854 1855/** 1856 * bnx2fc_setup_task_ctx - allocate and map task context 1857 * 1858 * @hba: pointer to adapter structure 1859 * 1860 * allocate memory for task context, and associated BD table to be used 1861 * by firmware 1862 * 1863 */ 1864int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba) 1865{ 1866 int rc = 0; 1867 struct regpair *task_ctx_bdt; 1868 dma_addr_t addr; 1869 int task_ctx_arr_sz; 1870 int i; 1871 1872 /* 1873 * Allocate task context bd table. A page size of bd table 1874 * can map 256 buffers. Each buffer contains 32 task context 1875 * entries. Hence the limit with one page is 8192 task context 1876 * entries. 1877 */ 1878 hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev, 1879 PAGE_SIZE, 1880 &hba->task_ctx_bd_dma, 1881 GFP_KERNEL); 1882 if (!hba->task_ctx_bd_tbl) { 1883 printk(KERN_ERR PFX "unable to allocate task context BDT\n"); 1884 rc = -1; 1885 goto out; 1886 } 1887 1888 /* 1889 * Allocate task_ctx which is an array of pointers pointing to 1890 * a page containing 32 task contexts 1891 */ 1892 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE); 1893 hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)), 1894 GFP_KERNEL); 1895 if (!hba->task_ctx) { 1896 printk(KERN_ERR PFX "unable to allocate task context array\n"); 1897 rc = -1; 1898 goto out1; 1899 } 1900 1901 /* 1902 * Allocate task_ctx_dma which is an array of dma addresses 1903 */ 1904 hba->task_ctx_dma = kmalloc((task_ctx_arr_sz * 1905 sizeof(dma_addr_t)), GFP_KERNEL); 1906 if (!hba->task_ctx_dma) { 1907 printk(KERN_ERR PFX "unable to alloc context mapping array\n"); 1908 rc = -1; 1909 goto out2; 1910 } 1911 1912 task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl; 1913 for (i = 0; i < task_ctx_arr_sz; i++) { 1914 1915 hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev, 1916 PAGE_SIZE, 1917 &hba->task_ctx_dma[i], 1918 GFP_KERNEL); 1919 if (!hba->task_ctx[i]) { 1920 printk(KERN_ERR PFX "unable to alloc task context\n"); 1921 rc = -1; 1922 goto out3; 1923 } 1924 addr = (u64)hba->task_ctx_dma[i]; 1925 task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32); 1926 task_ctx_bdt->lo = cpu_to_le32((u32)addr); 1927 task_ctx_bdt++; 1928 } 1929 return 0; 1930 1931out3: 1932 for (i = 0; i < task_ctx_arr_sz; i++) { 1933 if (hba->task_ctx[i]) { 1934 1935 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1936 hba->task_ctx[i], hba->task_ctx_dma[i]); 1937 hba->task_ctx[i] = NULL; 1938 } 1939 } 1940 1941 kfree(hba->task_ctx_dma); 1942 hba->task_ctx_dma = NULL; 1943out2: 1944 kfree(hba->task_ctx); 1945 hba->task_ctx = NULL; 1946out1: 1947 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1948 hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma); 1949 hba->task_ctx_bd_tbl = NULL; 1950out: 1951 return rc; 1952} 1953 1954void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba) 1955{ 1956 int task_ctx_arr_sz; 1957 int i; 1958 1959 if (hba->task_ctx_bd_tbl) { 1960 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1961 hba->task_ctx_bd_tbl, 1962 hba->task_ctx_bd_dma); 1963 hba->task_ctx_bd_tbl = NULL; 1964 } 1965 1966 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE); 1967 if (hba->task_ctx) { 1968 for (i = 0; i < task_ctx_arr_sz; i++) { 1969 if (hba->task_ctx[i]) { 1970 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1971 hba->task_ctx[i], 1972 hba->task_ctx_dma[i]); 1973 hba->task_ctx[i] = NULL; 1974 } 1975 } 1976 kfree(hba->task_ctx); 1977 hba->task_ctx = NULL; 1978 } 1979 1980 kfree(hba->task_ctx_dma); 1981 hba->task_ctx_dma = NULL; 1982} 1983 1984static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba) 1985{ 1986 int i; 1987 int segment_count; 1988 u32 *pbl; 1989 1990 if (hba->hash_tbl_segments) { 1991 1992 pbl = hba->hash_tbl_pbl; 1993 if (pbl) { 1994 segment_count = hba->hash_tbl_segment_count; 1995 for (i = 0; i < segment_count; ++i) { 1996 dma_addr_t dma_address; 1997 1998 dma_address = le32_to_cpu(*pbl); 1999 ++pbl; 2000 dma_address += ((u64)le32_to_cpu(*pbl)) << 32; 2001 ++pbl; 2002 dma_free_coherent(&hba->pcidev->dev, 2003 BNX2FC_HASH_TBL_CHUNK_SIZE, 2004 hba->hash_tbl_segments[i], 2005 dma_address); 2006 } 2007 } 2008 2009 kfree(hba->hash_tbl_segments); 2010 hba->hash_tbl_segments = NULL; 2011 } 2012 2013 if (hba->hash_tbl_pbl) { 2014 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 2015 hba->hash_tbl_pbl, 2016 hba->hash_tbl_pbl_dma); 2017 hba->hash_tbl_pbl = NULL; 2018 } 2019} 2020 2021static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba) 2022{ 2023 int i; 2024 int hash_table_size; 2025 int segment_count; 2026 int segment_array_size; 2027 int dma_segment_array_size; 2028 dma_addr_t *dma_segment_array; 2029 u32 *pbl; 2030 2031 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL * 2032 sizeof(struct fcoe_hash_table_entry); 2033 2034 segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1; 2035 segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE; 2036 hba->hash_tbl_segment_count = segment_count; 2037 2038 segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments); 2039 hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL); 2040 if (!hba->hash_tbl_segments) { 2041 printk(KERN_ERR PFX "hash table pointers alloc failed\n"); 2042 return -ENOMEM; 2043 } 2044 dma_segment_array_size = segment_count * sizeof(*dma_segment_array); 2045 dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL); 2046 if (!dma_segment_array) { 2047 printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n"); 2048 goto cleanup_ht; 2049 } 2050 2051 for (i = 0; i < segment_count; ++i) { 2052 hba->hash_tbl_segments[i] = dma_alloc_coherent(&hba->pcidev->dev, 2053 BNX2FC_HASH_TBL_CHUNK_SIZE, 2054 &dma_segment_array[i], 2055 GFP_KERNEL); 2056 if (!hba->hash_tbl_segments[i]) { 2057 printk(KERN_ERR PFX "hash segment alloc failed\n"); 2058 goto cleanup_dma; 2059 } 2060 } 2061 2062 hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE, 2063 &hba->hash_tbl_pbl_dma, 2064 GFP_KERNEL); 2065 if (!hba->hash_tbl_pbl) { 2066 printk(KERN_ERR PFX "hash table pbl alloc failed\n"); 2067 goto cleanup_dma; 2068 } 2069 2070 pbl = hba->hash_tbl_pbl; 2071 for (i = 0; i < segment_count; ++i) { 2072 u64 paddr = dma_segment_array[i]; 2073 *pbl = cpu_to_le32((u32) paddr); 2074 ++pbl; 2075 *pbl = cpu_to_le32((u32) (paddr >> 32)); 2076 ++pbl; 2077 } 2078 pbl = hba->hash_tbl_pbl; 2079 i = 0; 2080 while (*pbl && *(pbl + 1)) { 2081 ++pbl; 2082 ++pbl; 2083 ++i; 2084 } 2085 kfree(dma_segment_array); 2086 return 0; 2087 2088cleanup_dma: 2089 for (i = 0; i < segment_count; ++i) { 2090 if (hba->hash_tbl_segments[i]) 2091 dma_free_coherent(&hba->pcidev->dev, 2092 BNX2FC_HASH_TBL_CHUNK_SIZE, 2093 hba->hash_tbl_segments[i], 2094 dma_segment_array[i]); 2095 } 2096 2097 kfree(dma_segment_array); 2098 2099cleanup_ht: 2100 kfree(hba->hash_tbl_segments); 2101 hba->hash_tbl_segments = NULL; 2102 return -ENOMEM; 2103} 2104 2105/** 2106 * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer 2107 * 2108 * @hba: Pointer to adapter structure 2109 * 2110 */ 2111int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba) 2112{ 2113 u64 addr; 2114 u32 mem_size; 2115 int i; 2116 2117 if (bnx2fc_allocate_hash_table(hba)) 2118 return -ENOMEM; 2119 2120 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair); 2121 hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size, 2122 &hba->t2_hash_tbl_ptr_dma, 2123 GFP_KERNEL); 2124 if (!hba->t2_hash_tbl_ptr) { 2125 printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n"); 2126 bnx2fc_free_fw_resc(hba); 2127 return -ENOMEM; 2128 } 2129 2130 mem_size = BNX2FC_NUM_MAX_SESS * 2131 sizeof(struct fcoe_t2_hash_table_entry); 2132 hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size, 2133 &hba->t2_hash_tbl_dma, 2134 GFP_KERNEL); 2135 if (!hba->t2_hash_tbl) { 2136 printk(KERN_ERR PFX "unable to allocate t2 hash table\n"); 2137 bnx2fc_free_fw_resc(hba); 2138 return -ENOMEM; 2139 } 2140 for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) { 2141 addr = (unsigned long) hba->t2_hash_tbl_dma + 2142 ((i+1) * sizeof(struct fcoe_t2_hash_table_entry)); 2143 hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff; 2144 hba->t2_hash_tbl[i].next.hi = addr >> 32; 2145 } 2146 2147 hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev, 2148 PAGE_SIZE, &hba->dummy_buf_dma, 2149 GFP_KERNEL); 2150 if (!hba->dummy_buffer) { 2151 printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n"); 2152 bnx2fc_free_fw_resc(hba); 2153 return -ENOMEM; 2154 } 2155 2156 hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE, 2157 &hba->stats_buf_dma, 2158 GFP_KERNEL); 2159 if (!hba->stats_buffer) { 2160 printk(KERN_ERR PFX "unable to alloc Stats Buffer\n"); 2161 bnx2fc_free_fw_resc(hba); 2162 return -ENOMEM; 2163 } 2164 2165 return 0; 2166} 2167 2168void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba) 2169{ 2170 u32 mem_size; 2171 2172 if (hba->stats_buffer) { 2173 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 2174 hba->stats_buffer, hba->stats_buf_dma); 2175 hba->stats_buffer = NULL; 2176 } 2177 2178 if (hba->dummy_buffer) { 2179 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 2180 hba->dummy_buffer, hba->dummy_buf_dma); 2181 hba->dummy_buffer = NULL; 2182 } 2183 2184 if (hba->t2_hash_tbl_ptr) { 2185 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair); 2186 dma_free_coherent(&hba->pcidev->dev, mem_size, 2187 hba->t2_hash_tbl_ptr, 2188 hba->t2_hash_tbl_ptr_dma); 2189 hba->t2_hash_tbl_ptr = NULL; 2190 } 2191 2192 if (hba->t2_hash_tbl) { 2193 mem_size = BNX2FC_NUM_MAX_SESS * 2194 sizeof(struct fcoe_t2_hash_table_entry); 2195 dma_free_coherent(&hba->pcidev->dev, mem_size, 2196 hba->t2_hash_tbl, hba->t2_hash_tbl_dma); 2197 hba->t2_hash_tbl = NULL; 2198 } 2199 bnx2fc_free_hash_table(hba); 2200} 2201