1/* 2******************************************************************************* 3** O.S : Linux 4** FILE NAME : arcmsr.h 5** BY : Nick Cheng 6** Description: SCSI RAID Device Driver for 7** ARECA RAID Host adapter 8******************************************************************************* 9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10** 11** Web site: www.areca.com.tw 12** E-mail: support@areca.com.tw 13** 14** This program is free software; you can redistribute it and/or modify 15** it under the terms of the GNU General Public License version 2 as 16** published by the Free Software Foundation. 17** This program is distributed in the hope that it will be useful, 18** but WITHOUT ANY WARRANTY; without even the implied warranty of 19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20** GNU General Public License for more details. 21******************************************************************************* 22** Redistribution and use in source and binary forms, with or without 23** modification, are permitted provided that the following conditions 24** are met: 25** 1. Redistributions of source code must retain the above copyright 26** notice, this list of conditions and the following disclaimer. 27** 2. Redistributions in binary form must reproduce the above copyright 28** notice, this list of conditions and the following disclaimer in the 29** documentation and/or other materials provided with the distribution. 30** 3. The name of the author may not be used to endorse or promote products 31** derived from this software without specific prior written permission. 32** 33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43******************************************************************************* 44*/ 45#include <linux/interrupt.h> 46struct device_attribute; 47/*The limit of outstanding scsi command that firmware can handle*/ 48#define ARCMSR_MAX_FREECCB_NUM 1024 49#define ARCMSR_MAX_OUTSTANDING_CMD 1024 50#define ARCMSR_DEFAULT_OUTSTANDING_CMD 128 51#define ARCMSR_MIN_OUTSTANDING_CMD 32 52#define ARCMSR_DRIVER_VERSION "v1.50.00.02-20200819" 53#define ARCMSR_SCSI_INITIATOR_ID 255 54#define ARCMSR_MAX_XFER_SECTORS 512 55#define ARCMSR_MAX_XFER_SECTORS_B 4096 56#define ARCMSR_MAX_XFER_SECTORS_C 304 57#define ARCMSR_MAX_TARGETID 17 58#define ARCMSR_MAX_TARGETLUN 8 59#define ARCMSR_MAX_CMD_PERLUN 128 60#define ARCMSR_DEFAULT_CMD_PERLUN 32 61#define ARCMSR_MIN_CMD_PERLUN 1 62#define ARCMSR_MAX_QBUFFER 4096 63#define ARCMSR_DEFAULT_SG_ENTRIES 38 64#define ARCMSR_MAX_HBB_POSTQUEUE 264 65#define ARCMSR_MAX_ARC1214_POSTQUEUE 256 66#define ARCMSR_MAX_ARC1214_DONEQUEUE 257 67#define ARCMSR_MAX_HBE_DONEQUEUE 512 68#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 69#define ARCMSR_CDB_SG_PAGE_LENGTH 256 70#define ARCMST_NUM_MSIX_VECTORS 4 71#ifndef PCI_DEVICE_ID_ARECA_1880 72#define PCI_DEVICE_ID_ARECA_1880 0x1880 73#endif 74#ifndef PCI_DEVICE_ID_ARECA_1214 75#define PCI_DEVICE_ID_ARECA_1214 0x1214 76#endif 77#ifndef PCI_DEVICE_ID_ARECA_1203 78#define PCI_DEVICE_ID_ARECA_1203 0x1203 79#endif 80#ifndef PCI_DEVICE_ID_ARECA_1883 81#define PCI_DEVICE_ID_ARECA_1883 0x1883 82#endif 83#ifndef PCI_DEVICE_ID_ARECA_1884 84#define PCI_DEVICE_ID_ARECA_1884 0x1884 85#endif 86#define PCI_DEVICE_ID_ARECA_1886_0 0x1886 87#define PCI_DEVICE_ID_ARECA_1886 0x188A 88#define ARCMSR_HOURS (1000 * 60 * 60 * 4) 89#define ARCMSR_MINUTES (1000 * 60 * 60) 90/* 91********************************************************************************** 92** 93********************************************************************************** 94*/ 95#define ARC_SUCCESS 0 96#define ARC_FAILURE 1 97/* 98******************************************************************************* 99** split 64bits dma addressing 100******************************************************************************* 101*/ 102#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 103#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 104/* 105******************************************************************************* 106** MESSAGE CONTROL CODE 107******************************************************************************* 108*/ 109struct CMD_MESSAGE 110{ 111 uint32_t HeaderLength; 112 uint8_t Signature[8]; 113 uint32_t Timeout; 114 uint32_t ControlCode; 115 uint32_t ReturnCode; 116 uint32_t Length; 117}; 118/* 119******************************************************************************* 120** IOP Message Transfer Data for user space 121******************************************************************************* 122*/ 123#define ARCMSR_API_DATA_BUFLEN 1032 124struct CMD_MESSAGE_FIELD 125{ 126 struct CMD_MESSAGE cmdmessage; 127 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN]; 128}; 129/* IOP message transfer */ 130#define ARCMSR_MESSAGE_FAIL 0x0001 131/* DeviceType */ 132#define ARECA_SATA_RAID 0x90000000 133/* FunctionCode */ 134#define FUNCTION_READ_RQBUFFER 0x0801 135#define FUNCTION_WRITE_WQBUFFER 0x0802 136#define FUNCTION_CLEAR_RQBUFFER 0x0803 137#define FUNCTION_CLEAR_WQBUFFER 0x0804 138#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 139#define FUNCTION_RETURN_CODE_3F 0x0806 140#define FUNCTION_SAY_HELLO 0x0807 141#define FUNCTION_SAY_GOODBYE 0x0808 142#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 143#define FUNCTION_GET_FIRMWARE_STATUS 0x080A 144#define FUNCTION_HARDWARE_RESET 0x080B 145/* ARECA IO CONTROL CODE*/ 146#define ARCMSR_MESSAGE_READ_RQBUFFER \ 147 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 148#define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 149 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 150#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 151 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 152#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 153 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 154#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 155 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 156#define ARCMSR_MESSAGE_RETURN_CODE_3F \ 157 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 158#define ARCMSR_MESSAGE_SAY_HELLO \ 159 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 160#define ARCMSR_MESSAGE_SAY_GOODBYE \ 161 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 162#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 163 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 164/* ARECA IOCTL ReturnCode */ 165#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 166#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 167#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 168#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 169/* 170************************************************************* 171** structure for holding DMA address data 172************************************************************* 173*/ 174#define IS_DMA64 (sizeof(dma_addr_t) == 8) 175#define IS_SG64_ADDR 0x01000000 /* bit24 */ 176struct SG32ENTRY 177{ 178 __le32 length; 179 __le32 address; 180}__attribute__ ((packed)); 181struct SG64ENTRY 182{ 183 __le32 length; 184 __le32 address; 185 __le32 addresshigh; 186}__attribute__ ((packed)); 187/* 188******************************************************************** 189** Q Buffer of IOP Message Transfer 190******************************************************************** 191*/ 192struct QBUFFER 193{ 194 uint32_t data_len; 195 uint8_t data[124]; 196}; 197/* 198******************************************************************************* 199** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 200******************************************************************************* 201*/ 202struct FIRMWARE_INFO 203{ 204 uint32_t signature; /*0, 00-03*/ 205 uint32_t request_len; /*1, 04-07*/ 206 uint32_t numbers_queue; /*2, 08-11*/ 207 uint32_t sdram_size; /*3, 12-15*/ 208 uint32_t ide_channels; /*4, 16-19*/ 209 char vendor[40]; /*5, 20-59*/ 210 char model[8]; /*15, 60-67*/ 211 char firmware_ver[16]; /*17, 68-83*/ 212 char device_map[16]; /*21, 84-99*/ 213 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 214 uint8_t cfgSerial[16]; /*26,104-119*/ 215 uint32_t cfgPicStatus; /*30,120-123*/ 216}; 217/* signature of set and get firmware config */ 218#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 219#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 220/* message code of inbound message register */ 221#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 222#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 223#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 224#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 225#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 226#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 227#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 228#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 229#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 230/* doorbell interrupt generator */ 231#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 232#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 233#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 234#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 235/* ccb areca cdb flag */ 236#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 237#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 238#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 239#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 240#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 241/* outbound firmware ok */ 242#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 243/* ARC-1680 Bus Reset*/ 244#define ARCMSR_ARC1680_BUS_RESET 0x00000003 245/* ARC-1880 Bus Reset*/ 246#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024 247#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080 248 249/* 250************************************************************************ 251** SPEC. for Areca Type B adapter 252************************************************************************ 253*/ 254/* ARECA HBB COMMAND for its FIRMWARE */ 255/* window of "instruction flags" from driver to iop */ 256#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 257#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 258/* window of "instruction flags" from iop to driver */ 259#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 260#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 261/* window of "instruction flags" from iop to driver */ 262#define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 263#define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 264/* window of "instruction flags" from driver to iop */ 265#define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 266#define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 267/* ARECA FLAG LANGUAGE */ 268/* ioctl transfer */ 269#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 270/* ioctl transfer */ 271#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 272#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 273#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 274 275#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 276#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 277#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 278/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 279#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 280/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 281#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 282/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 283#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 284/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 285#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 286/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 287#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 288/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 289#define ARCMSR_MESSAGE_START_BGRB 0x00060008 290#define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008 291#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 292#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 293#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 294/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 295#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 296/* ioctl transfer */ 297#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 298/* ioctl transfer */ 299#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 300#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 301#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 302#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 303 304/* data tunnel buffer between user space program and its firmware */ 305/* user space data to iop 128bytes */ 306#define ARCMSR_MESSAGE_WBUFFER 0x0000fe00 307/* iop data to user space 128bytes */ 308#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 309/* iop message_rwbuffer for message command */ 310#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 311 312#define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x) 313#define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x) 314/* 315************************************************************************ 316** SPEC. for Areca HBC adapter 317************************************************************************ 318*/ 319#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 320#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 321/* Host Interrupt Mask */ 322#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 323#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 324#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 325#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 326/* Host Interrupt Status */ 327#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 328 /* 329 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 330 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 331 */ 332#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 333 /* 334 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 335 ** value. This bit clears only when Outbound Doorbell bits 336 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 337 ** Clear register clears bits in the Outbound Doorbell register. 338 */ 339#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 340 /* 341 ** Set whenever the Outbound Post List Producer/Consumer 342 ** Register (FIFO) is not empty. It clears when the Outbound 343 ** Post List FIFO is empty. 344 */ 345#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 346 /* 347 ** This bit indicates a SAS interrupt from a source external to 348 ** the PCIe core. This bit is not maskable. 349 */ 350 /* DoorBell*/ 351#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 352#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 353 /*inbound message 0 ready*/ 354#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 355 /*more than 12 request completed in a time*/ 356#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 357#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 358 /*outbound DATA WRITE isr door bell clear*/ 359#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 360#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 361 /*outbound DATA READ isr door bell clear*/ 362#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 363 /*outbound message 0 ready*/ 364#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 365 /*outbound message cmd isr door bell clear*/ 366#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 367 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 368#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 369/* 370******************************************************************************* 371** SPEC. for Areca Type D adapter 372******************************************************************************* 373*/ 374#define ARCMSR_ARC1214_CHIP_ID 0x00004 375#define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008 376#define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034 377#define ARCMSR_ARC1214_SAMPLE_RESET 0x00100 378#define ARCMSR_ARC1214_RESET_REQUEST 0x00108 379#define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200 380#define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C 381#define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400 382#define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404 383#define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420 384#define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424 385#define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460 386#define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480 387#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484 388#define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000 389#define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004 390#define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018 391#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060 392#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064 393#define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C 394#define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070 395#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088 396#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C 397#define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000 398#define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100 399#define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200 400/* Host Interrupt Mask */ 401#define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010 402#define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000 403/* Host Interrupt Status */ 404#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000 405#define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010 406/* DoorBell*/ 407#define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001 408#define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002 409/*inbound message 0 ready*/ 410#define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001 411/*outbound DATA WRITE isr door bell clear*/ 412#define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002 413/*outbound message 0 ready*/ 414#define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 415/*outbound message cmd isr door bell clear*/ 416/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 417#define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000 418#define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 419/* 420******************************************************************************* 421** SPEC. for Areca Type E adapter 422******************************************************************************* 423*/ 424#define ARCMSR_SIGNATURE_1884 0x188417D3 425 426#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 427#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 428#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 429 430#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 431#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 432#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 433 434#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 435 436#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 437#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 438#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 439 440/* ARC-1884 doorbell sync */ 441#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 442#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 443#define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080 444 445/* 446******************************************************************************* 447** SPEC. for Areca Type F adapter 448******************************************************************************* 449*/ 450#define ARCMSR_SIGNATURE_1886 0x188617D3 451// Doorbell and interrupt definition are same as Type E adapter 452/* ARC-1886 doorbell sync */ 453#define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 454//set host rw buffer physical address at inbound message 0, 1 (low,high) 455#define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 456#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 457#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 458 459/* 460******************************************************************************* 461** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 462******************************************************************************* 463*/ 464struct ARCMSR_CDB 465{ 466 uint8_t Bus; 467 uint8_t TargetID; 468 uint8_t LUN; 469 uint8_t Function; 470 uint8_t CdbLength; 471 uint8_t sgcount; 472 uint8_t Flags; 473#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 474#define ARCMSR_CDB_FLAG_BIOS 0x02 475#define ARCMSR_CDB_FLAG_WRITE 0x04 476#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 477#define ARCMSR_CDB_FLAG_HEADQ 0x08 478#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 479 480 uint8_t msgPages; 481 uint32_t msgContext; 482 uint32_t DataLength; 483 uint8_t Cdb[16]; 484 uint8_t DeviceStatus; 485#define ARCMSR_DEV_CHECK_CONDITION 0x02 486#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 487#define ARCMSR_DEV_ABORTED 0xF1 488#define ARCMSR_DEV_INIT_FAIL 0xF2 489 490 uint8_t SenseData[15]; 491 union 492 { 493 struct SG32ENTRY sg32entry[1]; 494 struct SG64ENTRY sg64entry[1]; 495 } u; 496}; 497/* 498******************************************************************************* 499** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 500******************************************************************************* 501*/ 502struct MessageUnit_A 503{ 504 uint32_t resrved0[4]; /*0000 000F*/ 505 uint32_t inbound_msgaddr0; /*0010 0013*/ 506 uint32_t inbound_msgaddr1; /*0014 0017*/ 507 uint32_t outbound_msgaddr0; /*0018 001B*/ 508 uint32_t outbound_msgaddr1; /*001C 001F*/ 509 uint32_t inbound_doorbell; /*0020 0023*/ 510 uint32_t inbound_intstatus; /*0024 0027*/ 511 uint32_t inbound_intmask; /*0028 002B*/ 512 uint32_t outbound_doorbell; /*002C 002F*/ 513 uint32_t outbound_intstatus; /*0030 0033*/ 514 uint32_t outbound_intmask; /*0034 0037*/ 515 uint32_t reserved1[2]; /*0038 003F*/ 516 uint32_t inbound_queueport; /*0040 0043*/ 517 uint32_t outbound_queueport; /*0044 0047*/ 518 uint32_t reserved2[2]; /*0048 004F*/ 519 uint32_t reserved3[492]; /*0050 07FF 492*/ 520 uint32_t reserved4[128]; /*0800 09FF 128*/ 521 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 522 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 523 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 524 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 525 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 526}; 527 528struct MessageUnit_B 529{ 530 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 531 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 532 uint32_t postq_index; 533 uint32_t doneq_index; 534 uint32_t __iomem *drv2iop_doorbell; 535 uint32_t __iomem *drv2iop_doorbell_mask; 536 uint32_t __iomem *iop2drv_doorbell; 537 uint32_t __iomem *iop2drv_doorbell_mask; 538 uint32_t __iomem *message_rwbuffer; 539 uint32_t __iomem *message_wbuffer; 540 uint32_t __iomem *message_rbuffer; 541}; 542/* 543********************************************************************* 544** LSI 545********************************************************************* 546*/ 547struct MessageUnit_C{ 548 uint32_t message_unit_status; /*0000 0003*/ 549 uint32_t slave_error_attribute; /*0004 0007*/ 550 uint32_t slave_error_address; /*0008 000B*/ 551 uint32_t posted_outbound_doorbell; /*000C 000F*/ 552 uint32_t master_error_attribute; /*0010 0013*/ 553 uint32_t master_error_address_low; /*0014 0017*/ 554 uint32_t master_error_address_high; /*0018 001B*/ 555 uint32_t hcb_size; /*001C 001F*/ 556 uint32_t inbound_doorbell; /*0020 0023*/ 557 uint32_t diagnostic_rw_data; /*0024 0027*/ 558 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 559 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 560 uint32_t host_int_status; /*0030 0033*/ 561 uint32_t host_int_mask; /*0034 0037*/ 562 uint32_t dcr_data; /*0038 003B*/ 563 uint32_t dcr_address; /*003C 003F*/ 564 uint32_t inbound_queueport; /*0040 0043*/ 565 uint32_t outbound_queueport; /*0044 0047*/ 566 uint32_t hcb_pci_address_low; /*0048 004B*/ 567 uint32_t hcb_pci_address_high; /*004C 004F*/ 568 uint32_t iop_int_status; /*0050 0053*/ 569 uint32_t iop_int_mask; /*0054 0057*/ 570 uint32_t iop_inbound_queue_port; /*0058 005B*/ 571 uint32_t iop_outbound_queue_port; /*005C 005F*/ 572 uint32_t inbound_free_list_index; /*0060 0063*/ 573 uint32_t inbound_post_list_index; /*0064 0067*/ 574 uint32_t outbound_free_list_index; /*0068 006B*/ 575 uint32_t outbound_post_list_index; /*006C 006F*/ 576 uint32_t inbound_doorbell_clear; /*0070 0073*/ 577 uint32_t i2o_message_unit_control; /*0074 0077*/ 578 uint32_t last_used_message_source_address_low; /*0078 007B*/ 579 uint32_t last_used_message_source_address_high; /*007C 007F*/ 580 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 581 uint32_t message_dest_address_index; /*0090 0093*/ 582 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 583 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 584 uint32_t outbound_doorbell; /*009C 009F*/ 585 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 586 uint32_t message_source_address_index; /*00A4 00A7*/ 587 uint32_t message_done_queue_index; /*00A8 00AB*/ 588 uint32_t reserved0; /*00AC 00AF*/ 589 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 590 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 591 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 592 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 593 uint32_t inbound_queueport_low; /*00C0 00C3*/ 594 uint32_t inbound_queueport_high; /*00C4 00C7*/ 595 uint32_t outbound_queueport_low; /*00C8 00CB*/ 596 uint32_t outbound_queueport_high; /*00CC 00CF*/ 597 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 598 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 599 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 600 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 601 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 602 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 603 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 604 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 605 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 606 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 607 uint32_t host_diagnostic; /*00F8 00FB*/ 608 uint32_t write_sequence; /*00FC 00FF*/ 609 uint32_t reserved1[34]; /*0100 0187*/ 610 uint32_t reserved2[1950]; /*0188 1FFF*/ 611 uint32_t message_wbuffer[32]; /*2000 207F*/ 612 uint32_t reserved3[32]; /*2080 20FF*/ 613 uint32_t message_rbuffer[32]; /*2100 217F*/ 614 uint32_t reserved4[32]; /*2180 21FF*/ 615 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 616}; 617/* 618********************************************************************* 619** Messaging Unit (MU) of Type D processor 620********************************************************************* 621*/ 622struct InBound_SRB { 623 uint32_t addressLow; /* pointer to SRB block */ 624 uint32_t addressHigh; 625 uint32_t length; /* in DWORDs */ 626 uint32_t reserved0; 627}; 628 629struct OutBound_SRB { 630 uint32_t addressLow; /* pointer to SRB block */ 631 uint32_t addressHigh; 632}; 633 634struct MessageUnit_D { 635 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE]; 636 volatile struct OutBound_SRB 637 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE]; 638 u16 postq_index; 639 volatile u16 doneq_index; 640 u32 __iomem *chip_id; /* 0x00004 */ 641 u32 __iomem *cpu_mem_config; /* 0x00008 */ 642 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */ 643 u32 __iomem *sample_at_reset; /* 0x00100 */ 644 u32 __iomem *reset_request; /* 0x00108 */ 645 u32 __iomem *host_int_status; /* 0x00200 */ 646 u32 __iomem *pcief0_int_enable; /* 0x0020C */ 647 u32 __iomem *inbound_msgaddr0; /* 0x00400 */ 648 u32 __iomem *inbound_msgaddr1; /* 0x00404 */ 649 u32 __iomem *outbound_msgaddr0; /* 0x00420 */ 650 u32 __iomem *outbound_msgaddr1; /* 0x00424 */ 651 u32 __iomem *inbound_doorbell; /* 0x00460 */ 652 u32 __iomem *outbound_doorbell; /* 0x00480 */ 653 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */ 654 u32 __iomem *inboundlist_base_low; /* 0x01000 */ 655 u32 __iomem *inboundlist_base_high; /* 0x01004 */ 656 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */ 657 u32 __iomem *outboundlist_base_low; /* 0x01060 */ 658 u32 __iomem *outboundlist_base_high; /* 0x01064 */ 659 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */ 660 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */ 661 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */ 662 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */ 663 u32 __iomem *message_wbuffer; /* 0x2000 */ 664 u32 __iomem *message_rbuffer; /* 0x2100 */ 665 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */ 666}; 667/* 668********************************************************************* 669** Messaging Unit (MU) of Type E processor(LSI) 670********************************************************************* 671*/ 672struct MessageUnit_E{ 673 uint32_t iobound_doorbell; /*0000 0003*/ 674 uint32_t write_sequence_3xxx; /*0004 0007*/ 675 uint32_t host_diagnostic_3xxx; /*0008 000B*/ 676 uint32_t posted_outbound_doorbell; /*000C 000F*/ 677 uint32_t master_error_attribute; /*0010 0013*/ 678 uint32_t master_error_address_low; /*0014 0017*/ 679 uint32_t master_error_address_high; /*0018 001B*/ 680 uint32_t hcb_size; /*001C 001F*/ 681 uint32_t inbound_doorbell; /*0020 0023*/ 682 uint32_t diagnostic_rw_data; /*0024 0027*/ 683 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 684 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 685 uint32_t host_int_status; /*0030 0033*/ 686 uint32_t host_int_mask; /*0034 0037*/ 687 uint32_t dcr_data; /*0038 003B*/ 688 uint32_t dcr_address; /*003C 003F*/ 689 uint32_t inbound_queueport; /*0040 0043*/ 690 uint32_t outbound_queueport; /*0044 0047*/ 691 uint32_t hcb_pci_address_low; /*0048 004B*/ 692 uint32_t hcb_pci_address_high; /*004C 004F*/ 693 uint32_t iop_int_status; /*0050 0053*/ 694 uint32_t iop_int_mask; /*0054 0057*/ 695 uint32_t iop_inbound_queue_port; /*0058 005B*/ 696 uint32_t iop_outbound_queue_port; /*005C 005F*/ 697 uint32_t inbound_free_list_index; /*0060 0063*/ 698 uint32_t inbound_post_list_index; /*0064 0067*/ 699 uint32_t reply_post_producer_index; /*0068 006B*/ 700 uint32_t reply_post_consumer_index; /*006C 006F*/ 701 uint32_t inbound_doorbell_clear; /*0070 0073*/ 702 uint32_t i2o_message_unit_control; /*0074 0077*/ 703 uint32_t last_used_message_source_address_low; /*0078 007B*/ 704 uint32_t last_used_message_source_address_high; /*007C 007F*/ 705 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 706 uint32_t message_dest_address_index; /*0090 0093*/ 707 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 708 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 709 uint32_t outbound_doorbell; /*009C 009F*/ 710 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 711 uint32_t message_source_address_index; /*00A4 00A7*/ 712 uint32_t message_done_queue_index; /*00A8 00AB*/ 713 uint32_t reserved0; /*00AC 00AF*/ 714 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 715 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 716 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 717 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 718 uint32_t inbound_queueport_low; /*00C0 00C3*/ 719 uint32_t inbound_queueport_high; /*00C4 00C7*/ 720 uint32_t outbound_queueport_low; /*00C8 00CB*/ 721 uint32_t outbound_queueport_high; /*00CC 00CF*/ 722 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 723 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 724 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 725 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 726 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 727 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 728 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 729 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 730 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 731 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 732 uint32_t host_diagnostic; /*00F8 00FB*/ 733 uint32_t write_sequence; /*00FC 00FF*/ 734 uint32_t reserved1[34]; /*0100 0187*/ 735 uint32_t reserved2[1950]; /*0188 1FFF*/ 736 uint32_t message_wbuffer[32]; /*2000 207F*/ 737 uint32_t reserved3[32]; /*2080 20FF*/ 738 uint32_t message_rbuffer[32]; /*2100 217F*/ 739 uint32_t reserved4[32]; /*2180 21FF*/ 740 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 741}; 742 743/* 744********************************************************************* 745** Messaging Unit (MU) of Type F processor(LSI) 746********************************************************************* 747*/ 748struct MessageUnit_F { 749 uint32_t iobound_doorbell; /*0000 0003*/ 750 uint32_t write_sequence_3xxx; /*0004 0007*/ 751 uint32_t host_diagnostic_3xxx; /*0008 000B*/ 752 uint32_t posted_outbound_doorbell; /*000C 000F*/ 753 uint32_t master_error_attribute; /*0010 0013*/ 754 uint32_t master_error_address_low; /*0014 0017*/ 755 uint32_t master_error_address_high; /*0018 001B*/ 756 uint32_t hcb_size; /*001C 001F*/ 757 uint32_t inbound_doorbell; /*0020 0023*/ 758 uint32_t diagnostic_rw_data; /*0024 0027*/ 759 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 760 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 761 uint32_t host_int_status; /*0030 0033*/ 762 uint32_t host_int_mask; /*0034 0037*/ 763 uint32_t dcr_data; /*0038 003B*/ 764 uint32_t dcr_address; /*003C 003F*/ 765 uint32_t inbound_queueport; /*0040 0043*/ 766 uint32_t outbound_queueport; /*0044 0047*/ 767 uint32_t hcb_pci_address_low; /*0048 004B*/ 768 uint32_t hcb_pci_address_high; /*004C 004F*/ 769 uint32_t iop_int_status; /*0050 0053*/ 770 uint32_t iop_int_mask; /*0054 0057*/ 771 uint32_t iop_inbound_queue_port; /*0058 005B*/ 772 uint32_t iop_outbound_queue_port; /*005C 005F*/ 773 uint32_t inbound_free_list_index; /*0060 0063*/ 774 uint32_t inbound_post_list_index; /*0064 0067*/ 775 uint32_t reply_post_producer_index; /*0068 006B*/ 776 uint32_t reply_post_consumer_index; /*006C 006F*/ 777 uint32_t inbound_doorbell_clear; /*0070 0073*/ 778 uint32_t i2o_message_unit_control; /*0074 0077*/ 779 uint32_t last_used_message_source_address_low; /*0078 007B*/ 780 uint32_t last_used_message_source_address_high; /*007C 007F*/ 781 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 782 uint32_t message_dest_address_index; /*0090 0093*/ 783 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 784 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 785 uint32_t outbound_doorbell; /*009C 009F*/ 786 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 787 uint32_t message_source_address_index; /*00A4 00A7*/ 788 uint32_t message_done_queue_index; /*00A8 00AB*/ 789 uint32_t reserved0; /*00AC 00AF*/ 790 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 791 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 792 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 793 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 794 uint32_t inbound_queueport_low; /*00C0 00C3*/ 795 uint32_t inbound_queueport_high; /*00C4 00C7*/ 796 uint32_t outbound_queueport_low; /*00C8 00CB*/ 797 uint32_t outbound_queueport_high; /*00CC 00CF*/ 798 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 799 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 800 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 801 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 802 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 803 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 804 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 805 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 806 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 807 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 808 uint32_t host_diagnostic; /*00F8 00FB*/ 809 uint32_t write_sequence; /*00FC 00FF*/ 810 uint32_t reserved1[46]; /*0100 01B7*/ 811 uint32_t reply_post_producer_index1; /*01B8 01BB*/ 812 uint32_t reply_post_consumer_index1; /*01BC 01BF*/ 813}; 814 815#define MESG_RW_BUFFER_SIZE (256 * 3) 816 817typedef struct deliver_completeQ { 818 uint16_t cmdFlag; 819 uint16_t cmdSMID; 820 uint16_t cmdLMID; // reserved (0) 821 uint16_t cmdFlag2; // reserved (0) 822} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 823/* 824******************************************************************************* 825** Adapter Control Block 826******************************************************************************* 827*/ 828struct AdapterControlBlock 829{ 830 uint32_t adapter_type; /* adapter A,B..... */ 831#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 832#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 833#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 834#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 835#define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */ 836#define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */ 837 u32 ioqueue_size; 838 struct pci_dev * pdev; 839 struct Scsi_Host * host; 840 unsigned long vir2phy_offset; 841 /* Offset is used in making arc cdb physical to virtual calculations */ 842 uint32_t outbound_int_enable; 843 uint32_t cdb_phyaddr_hi32; 844 uint32_t reg_mu_acc_handle0; 845 uint64_t cdb_phyadd_hipart; 846 spinlock_t eh_lock; 847 spinlock_t ccblist_lock; 848 spinlock_t postq_lock; 849 spinlock_t doneq_lock; 850 spinlock_t rqbuffer_lock; 851 spinlock_t wqbuffer_lock; 852 union { 853 struct MessageUnit_A __iomem *pmuA; 854 struct MessageUnit_B *pmuB; 855 struct MessageUnit_C __iomem *pmuC; 856 struct MessageUnit_D *pmuD; 857 struct MessageUnit_E __iomem *pmuE; 858 struct MessageUnit_F __iomem *pmuF; 859 }; 860 /* message unit ATU inbound base address0 */ 861 void __iomem *mem_base0; 862 void __iomem *mem_base1; 863 //0x000 - COMPORT_IN (Host sent to ROC) 864 uint32_t *message_wbuffer; 865 //0x100 - COMPORT_OUT (ROC sent to Host) 866 uint32_t *message_rbuffer; 867 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 868 uint32_t acb_flags; 869 u16 dev_id; 870 uint8_t adapter_index; 871#define ACB_F_SCSISTOPADAPTER 0x0001 872#define ACB_F_MSG_STOP_BGRB 0x0002 873/* stop RAID background rebuild */ 874#define ACB_F_MSG_START_BGRB 0x0004 875/* stop RAID background rebuild */ 876#define ACB_F_IOPDATA_OVERFLOW 0x0008 877/* iop message data rqbuffer overflow */ 878#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 879/* message clear wqbuffer */ 880#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 881/* message clear rqbuffer */ 882#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 883#define ACB_F_BUS_RESET 0x0080 884 885#define ACB_F_IOP_INITED 0x0100 886/* iop init */ 887#define ACB_F_ABORT 0x0200 888#define ACB_F_FIRMWARE_TRAP 0x0400 889#define ACB_F_ADAPTER_REMOVED 0x0800 890#define ACB_F_MSG_GET_CONFIG 0x1000 891 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 892 /* used for memory free */ 893 struct list_head ccb_free_list; 894 /* head of free ccb list */ 895 896 atomic_t ccboutstandingcount; 897 /*The present outstanding command number that in the IOP that 898 waiting for being handled by FW*/ 899 900 void * dma_coherent; 901 /* dma_coherent used for memory free */ 902 dma_addr_t dma_coherent_handle; 903 /* dma_coherent_handle used for memory free */ 904 dma_addr_t dma_coherent_handle2; 905 void *dma_coherent2; 906 unsigned int uncache_size; 907 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 908 /* data collection buffer for read from 80331 */ 909 int32_t rqbuf_getIndex; 910 /* first of read buffer */ 911 int32_t rqbuf_putIndex; 912 /* last of read buffer */ 913 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 914 /* data collection buffer for write to 80331 */ 915 int32_t wqbuf_getIndex; 916 /* first of write buffer */ 917 int32_t wqbuf_putIndex; 918 /* last of write buffer */ 919 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 920 /* id0 ..... id15, lun0...lun7 */ 921#define ARECA_RAID_GONE 0x55 922#define ARECA_RAID_GOOD 0xaa 923 uint32_t num_resets; 924 uint32_t num_aborts; 925 uint32_t signature; 926 uint32_t firm_request_len; 927 uint32_t firm_numbers_queue; 928 uint32_t firm_sdram_size; 929 uint32_t firm_hd_channels; 930 uint32_t firm_cfg_version; 931 char firm_model[12]; 932 char firm_version[20]; 933 char device_map[20]; /*21,84-99*/ 934 struct work_struct arcmsr_do_message_isr_bh; 935 struct timer_list eternal_timer; 936 unsigned short fw_flag; 937#define FW_NORMAL 0x0000 938#define FW_BOG 0x0001 939#define FW_DEADLOCK 0x0010 940 uint32_t maxOutstanding; 941 int vector_count; 942 uint32_t maxFreeCCB; 943 struct timer_list refresh_timer; 944 uint32_t doneq_index; 945 uint32_t ccbsize; 946 uint32_t in_doorbell; 947 uint32_t out_doorbell; 948 uint32_t completionQ_entry; 949 pCompletion_Q pCompletionQ; 950 uint32_t completeQ_size; 951};/* HW_DEVICE_EXTENSION */ 952/* 953******************************************************************************* 954** Command Control Block 955** this CCB length must be 32 bytes boundary 956******************************************************************************* 957*/ 958struct CommandControlBlock{ 959 /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 960 struct list_head list; /*x32: 8byte, x64: 16byte*/ 961 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 962 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 963 unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/ 964 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ 965 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 966#define CCB_FLAG_READ 0x0000 967#define CCB_FLAG_WRITE 0x0001 968#define CCB_FLAG_ERROR 0x0002 969#define CCB_FLAG_FLUSHCACHE 0x0004 970#define CCB_FLAG_MASTER_ABORTED 0x0008 971 uint16_t startdone; /*x32:2byte,x32:2byte*/ 972#define ARCMSR_CCB_DONE 0x0000 973#define ARCMSR_CCB_START 0x55AA 974#define ARCMSR_CCB_ABORTED 0xAA55 975#define ARCMSR_CCB_ILLEGAL 0xFFFF 976 uint32_t smid; 977#if BITS_PER_LONG == 64 978 /* ======================512+64 bytes======================== */ 979 uint32_t reserved[3]; /*12 byte*/ 980#else 981 /* ======================512+32 bytes======================== */ 982 uint32_t reserved[8]; /*32 byte*/ 983#endif 984 /* ======================================================= */ 985 struct ARCMSR_CDB arcmsr_cdb; 986}; 987/* 988******************************************************************************* 989** ARECA SCSI sense data 990******************************************************************************* 991*/ 992struct SENSE_DATA 993{ 994 uint8_t ErrorCode:7; 995#define SCSI_SENSE_CURRENT_ERRORS 0x70 996#define SCSI_SENSE_DEFERRED_ERRORS 0x71 997 uint8_t Valid:1; 998 uint8_t SegmentNumber; 999 uint8_t SenseKey:4; 1000 uint8_t Reserved:1; 1001 uint8_t IncorrectLength:1; 1002 uint8_t EndOfMedia:1; 1003 uint8_t FileMark:1; 1004 uint8_t Information[4]; 1005 uint8_t AdditionalSenseLength; 1006 uint8_t CommandSpecificInformation[4]; 1007 uint8_t AdditionalSenseCode; 1008 uint8_t AdditionalSenseCodeQualifier; 1009 uint8_t FieldReplaceableUnitCode; 1010 uint8_t SenseKeySpecific[3]; 1011}; 1012/* 1013******************************************************************************* 1014** Outbound Interrupt Status Register - OISR 1015******************************************************************************* 1016*/ 1017#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 1018#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 1019#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 1020#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 1021#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 1022#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 1023#define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 1024 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 1025 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 1026 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 1027 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 1028 |ARCMSR_MU_OUTBOUND_PCI_INT) 1029/* 1030******************************************************************************* 1031** Outbound Interrupt Mask Register - OIMR 1032******************************************************************************* 1033*/ 1034#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 1035#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 1036#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 1037#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 1038#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 1039#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 1040#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 1041 1042extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *); 1043extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *, 1044 struct QBUFFER __iomem *); 1045extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *); 1046extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 1047extern struct device_attribute *arcmsr_host_attrs[]; 1048extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 1049void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 1050