1/* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $ 42 */ 43 44#include "aic79xx_osm.h" 45#include "aic79xx_inline.h" 46#include "aic79xx_pci.h" 47 48static inline uint64_t 49ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 50{ 51 uint64_t id; 52 53 id = subvendor 54 | (subdevice << 16) 55 | ((uint64_t)vendor << 32) 56 | ((uint64_t)device << 48); 57 58 return (id); 59} 60 61#define ID_AIC7902_PCI_REV_A4 0x3 62#define ID_AIC7902_PCI_REV_B0 0x10 63#define SUBID_HP 0x0E11 64 65#define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 66 67#define DEVID_9005_TYPE(id) ((id) & 0xF) 68#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 69#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 70#define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 71#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 72 73#define DEVID_9005_MFUNC(id) ((id) & 0x10) 74 75#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 76 77#define SUBID_9005_TYPE(id) ((id) & 0xF) 78#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 79#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 80 81#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 82 83#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 84 85#define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6) 86#define SUBID_9005_SEEPTYPE_NONE 0x0 87#define SUBID_9005_SEEPTYPE_4K 0x1 88 89static ahd_device_setup_t ahd_aic7901_setup; 90static ahd_device_setup_t ahd_aic7901A_setup; 91static ahd_device_setup_t ahd_aic7902_setup; 92static ahd_device_setup_t ahd_aic790X_setup; 93 94static const struct ahd_pci_identity ahd_pci_ident_table[] = 95{ 96 /* aic7901 based controllers */ 97 { 98 ID_AHA_29320A, 99 ID_ALL_MASK, 100 "Adaptec 29320A Ultra320 SCSI adapter", 101 ahd_aic7901_setup 102 }, 103 { 104 ID_AHA_29320ALP, 105 ID_ALL_MASK, 106 "Adaptec 29320ALP PCIx Ultra320 SCSI adapter", 107 ahd_aic7901_setup 108 }, 109 { 110 ID_AHA_29320LPE, 111 ID_ALL_MASK, 112 "Adaptec 29320LPE PCIe Ultra320 SCSI adapter", 113 ahd_aic7901_setup 114 }, 115 /* aic7901A based controllers */ 116 { 117 ID_AHA_29320LP, 118 ID_ALL_MASK, 119 "Adaptec 29320LP Ultra320 SCSI adapter", 120 ahd_aic7901A_setup 121 }, 122 /* aic7902 based controllers */ 123 { 124 ID_AHA_29320, 125 ID_ALL_MASK, 126 "Adaptec 29320 Ultra320 SCSI adapter", 127 ahd_aic7902_setup 128 }, 129 { 130 ID_AHA_29320B, 131 ID_ALL_MASK, 132 "Adaptec 29320B Ultra320 SCSI adapter", 133 ahd_aic7902_setup 134 }, 135 { 136 ID_AHA_39320, 137 ID_ALL_MASK, 138 "Adaptec 39320 Ultra320 SCSI adapter", 139 ahd_aic7902_setup 140 }, 141 { 142 ID_AHA_39320_B, 143 ID_ALL_MASK, 144 "Adaptec 39320 Ultra320 SCSI adapter", 145 ahd_aic7902_setup 146 }, 147 { 148 ID_AHA_39320_B_DELL, 149 ID_ALL_MASK, 150 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 151 ahd_aic7902_setup 152 }, 153 { 154 ID_AHA_39320A, 155 ID_ALL_MASK, 156 "Adaptec 39320A Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320D, 161 ID_ALL_MASK, 162 "Adaptec 39320D Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320D_HP, 167 ID_ALL_MASK, 168 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320D_B, 173 ID_ALL_MASK, 174 "Adaptec 39320D Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D_B_HP, 179 ID_ALL_MASK, 180 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 /* Generic chip probes for devices we don't know 'exactly' */ 184 { 185 ID_AIC7901 & ID_9005_GENERIC_MASK, 186 ID_9005_GENERIC_MASK, 187 "Adaptec AIC7901 Ultra320 SCSI adapter", 188 ahd_aic7901_setup 189 }, 190 { 191 ID_AIC7901A & ID_DEV_VENDOR_MASK, 192 ID_DEV_VENDOR_MASK, 193 "Adaptec AIC7901A Ultra320 SCSI adapter", 194 ahd_aic7901A_setup 195 }, 196 { 197 ID_AIC7902 & ID_9005_GENERIC_MASK, 198 ID_9005_GENERIC_MASK, 199 "Adaptec AIC7902 Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 } 202}; 203 204static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table); 205 206#define DEVCONFIG 0x40 207#define PCIXINITPAT 0x0000E000ul 208#define PCIXINIT_PCI33_66 0x0000E000ul 209#define PCIXINIT_PCIX50_66 0x0000C000ul 210#define PCIXINIT_PCIX66_100 0x0000A000ul 211#define PCIXINIT_PCIX100_133 0x00008000ul 212#define PCI_BUS_MODES_INDEX(devconfig) \ 213 (((devconfig) & PCIXINITPAT) >> 13) 214static const char *pci_bus_modes[] = 215{ 216 "PCI bus mode unknown", 217 "PCI bus mode unknown", 218 "PCI bus mode unknown", 219 "PCI bus mode unknown", 220 "PCI-X 101-133MHz", 221 "PCI-X 67-100MHz", 222 "PCI-X 50-66MHz", 223 "PCI 33 or 66MHz" 224}; 225 226#define TESTMODE 0x00000800ul 227#define IRDY_RST 0x00000200ul 228#define FRAME_RST 0x00000100ul 229#define PCI64BIT 0x00000080ul 230#define MRDCEN 0x00000040ul 231#define ENDIANSEL 0x00000020ul 232#define MIXQWENDIANEN 0x00000008ul 233#define DACEN 0x00000004ul 234#define STPWLEVEL 0x00000002ul 235#define QWENDIANSEL 0x00000001ul 236 237#define DEVCONFIG1 0x44 238#define PREQDIS 0x01 239 240#define CSIZE_LATTIME 0x0c 241#define CACHESIZE 0x000000fful 242#define LATTIME 0x0000ff00ul 243 244static int ahd_check_extport(struct ahd_softc *ahd); 245static void ahd_configure_termination(struct ahd_softc *ahd, 246 u_int adapter_control); 247static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 248static void ahd_pci_intr(struct ahd_softc *ahd); 249 250const struct ahd_pci_identity * 251ahd_find_pci_device(ahd_dev_softc_t pci) 252{ 253 uint64_t full_id; 254 uint16_t device; 255 uint16_t vendor; 256 uint16_t subdevice; 257 uint16_t subvendor; 258 const struct ahd_pci_identity *entry; 259 u_int i; 260 261 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 262 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 263 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 264 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 265 full_id = ahd_compose_id(device, 266 vendor, 267 subdevice, 268 subvendor); 269 270 /* 271 * Controllers, mask out the IROC/HostRAID bit 272 */ 273 274 full_id &= ID_ALL_IROC_MASK; 275 276 for (i = 0; i < ahd_num_pci_devs; i++) { 277 entry = &ahd_pci_ident_table[i]; 278 if (entry->full_id == (full_id & entry->id_mask)) { 279 /* Honor exclusion entries. */ 280 if (entry->name == NULL) 281 return (NULL); 282 return (entry); 283 } 284 } 285 return (NULL); 286} 287 288int 289ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry) 290{ 291 u_int command; 292 uint32_t devconfig; 293 uint16_t subvendor; 294 int error; 295 296 ahd->description = entry->name; 297 /* 298 * Record if this is an HP board. 299 */ 300 subvendor = ahd_pci_read_config(ahd->dev_softc, 301 PCIR_SUBVEND_0, /*bytes*/2); 302 if (subvendor == SUBID_HP) 303 ahd->flags |= AHD_HP_BOARD; 304 305 error = entry->setup(ahd); 306 if (error != 0) 307 return (error); 308 309 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 310 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 311 ahd->chip |= AHD_PCI; 312 /* Disable PCIX workarounds when running in PCI mode. */ 313 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 314 } else { 315 ahd->chip |= AHD_PCIX; 316 } 317 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 318 319 ahd_power_state_change(ahd, AHD_POWER_STATE_D0); 320 321 error = ahd_pci_map_registers(ahd); 322 if (error != 0) 323 return (error); 324 325 /* 326 * If we need to support high memory, enable dual 327 * address cycles. This bit must be set to enable 328 * high address bit generation even if we are on a 329 * 64bit bus (PCI64BIT set in devconfig). 330 */ 331 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 332 if (bootverbose) 333 printk("%s: Enabling 39Bit Addressing\n", 334 ahd_name(ahd)); 335 devconfig = ahd_pci_read_config(ahd->dev_softc, 336 DEVCONFIG, /*bytes*/4); 337 devconfig |= DACEN; 338 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 339 devconfig, /*bytes*/4); 340 } 341 342 /* Ensure busmastering is enabled */ 343 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 344 command |= PCIM_CMD_BUSMASTEREN; 345 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 346 347 error = ahd_softc_init(ahd); 348 if (error != 0) 349 return (error); 350 351 ahd->bus_intr = ahd_pci_intr; 352 353 error = ahd_reset(ahd, /*reinit*/FALSE); 354 if (error != 0) 355 return (ENXIO); 356 357 ahd->pci_cachesize = 358 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 359 /*bytes*/1) & CACHESIZE; 360 ahd->pci_cachesize *= 4; 361 362 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 363 /* See if we have a SEEPROM and perform auto-term */ 364 error = ahd_check_extport(ahd); 365 if (error != 0) 366 return (error); 367 368 /* Core initialization */ 369 error = ahd_init(ahd); 370 if (error != 0) 371 return (error); 372 ahd->init_level++; 373 374 /* 375 * Allow interrupts now that we are completely setup. 376 */ 377 return ahd_pci_map_int(ahd); 378} 379 380#ifdef CONFIG_PM 381void 382ahd_pci_suspend(struct ahd_softc *ahd) 383{ 384 /* 385 * Save chip register configuration data for chip resets 386 * that occur during runtime and resume events. 387 */ 388 ahd->suspend_state.pci_state.devconfig = 389 ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 390 ahd->suspend_state.pci_state.command = 391 ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 392 ahd->suspend_state.pci_state.csize_lattime = 393 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1); 394 395} 396 397void 398ahd_pci_resume(struct ahd_softc *ahd) 399{ 400 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 401 ahd->suspend_state.pci_state.devconfig, /*bytes*/4); 402 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 403 ahd->suspend_state.pci_state.command, /*bytes*/1); 404 ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME, 405 ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1); 406} 407#endif 408 409/* 410 * Perform some simple tests that should catch situations where 411 * our registers are invalidly mapped. 412 */ 413int 414ahd_pci_test_register_access(struct ahd_softc *ahd) 415{ 416 uint32_t cmd; 417 u_int targpcistat; 418 u_int pci_status1; 419 int error; 420 uint8_t hcntrl; 421 422 error = EIO; 423 424 /* 425 * Enable PCI error interrupt status, but suppress NMIs 426 * generated by SERR raised due to target aborts. 427 */ 428 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 429 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 430 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 431 432 /* 433 * First a simple test to see if any 434 * registers can be read. Reading 435 * HCNTRL has no side effects and has 436 * at least one bit that is guaranteed to 437 * be zero so it is a good register to 438 * use for this test. 439 */ 440 hcntrl = ahd_inb(ahd, HCNTRL); 441 if (hcntrl == 0xFF) 442 goto fail; 443 444 /* 445 * Next create a situation where write combining 446 * or read prefetching could be initiated by the 447 * CPU or host bridge. Our device does not support 448 * either, so look for data corruption and/or flaged 449 * PCI errors. First pause without causing another 450 * chip reset. 451 */ 452 hcntrl &= ~CHIPRST; 453 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 454 while (ahd_is_paused(ahd) == 0) 455 ; 456 457 /* Clear any PCI errors that occurred before our driver attached. */ 458 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 459 targpcistat = ahd_inb(ahd, TARGPCISTAT); 460 ahd_outb(ahd, TARGPCISTAT, targpcistat); 461 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 462 PCIR_STATUS + 1, /*bytes*/1); 463 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 464 pci_status1, /*bytes*/1); 465 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 466 ahd_outb(ahd, CLRINT, CLRPCIINT); 467 468 ahd_outb(ahd, SEQCTL0, PERRORDIS); 469 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 470 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 471 goto fail; 472 473 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 474 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 475 targpcistat = ahd_inb(ahd, TARGPCISTAT); 476 if ((targpcistat & STA) != 0) 477 goto fail; 478 } 479 480 error = 0; 481 482fail: 483 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 484 485 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 486 targpcistat = ahd_inb(ahd, TARGPCISTAT); 487 488 /* Silently clear any latched errors. */ 489 ahd_outb(ahd, TARGPCISTAT, targpcistat); 490 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 491 PCIR_STATUS + 1, /*bytes*/1); 492 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 493 pci_status1, /*bytes*/1); 494 ahd_outb(ahd, CLRINT, CLRPCIINT); 495 } 496 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 497 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 498 return (error); 499} 500 501/* 502 * Check the external port logic for a serial eeprom 503 * and termination/cable detection contrls. 504 */ 505static int 506ahd_check_extport(struct ahd_softc *ahd) 507{ 508 struct vpd_config vpd; 509 struct seeprom_config *sc; 510 u_int adapter_control; 511 int have_seeprom; 512 int error; 513 514 sc = ahd->seep_config; 515 have_seeprom = ahd_acquire_seeprom(ahd); 516 if (have_seeprom) { 517 u_int start_addr; 518 519 /* 520 * Fetch VPD for this function and parse it. 521 */ 522 if (bootverbose) 523 printk("%s: Reading VPD from SEEPROM...", 524 ahd_name(ahd)); 525 526 /* Address is always in units of 16bit words */ 527 start_addr = ((2 * sizeof(*sc)) 528 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 529 530 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 531 start_addr, sizeof(vpd)/2, 532 /*bytestream*/TRUE); 533 if (error == 0) 534 error = ahd_parse_vpddata(ahd, &vpd); 535 if (bootverbose) 536 printk("%s: VPD parsing %s\n", 537 ahd_name(ahd), 538 error == 0 ? "successful" : "failed"); 539 540 if (bootverbose) 541 printk("%s: Reading SEEPROM...", ahd_name(ahd)); 542 543 /* Address is always in units of 16bit words */ 544 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 545 546 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 547 start_addr, sizeof(*sc)/2, 548 /*bytestream*/FALSE); 549 550 if (error != 0) { 551 printk("Unable to read SEEPROM\n"); 552 have_seeprom = 0; 553 } else { 554 have_seeprom = ahd_verify_cksum(sc); 555 556 if (bootverbose) { 557 if (have_seeprom == 0) 558 printk ("checksum error\n"); 559 else 560 printk ("done.\n"); 561 } 562 } 563 ahd_release_seeprom(ahd); 564 } 565 566 if (!have_seeprom) { 567 u_int nvram_scb; 568 569 /* 570 * Pull scratch ram settings and treat them as 571 * if they are the contents of an seeprom if 572 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 573 * in SCB 0xFF. We manually compose the data as 16bit 574 * values to avoid endian issues. 575 */ 576 ahd_set_scbptr(ahd, 0xFF); 577 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 578 if (nvram_scb != 0xFF 579 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 580 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 581 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 582 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 583 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 584 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 585 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 586 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 587 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 588 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 589 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 590 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 591 uint16_t *sc_data; 592 int i; 593 594 ahd_set_scbptr(ahd, nvram_scb); 595 sc_data = (uint16_t *)sc; 596 for (i = 0; i < 64; i += 2) 597 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 598 have_seeprom = ahd_verify_cksum(sc); 599 if (have_seeprom) 600 ahd->flags |= AHD_SCB_CONFIG_USED; 601 } 602 } 603 604#ifdef AHD_DEBUG 605 if (have_seeprom != 0 606 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 607 uint16_t *sc_data; 608 int i; 609 610 printk("%s: Seeprom Contents:", ahd_name(ahd)); 611 sc_data = (uint16_t *)sc; 612 for (i = 0; i < (sizeof(*sc)); i += 2) 613 printk("\n\t0x%.4x", sc_data[i]); 614 printk("\n"); 615 } 616#endif 617 618 if (!have_seeprom) { 619 if (bootverbose) 620 printk("%s: No SEEPROM available.\n", ahd_name(ahd)); 621 ahd->flags |= AHD_USEDEFAULTS; 622 error = ahd_default_config(ahd); 623 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 624 kfree(ahd->seep_config); 625 ahd->seep_config = NULL; 626 } else { 627 error = ahd_parse_cfgdata(ahd, sc); 628 adapter_control = sc->adapter_control; 629 } 630 if (error != 0) 631 return (error); 632 633 ahd_configure_termination(ahd, adapter_control); 634 635 return (0); 636} 637 638static void 639ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 640{ 641 int error; 642 u_int sxfrctl1; 643 uint8_t termctl; 644 uint32_t devconfig; 645 646 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 647 devconfig &= ~STPWLEVEL; 648 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 649 devconfig |= STPWLEVEL; 650 if (bootverbose) 651 printk("%s: STPWLEVEL is %s\n", 652 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 653 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 654 655 /* Make sure current sensing is off. */ 656 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 657 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 658 } 659 660 /* 661 * Read to sense. Write to set. 662 */ 663 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 664 if ((adapter_control & CFAUTOTERM) == 0) { 665 if (bootverbose) 666 printk("%s: Manual Primary Termination\n", 667 ahd_name(ahd)); 668 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 669 if ((adapter_control & CFSTERM) != 0) 670 termctl |= FLX_TERMCTL_ENPRILOW; 671 if ((adapter_control & CFWSTERM) != 0) 672 termctl |= FLX_TERMCTL_ENPRIHIGH; 673 } else if (error != 0) { 674 printk("%s: Primary Auto-Term Sensing failed! " 675 "Using Defaults.\n", ahd_name(ahd)); 676 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 677 } 678 679 if ((adapter_control & CFSEAUTOTERM) == 0) { 680 if (bootverbose) 681 printk("%s: Manual Secondary Termination\n", 682 ahd_name(ahd)); 683 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 684 if ((adapter_control & CFSELOWTERM) != 0) 685 termctl |= FLX_TERMCTL_ENSECLOW; 686 if ((adapter_control & CFSEHIGHTERM) != 0) 687 termctl |= FLX_TERMCTL_ENSECHIGH; 688 } else if (error != 0) { 689 printk("%s: Secondary Auto-Term Sensing failed! " 690 "Using Defaults.\n", ahd_name(ahd)); 691 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 692 } 693 694 /* 695 * Now set the termination based on what we found. 696 */ 697 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 698 ahd->flags &= ~AHD_TERM_ENB_A; 699 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 700 ahd->flags |= AHD_TERM_ENB_A; 701 sxfrctl1 |= STPWEN; 702 } 703 /* Must set the latch once in order to be effective. */ 704 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 705 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 706 707 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 708 if (error != 0) { 709 printk("%s: Unable to set termination settings!\n", 710 ahd_name(ahd)); 711 } else if (bootverbose) { 712 printk("%s: Primary High byte termination %sabled\n", 713 ahd_name(ahd), 714 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 715 716 printk("%s: Primary Low byte termination %sabled\n", 717 ahd_name(ahd), 718 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 719 720 printk("%s: Secondary High byte termination %sabled\n", 721 ahd_name(ahd), 722 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 723 724 printk("%s: Secondary Low byte termination %sabled\n", 725 ahd_name(ahd), 726 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 727 } 728 return; 729} 730 731#define DPE 0x80 732#define SSE 0x40 733#define RMA 0x20 734#define RTA 0x10 735#define STA 0x08 736#define DPR 0x01 737 738static const char *split_status_source[] = 739{ 740 "DFF0", 741 "DFF1", 742 "OVLY", 743 "CMC", 744}; 745 746static const char *pci_status_source[] = 747{ 748 "DFF0", 749 "DFF1", 750 "SG", 751 "CMC", 752 "OVLY", 753 "NONE", 754 "MSI", 755 "TARG" 756}; 757 758static const char *split_status_strings[] = 759{ 760 "%s: Received split response in %s.\n", 761 "%s: Received split completion error message in %s\n", 762 "%s: Receive overrun in %s\n", 763 "%s: Count not complete in %s\n", 764 "%s: Split completion data bucket in %s\n", 765 "%s: Split completion address error in %s\n", 766 "%s: Split completion byte count error in %s\n", 767 "%s: Signaled Target-abort to early terminate a split in %s\n" 768}; 769 770static const char *pci_status_strings[] = 771{ 772 "%s: Data Parity Error has been reported via PERR# in %s\n", 773 "%s: Target initial wait state error in %s\n", 774 "%s: Split completion read data parity error in %s\n", 775 "%s: Split completion address attribute parity error in %s\n", 776 "%s: Received a Target Abort in %s\n", 777 "%s: Received a Master Abort in %s\n", 778 "%s: Signal System Error Detected in %s\n", 779 "%s: Address or Write Phase Parity Error Detected in %s.\n" 780}; 781 782static void 783ahd_pci_intr(struct ahd_softc *ahd) 784{ 785 uint8_t pci_status[8]; 786 ahd_mode_state saved_modes; 787 u_int pci_status1; 788 u_int intstat; 789 u_int i; 790 u_int reg; 791 792 intstat = ahd_inb(ahd, INTSTAT); 793 794 if ((intstat & SPLTINT) != 0) 795 ahd_pci_split_intr(ahd, intstat); 796 797 if ((intstat & PCIINT) == 0) 798 return; 799 800 printk("%s: PCI error Interrupt\n", ahd_name(ahd)); 801 saved_modes = ahd_save_modes(ahd); 802 ahd_dump_card_state(ahd); 803 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 804 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 805 806 if (i == 5) 807 continue; 808 pci_status[i] = ahd_inb(ahd, reg); 809 /* Clear latched errors. So our interrupt deasserts. */ 810 ahd_outb(ahd, reg, pci_status[i]); 811 } 812 813 for (i = 0; i < 8; i++) { 814 u_int bit; 815 816 if (i == 5) 817 continue; 818 819 for (bit = 0; bit < 8; bit++) { 820 821 if ((pci_status[i] & (0x1 << bit)) != 0) { 822 const char *s; 823 824 s = pci_status_strings[bit]; 825 if (i == 7/*TARG*/ && bit == 3) 826 s = "%s: Signaled Target Abort\n"; 827 printk(s, ahd_name(ahd), pci_status_source[i]); 828 } 829 } 830 } 831 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 832 PCIR_STATUS + 1, /*bytes*/1); 833 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 834 pci_status1, /*bytes*/1); 835 ahd_restore_modes(ahd, saved_modes); 836 ahd_outb(ahd, CLRINT, CLRPCIINT); 837 ahd_unpause(ahd); 838} 839 840static void 841ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 842{ 843 uint8_t split_status[4]; 844 uint8_t split_status1[4]; 845 uint8_t sg_split_status[2]; 846 uint8_t sg_split_status1[2]; 847 ahd_mode_state saved_modes; 848 u_int i; 849 uint16_t pcix_status; 850 851 /* 852 * Check for splits in all modes. Modes 0 and 1 853 * additionally have SG engine splits to look at. 854 */ 855 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 856 /*bytes*/2); 857 printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 858 ahd_name(ahd), pcix_status); 859 saved_modes = ahd_save_modes(ahd); 860 for (i = 0; i < 4; i++) { 861 ahd_set_modes(ahd, i, i); 862 863 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 864 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 865 /* Clear latched errors. So our interrupt deasserts. */ 866 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 867 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 868 if (i > 1) 869 continue; 870 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 871 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 872 /* Clear latched errors. So our interrupt deasserts. */ 873 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 874 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 875 } 876 877 for (i = 0; i < 4; i++) { 878 u_int bit; 879 880 for (bit = 0; bit < 8; bit++) { 881 882 if ((split_status[i] & (0x1 << bit)) != 0) 883 printk(split_status_strings[bit], ahd_name(ahd), 884 split_status_source[i]); 885 886 if (i > 1) 887 continue; 888 889 if ((sg_split_status[i] & (0x1 << bit)) != 0) 890 printk(split_status_strings[bit], ahd_name(ahd), "SG"); 891 } 892 } 893 /* 894 * Clear PCI-X status bits. 895 */ 896 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 897 pcix_status, /*bytes*/2); 898 ahd_outb(ahd, CLRINT, CLRSPLTINT); 899 ahd_restore_modes(ahd, saved_modes); 900} 901 902static int 903ahd_aic7901_setup(struct ahd_softc *ahd) 904{ 905 906 ahd->chip = AHD_AIC7901; 907 ahd->features = AHD_AIC7901_FE; 908 return (ahd_aic790X_setup(ahd)); 909} 910 911static int 912ahd_aic7901A_setup(struct ahd_softc *ahd) 913{ 914 915 ahd->chip = AHD_AIC7901A; 916 ahd->features = AHD_AIC7901A_FE; 917 return (ahd_aic790X_setup(ahd)); 918} 919 920static int 921ahd_aic7902_setup(struct ahd_softc *ahd) 922{ 923 ahd->chip = AHD_AIC7902; 924 ahd->features = AHD_AIC7902_FE; 925 return (ahd_aic790X_setup(ahd)); 926} 927 928static int 929ahd_aic790X_setup(struct ahd_softc *ahd) 930{ 931 ahd_dev_softc_t pci; 932 u_int rev; 933 934 pci = ahd->dev_softc; 935 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 936 if (rev < ID_AIC7902_PCI_REV_A4) { 937 printk("%s: Unable to attach to unsupported chip revision %d\n", 938 ahd_name(ahd), rev); 939 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 940 return (ENXIO); 941 } 942 ahd->channel = ahd_get_pci_function(pci) + 'A'; 943 if (rev < ID_AIC7902_PCI_REV_B0) { 944 /* 945 * Enable A series workarounds. 946 */ 947 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 948 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 949 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 950 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 951 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 952 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 953 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 954 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 955 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 956 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 957 | AHD_FAINT_LED_BUG; 958 959 /* 960 * IO Cell parameter setup. 961 */ 962 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 963 964 if ((ahd->flags & AHD_HP_BOARD) == 0) 965 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 966 } else { 967 /* This is revision B and newer. */ 968 extern uint32_t aic79xx_slowcrc; 969 u_int devconfig1; 970 971 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 972 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY 973 | AHD_BUSFREEREV_BUG; 974 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 975 976 /* If the user requested that the SLOWCRC bit to be set. */ 977 if (aic79xx_slowcrc) 978 ahd->features |= AHD_AIC79XXB_SLOWCRC; 979 980 /* 981 * Some issues have been resolved in the 7901B. 982 */ 983 if ((ahd->features & AHD_MULTI_FUNC) != 0) 984 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 985 986 /* 987 * IO Cell parameter setup. 988 */ 989 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 990 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 991 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 992 993 /* 994 * Set the PREQDIS bit for H2B which disables some workaround 995 * that doesn't work on regular PCI busses. 996 * XXX - Find out exactly what this does from the hardware 997 * folks! 998 */ 999 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1000 ahd_pci_write_config(pci, DEVCONFIG1, 1001 devconfig1|PREQDIS, /*bytes*/1); 1002 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1003 } 1004 1005 return (0); 1006} 1007