1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * SiRFSoC Real Time Clock interface for Linux 4 * 5 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company. 6 */ 7 8#include <linux/module.h> 9#include <linux/err.h> 10#include <linux/rtc.h> 11#include <linux/platform_device.h> 12#include <linux/slab.h> 13#include <linux/io.h> 14#include <linux/of.h> 15#include <linux/regmap.h> 16#include <linux/rtc/sirfsoc_rtciobrg.h> 17 18 19#define RTC_CN 0x00 20#define RTC_ALARM0 0x04 21#define RTC_ALARM1 0x18 22#define RTC_STATUS 0x08 23#define RTC_SW_VALUE 0x40 24#define SIRFSOC_RTC_AL1E (1<<6) 25#define SIRFSOC_RTC_AL1 (1<<4) 26#define SIRFSOC_RTC_HZE (1<<3) 27#define SIRFSOC_RTC_AL0E (1<<2) 28#define SIRFSOC_RTC_HZ (1<<1) 29#define SIRFSOC_RTC_AL0 (1<<0) 30#define RTC_DIV 0x0c 31#define RTC_DEEP_CTRL 0x14 32#define RTC_CLOCK_SWITCH 0x1c 33#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */ 34 35/* Refer to RTC DIV switch */ 36#define RTC_HZ 16 37 38/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */ 39#define RTC_SHIFT 4 40 41#define INTR_SYSRTC_CN 0x48 42 43struct sirfsoc_rtc_drv { 44 struct rtc_device *rtc; 45 u32 rtc_base; 46 u32 irq; 47 unsigned irq_wake; 48 /* Overflow for every 8 years extra time */ 49 u32 overflow_rtc; 50 spinlock_t lock; 51 struct regmap *regmap; 52#ifdef CONFIG_PM 53 u32 saved_counter; 54 u32 saved_overflow_rtc; 55#endif 56}; 57 58static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset) 59{ 60 u32 val; 61 62 regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val); 63 return val; 64} 65 66static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv, 67 u32 offset, u32 val) 68{ 69 regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val); 70} 71 72static int sirfsoc_rtc_read_alarm(struct device *dev, 73 struct rtc_wkalrm *alrm) 74{ 75 unsigned long rtc_alarm, rtc_count; 76 struct sirfsoc_rtc_drv *rtcdrv; 77 78 rtcdrv = dev_get_drvdata(dev); 79 80 spin_lock_irq(&rtcdrv->lock); 81 82 rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 83 84 rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0); 85 memset(alrm, 0, sizeof(struct rtc_wkalrm)); 86 87 /* 88 * assume alarm interval not beyond one round counter overflow_rtc: 89 * 0->0xffffffff 90 */ 91 /* if alarm is in next overflow cycle */ 92 if (rtc_count > rtc_alarm) 93 rtc_time64_to_tm((rtcdrv->overflow_rtc + 1) 94 << (BITS_PER_LONG - RTC_SHIFT) 95 | rtc_alarm >> RTC_SHIFT, &alrm->time); 96 else 97 rtc_time64_to_tm(rtcdrv->overflow_rtc 98 << (BITS_PER_LONG - RTC_SHIFT) 99 | rtc_alarm >> RTC_SHIFT, &alrm->time); 100 if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E) 101 alrm->enabled = 1; 102 103 spin_unlock_irq(&rtcdrv->lock); 104 105 return 0; 106} 107 108static int sirfsoc_rtc_set_alarm(struct device *dev, 109 struct rtc_wkalrm *alrm) 110{ 111 unsigned long rtc_status_reg, rtc_alarm; 112 struct sirfsoc_rtc_drv *rtcdrv; 113 rtcdrv = dev_get_drvdata(dev); 114 115 if (alrm->enabled) { 116 rtc_alarm = rtc_tm_to_time64(&alrm->time); 117 118 spin_lock_irq(&rtcdrv->lock); 119 120 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 121 if (rtc_status_reg & SIRFSOC_RTC_AL0E) { 122 /* 123 * An ongoing alarm in progress - ingore it and not 124 * to return EBUSY 125 */ 126 dev_info(dev, "An old alarm was set, will be replaced by a new one\n"); 127 } 128 129 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT); 130 rtc_status_reg &= ~0x07; /* mask out the lower status bits */ 131 /* 132 * This bit RTC_AL sets it as a wake-up source for Sleep Mode 133 * Writing 1 into this bit will clear it 134 */ 135 rtc_status_reg |= SIRFSOC_RTC_AL0; 136 /* enable the RTC alarm interrupt */ 137 rtc_status_reg |= SIRFSOC_RTC_AL0E; 138 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 139 140 spin_unlock_irq(&rtcdrv->lock); 141 } else { 142 /* 143 * if this function was called with enabled=0 144 * then it could mean that the application is 145 * trying to cancel an ongoing alarm 146 */ 147 spin_lock_irq(&rtcdrv->lock); 148 149 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 150 if (rtc_status_reg & SIRFSOC_RTC_AL0E) { 151 /* clear the RTC status register's alarm bit */ 152 rtc_status_reg &= ~0x07; 153 /* write 1 into SIRFSOC_RTC_AL0 to force a clear */ 154 rtc_status_reg |= (SIRFSOC_RTC_AL0); 155 /* Clear the Alarm enable bit */ 156 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E); 157 158 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, 159 rtc_status_reg); 160 } 161 162 spin_unlock_irq(&rtcdrv->lock); 163 } 164 165 return 0; 166} 167 168static int sirfsoc_rtc_read_time(struct device *dev, 169 struct rtc_time *tm) 170{ 171 unsigned long tmp_rtc = 0; 172 struct sirfsoc_rtc_drv *rtcdrv; 173 rtcdrv = dev_get_drvdata(dev); 174 /* 175 * This patch is taken from WinCE - Need to validate this for 176 * correctness. To work around sirfsoc RTC counter double sync logic 177 * fail, read several times to make sure get stable value. 178 */ 179 do { 180 tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 181 cpu_relax(); 182 } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN)); 183 184 rtc_time64_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) 185 | tmp_rtc >> RTC_SHIFT, tm); 186 return 0; 187} 188 189static int sirfsoc_rtc_set_time(struct device *dev, 190 struct rtc_time *tm) 191{ 192 unsigned long rtc_time; 193 struct sirfsoc_rtc_drv *rtcdrv; 194 rtcdrv = dev_get_drvdata(dev); 195 196 rtc_time = rtc_tm_to_time64(tm); 197 198 rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT); 199 200 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc); 201 sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT); 202 203 return 0; 204} 205 206static int sirfsoc_rtc_alarm_irq_enable(struct device *dev, 207 unsigned int enabled) 208{ 209 unsigned long rtc_status_reg = 0x0; 210 struct sirfsoc_rtc_drv *rtcdrv; 211 212 rtcdrv = dev_get_drvdata(dev); 213 214 spin_lock_irq(&rtcdrv->lock); 215 216 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 217 if (enabled) 218 rtc_status_reg |= SIRFSOC_RTC_AL0E; 219 else 220 rtc_status_reg &= ~SIRFSOC_RTC_AL0E; 221 222 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 223 224 spin_unlock_irq(&rtcdrv->lock); 225 226 return 0; 227 228} 229 230static const struct rtc_class_ops sirfsoc_rtc_ops = { 231 .read_time = sirfsoc_rtc_read_time, 232 .set_time = sirfsoc_rtc_set_time, 233 .read_alarm = sirfsoc_rtc_read_alarm, 234 .set_alarm = sirfsoc_rtc_set_alarm, 235 .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable 236}; 237 238static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata) 239{ 240 struct sirfsoc_rtc_drv *rtcdrv = pdata; 241 unsigned long rtc_status_reg = 0x0; 242 unsigned long events = 0x0; 243 244 spin_lock(&rtcdrv->lock); 245 246 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS); 247 /* this bit will be set ONLY if an alarm was active 248 * and it expired NOW 249 * So this is being used as an ASSERT 250 */ 251 if (rtc_status_reg & SIRFSOC_RTC_AL0) { 252 /* 253 * clear the RTC status register's alarm bit 254 * mask out the lower status bits 255 */ 256 rtc_status_reg &= ~0x07; 257 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */ 258 rtc_status_reg |= (SIRFSOC_RTC_AL0); 259 /* Clear the Alarm enable bit */ 260 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E); 261 } 262 263 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg); 264 265 spin_unlock(&rtcdrv->lock); 266 267 /* this should wake up any apps polling/waiting on the read 268 * after setting the alarm 269 */ 270 events |= RTC_IRQF | RTC_AF; 271 rtc_update_irq(rtcdrv->rtc, 1, events); 272 273 return IRQ_HANDLED; 274} 275 276static const struct of_device_id sirfsoc_rtc_of_match[] = { 277 { .compatible = "sirf,prima2-sysrtc"}, 278 {}, 279}; 280 281static const struct regmap_config sysrtc_regmap_config = { 282 .reg_bits = 32, 283 .val_bits = 32, 284 .fast_io = true, 285}; 286 287MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match); 288 289static int sirfsoc_rtc_probe(struct platform_device *pdev) 290{ 291 int err; 292 unsigned long rtc_div; 293 struct sirfsoc_rtc_drv *rtcdrv; 294 struct device_node *np = pdev->dev.of_node; 295 296 rtcdrv = devm_kzalloc(&pdev->dev, 297 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL); 298 if (rtcdrv == NULL) 299 return -ENOMEM; 300 301 spin_lock_init(&rtcdrv->lock); 302 303 err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base); 304 if (err) { 305 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n"); 306 return err; 307 } 308 309 platform_set_drvdata(pdev, rtcdrv); 310 311 /* Register rtc alarm as a wakeup source */ 312 device_init_wakeup(&pdev->dev, 1); 313 314 rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev, 315 &sysrtc_regmap_config); 316 if (IS_ERR(rtcdrv->regmap)) { 317 err = PTR_ERR(rtcdrv->regmap); 318 dev_err(&pdev->dev, "Failed to allocate register map: %d\n", 319 err); 320 return err; 321 } 322 323 /* 324 * Set SYS_RTC counter in RTC_HZ HZ Units 325 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1 326 * If 16HZ, therefore RTC_DIV = 1023; 327 */ 328 rtc_div = ((32768 / RTC_HZ) / 2) - 1; 329 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div); 330 331 /* 0x3 -> RTC_CLK */ 332 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK); 333 334 /* reset SYS RTC ALARM0 */ 335 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0); 336 337 /* reset SYS RTC ALARM1 */ 338 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0); 339 340 /* Restore RTC Overflow From Register After Command Reboot */ 341 rtcdrv->overflow_rtc = 342 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE); 343 344 rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev); 345 if (IS_ERR(rtcdrv->rtc)) 346 return PTR_ERR(rtcdrv->rtc); 347 348 rtcdrv->rtc->ops = &sirfsoc_rtc_ops; 349 rtcdrv->rtc->range_max = (1ULL << 60) - 1; 350 351 rtcdrv->irq = platform_get_irq(pdev, 0); 352 err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler, 353 IRQF_SHARED, pdev->name, rtcdrv); 354 if (err) { 355 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n"); 356 return err; 357 } 358 359 return rtc_register_device(rtcdrv->rtc); 360} 361 362#ifdef CONFIG_PM_SLEEP 363static int sirfsoc_rtc_suspend(struct device *dev) 364{ 365 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); 366 rtcdrv->overflow_rtc = 367 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE); 368 369 rtcdrv->saved_counter = 370 sirfsoc_rtc_readl(rtcdrv, RTC_CN); 371 rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc; 372 if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq)) 373 rtcdrv->irq_wake = 1; 374 375 return 0; 376} 377 378static int sirfsoc_rtc_resume(struct device *dev) 379{ 380 u32 tmp; 381 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev); 382 383 /* 384 * if resume from snapshot and the rtc power is lost, 385 * restroe the rtc settings 386 */ 387 if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) { 388 u32 rtc_div; 389 /* 0x3 -> RTC_CLK */ 390 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK); 391 /* 392 * Set SYS_RTC counter in RTC_HZ HZ Units 393 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1 394 * If 16HZ, therefore RTC_DIV = 1023; 395 */ 396 rtc_div = ((32768 / RTC_HZ) / 2) - 1; 397 398 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div); 399 400 /* reset SYS RTC ALARM0 */ 401 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0); 402 403 /* reset SYS RTC ALARM1 */ 404 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0); 405 } 406 rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc; 407 408 /* 409 * if current counter is small than previous, 410 * it means overflow in sleep 411 */ 412 tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN); 413 if (tmp <= rtcdrv->saved_counter) 414 rtcdrv->overflow_rtc++; 415 /* 416 *PWRC Value Be Changed When Suspend, Restore Overflow 417 * In Memory To Register 418 */ 419 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc); 420 421 if (device_may_wakeup(dev) && rtcdrv->irq_wake) { 422 disable_irq_wake(rtcdrv->irq); 423 rtcdrv->irq_wake = 0; 424 } 425 426 return 0; 427} 428#endif 429 430static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops, 431 sirfsoc_rtc_suspend, sirfsoc_rtc_resume); 432 433static struct platform_driver sirfsoc_rtc_driver = { 434 .driver = { 435 .name = "sirfsoc-rtc", 436 .pm = &sirfsoc_rtc_pm_ops, 437 .of_match_table = sirfsoc_rtc_of_match, 438 }, 439 .probe = sirfsoc_rtc_probe, 440}; 441module_platform_driver(sirfsoc_rtc_driver); 442 443MODULE_DESCRIPTION("SiRF SoC rtc driver"); 444MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>"); 445MODULE_LICENSE("GPL v2"); 446MODULE_ALIAS("platform:sirfsoc-rtc"); 447