xref: /kernel/linux/linux-5.10/drivers/rtc/rtc-pxa.c (revision 8c2ecf20) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Real Time Clock interface for XScale PXA27x and PXA3xx
4 *
5 * Copyright (C) 2008 Robert Jarzmik
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/rtc.h>
12#include <linux/seq_file.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18
19#include <mach/hardware.h>
20
21#include "rtc-sa1100.h"
22
23#define RTC_DEF_DIVIDER		(32768 - 1)
24#define RTC_DEF_TRIM		0
25#define MAXFREQ_PERIODIC	1000
26
27/*
28 * PXA Registers and bits definitions
29 */
30#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
31#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
32#define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
33#define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
34#define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
35#define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
36#define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
37#define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
38#define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
39#define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
40#define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
41#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
42#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
43#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
44#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
45#define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
46			 | RTSR_SWAL1 | RTSR_SWAL2)
47#define RYxR_YEAR_S	9
48#define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
49#define RYxR_MONTH_S	5
50#define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
51#define RYxR_DAY_MASK	0x1f
52#define RDxR_WOM_S     20
53#define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
54#define RDxR_DOW_S     17
55#define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
56#define RDxR_HOUR_S	12
57#define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
58#define RDxR_MIN_S	6
59#define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
60#define RDxR_SEC_MASK	0x3f
61
62#define RTSR		0x08
63#define RTTR		0x0c
64#define RDCR		0x10
65#define RYCR		0x14
66#define RDAR1		0x18
67#define RYAR1		0x1c
68#define RTCPICR		0x34
69#define PIAR		0x38
70
71#define rtc_readl(pxa_rtc, reg)	\
72	__raw_readl((pxa_rtc)->base + (reg))
73#define rtc_writel(pxa_rtc, reg, value)	\
74	__raw_writel((value), (pxa_rtc)->base + (reg))
75
76struct pxa_rtc {
77	struct sa1100_rtc sa1100_rtc;
78	struct resource	*ress;
79	void __iomem		*base;
80	struct rtc_device	*rtc;
81	spinlock_t		lock;		/* Protects this structure */
82};
83
84
85static u32 ryxr_calc(struct rtc_time *tm)
86{
87	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
88		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
89		| tm->tm_mday;
90}
91
92static u32 rdxr_calc(struct rtc_time *tm)
93{
94	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
95		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
96		| (tm->tm_hour << RDxR_HOUR_S)
97		| (tm->tm_min << RDxR_MIN_S)
98		| tm->tm_sec;
99}
100
101static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
102{
103	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
104	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
105	tm->tm_mday = (rycr & RYxR_DAY_MASK);
106	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
107	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
108	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
109	tm->tm_sec = rdcr & RDxR_SEC_MASK;
110}
111
112static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
113{
114	u32 rtsr;
115
116	rtsr = rtc_readl(pxa_rtc, RTSR);
117	rtsr &= ~RTSR_TRIG_MASK;
118	rtsr &= ~mask;
119	rtc_writel(pxa_rtc, RTSR, rtsr);
120}
121
122static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
123{
124	u32 rtsr;
125
126	rtsr = rtc_readl(pxa_rtc, RTSR);
127	rtsr &= ~RTSR_TRIG_MASK;
128	rtsr |= mask;
129	rtc_writel(pxa_rtc, RTSR, rtsr);
130}
131
132static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
133{
134	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
135	u32 rtsr;
136	unsigned long events = 0;
137
138	spin_lock(&pxa_rtc->lock);
139
140	/* clear interrupt sources */
141	rtsr = rtc_readl(pxa_rtc, RTSR);
142	rtc_writel(pxa_rtc, RTSR, rtsr);
143
144	/* temporary disable rtc interrupts */
145	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
146
147	/* clear alarm interrupt if it has occurred */
148	if (rtsr & RTSR_RDAL1)
149		rtsr &= ~RTSR_RDALE1;
150
151	/* update irq data & counter */
152	if (rtsr & RTSR_RDAL1)
153		events |= RTC_AF | RTC_IRQF;
154	if (rtsr & RTSR_HZ)
155		events |= RTC_UF | RTC_IRQF;
156	if (rtsr & RTSR_PIAL)
157		events |= RTC_PF | RTC_IRQF;
158
159	rtc_update_irq(pxa_rtc->rtc, 1, events);
160
161	/* enable back rtc interrupts */
162	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
163
164	spin_unlock(&pxa_rtc->lock);
165	return IRQ_HANDLED;
166}
167
168static int pxa_rtc_open(struct device *dev)
169{
170	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
171	int ret;
172
173	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
174			  "rtc 1Hz", dev);
175	if (ret < 0) {
176		dev_err(dev, "can't get irq %i, err %d\n",
177			pxa_rtc->sa1100_rtc.irq_1hz, ret);
178		goto err_irq_1Hz;
179	}
180	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
181			  "rtc Alrm", dev);
182	if (ret < 0) {
183		dev_err(dev, "can't get irq %i, err %d\n",
184			pxa_rtc->sa1100_rtc.irq_alarm, ret);
185		goto err_irq_Alrm;
186	}
187
188	return 0;
189
190err_irq_Alrm:
191	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
192err_irq_1Hz:
193	return ret;
194}
195
196static void pxa_rtc_release(struct device *dev)
197{
198	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
199
200	spin_lock_irq(&pxa_rtc->lock);
201	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
202	spin_unlock_irq(&pxa_rtc->lock);
203
204	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
205	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
206}
207
208static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
209{
210	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
211
212	spin_lock_irq(&pxa_rtc->lock);
213
214	if (enabled)
215		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
216	else
217		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
218
219	spin_unlock_irq(&pxa_rtc->lock);
220	return 0;
221}
222
223static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
224{
225	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
226	u32 rycr, rdcr;
227
228	rycr = rtc_readl(pxa_rtc, RYCR);
229	rdcr = rtc_readl(pxa_rtc, RDCR);
230
231	tm_calc(rycr, rdcr, tm);
232	return 0;
233}
234
235static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
236{
237	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
238
239	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
240	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
241
242	return 0;
243}
244
245static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
246{
247	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
248	u32 rtsr, ryar, rdar;
249
250	ryar = rtc_readl(pxa_rtc, RYAR1);
251	rdar = rtc_readl(pxa_rtc, RDAR1);
252	tm_calc(ryar, rdar, &alrm->time);
253
254	rtsr = rtc_readl(pxa_rtc, RTSR);
255	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
256	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
257	return 0;
258}
259
260static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
261{
262	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
263	u32 rtsr;
264
265	spin_lock_irq(&pxa_rtc->lock);
266
267	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
268	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
269
270	rtsr = rtc_readl(pxa_rtc, RTSR);
271	if (alrm->enabled)
272		rtsr |= RTSR_RDALE1;
273	else
274		rtsr &= ~RTSR_RDALE1;
275	rtc_writel(pxa_rtc, RTSR, rtsr);
276
277	spin_unlock_irq(&pxa_rtc->lock);
278
279	return 0;
280}
281
282static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
283{
284	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
285
286	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
287	seq_printf(seq, "update_IRQ\t: %s\n",
288		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
289	seq_printf(seq, "periodic_IRQ\t: %s\n",
290		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
291	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
292
293	return 0;
294}
295
296static const struct rtc_class_ops pxa_rtc_ops = {
297	.read_time = pxa_rtc_read_time,
298	.set_time = pxa_rtc_set_time,
299	.read_alarm = pxa_rtc_read_alarm,
300	.set_alarm = pxa_rtc_set_alarm,
301	.alarm_irq_enable = pxa_alarm_irq_enable,
302	.proc = pxa_rtc_proc,
303};
304
305static int __init pxa_rtc_probe(struct platform_device *pdev)
306{
307	struct device *dev = &pdev->dev;
308	struct pxa_rtc *pxa_rtc;
309	struct sa1100_rtc *sa1100_rtc;
310	int ret;
311
312	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
313	if (!pxa_rtc)
314		return -ENOMEM;
315	sa1100_rtc = &pxa_rtc->sa1100_rtc;
316
317	spin_lock_init(&pxa_rtc->lock);
318	platform_set_drvdata(pdev, pxa_rtc);
319
320	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321	if (!pxa_rtc->ress) {
322		dev_err(dev, "No I/O memory resource defined\n");
323		return -ENXIO;
324	}
325
326	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
327	if (sa1100_rtc->irq_1hz < 0)
328		return -ENXIO;
329	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
330	if (sa1100_rtc->irq_alarm < 0)
331		return -ENXIO;
332
333	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
334	if (IS_ERR(sa1100_rtc->rtc))
335		return PTR_ERR(sa1100_rtc->rtc);
336
337	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
338				resource_size(pxa_rtc->ress));
339	if (!pxa_rtc->base) {
340		dev_err(dev, "Unable to map pxa RTC I/O memory\n");
341		return -ENOMEM;
342	}
343
344	pxa_rtc_open(dev);
345
346	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
347	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
348	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
349	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
350	ret = sa1100_rtc_init(pdev, sa1100_rtc);
351	if (ret) {
352		dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
353		return ret;
354	}
355
356	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
357
358	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
359						&pxa_rtc_ops, THIS_MODULE);
360	if (IS_ERR(pxa_rtc->rtc)) {
361		ret = PTR_ERR(pxa_rtc->rtc);
362		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
363		return ret;
364	}
365
366	device_init_wakeup(dev, 1);
367
368	return 0;
369}
370
371static int __exit pxa_rtc_remove(struct platform_device *pdev)
372{
373	struct device *dev = &pdev->dev;
374
375	pxa_rtc_release(dev);
376	return 0;
377}
378
379#ifdef CONFIG_OF
380static const struct of_device_id pxa_rtc_dt_ids[] = {
381	{ .compatible = "marvell,pxa-rtc" },
382	{}
383};
384MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
385#endif
386
387#ifdef CONFIG_PM_SLEEP
388static int pxa_rtc_suspend(struct device *dev)
389{
390	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
391
392	if (device_may_wakeup(dev))
393		enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
394	return 0;
395}
396
397static int pxa_rtc_resume(struct device *dev)
398{
399	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
400
401	if (device_may_wakeup(dev))
402		disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
403	return 0;
404}
405#endif
406
407static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
408
409static struct platform_driver pxa_rtc_driver = {
410	.remove		= __exit_p(pxa_rtc_remove),
411	.driver		= {
412		.name	= "pxa-rtc",
413		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
414		.pm	= &pxa_rtc_pm_ops,
415	},
416};
417
418module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
419
420MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
421MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
422MODULE_LICENSE("GPL");
423MODULE_ALIAS("platform:pxa-rtc");
424