1// SPDX-License-Identifier: GPL-2.0
2/*
3 * An I2C driver for the PCF85063 RTC
4 * Copyright 2014 Rose Technology
5 *
6 * Author: Søren Andersen <san@rosetechnology.dk>
7 * Maintainers: http://www.nslu2-linux.org/
8 *
9 * Copyright (C) 2019 Micro Crystal AG
10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
11 */
12#include <linux/clk-provider.h>
13#include <linux/i2c.h>
14#include <linux/bcd.h>
15#include <linux/rtc.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regmap.h>
20
21/*
22 * Information for this driver was pulled from the following datasheets.
23 *
24 *  https://www.nxp.com/documents/data_sheet/PCF85063A.pdf
25 *  https://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
26 *
27 *  PCF85063A -- Rev. 6 — 18 November 2015
28 *  PCF85063TP -- Rev. 4 — 6 May 2015
29 *
30 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
31 *  RV8263 -- Rev. 1.0 — January 2019
32 */
33
34#define PCF85063_REG_CTRL1		0x00 /* status */
35#define PCF85063_REG_CTRL1_CAP_SEL	BIT(0)
36#define PCF85063_REG_CTRL1_STOP		BIT(5)
37
38#define PCF85063_REG_CTRL2		0x01
39#define PCF85063_CTRL2_AF		BIT(6)
40#define PCF85063_CTRL2_AIE		BIT(7)
41
42#define PCF85063_REG_OFFSET		0x02
43#define PCF85063_OFFSET_SIGN_BIT	6	/* 2's complement sign bit */
44#define PCF85063_OFFSET_MODE		BIT(7)
45#define PCF85063_OFFSET_STEP0		4340
46#define PCF85063_OFFSET_STEP1		4069
47
48#define PCF85063_REG_CLKO_F_MASK	0x07 /* frequency mask */
49#define PCF85063_REG_CLKO_F_32768HZ	0x00
50#define PCF85063_REG_CLKO_F_OFF		0x07
51
52#define PCF85063_REG_RAM		0x03
53
54#define PCF85063_REG_SC			0x04 /* datetime */
55#define PCF85063_REG_SC_OS		0x80
56
57#define PCF85063_REG_ALM_S		0x0b
58#define PCF85063_AEN			BIT(7)
59
60struct pcf85063_config {
61	struct regmap_config regmap;
62	unsigned has_alarms:1;
63	unsigned force_cap_7000:1;
64};
65
66struct pcf85063 {
67	struct rtc_device	*rtc;
68	struct regmap		*regmap;
69#ifdef CONFIG_COMMON_CLK
70	struct clk_hw		clkout_hw;
71#endif
72};
73
74static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
75{
76	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
77	int rc;
78	u8 regs[7];
79
80	/*
81	 * while reading, the time/date registers are blocked and not updated
82	 * anymore until the access is finished. To not lose a second
83	 * event, the access must be finished within one second. So, read all
84	 * time/date registers in one turn.
85	 */
86	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
87			      sizeof(regs));
88	if (rc)
89		return rc;
90
91	/* if the clock has lost its power it makes no sense to use its time */
92	if (regs[0] & PCF85063_REG_SC_OS) {
93		dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
94		return -EINVAL;
95	}
96
97	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
98	tm->tm_min = bcd2bin(regs[1] & 0x7F);
99	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
100	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
101	tm->tm_wday = regs[4] & 0x07;
102	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
103	tm->tm_year = bcd2bin(regs[6]);
104	tm->tm_year += 100;
105
106	return 0;
107}
108
109static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
110{
111	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
112	int rc;
113	u8 regs[7];
114
115	/*
116	 * to accurately set the time, reset the divider chain and keep it in
117	 * reset state until all time/date registers are written
118	 */
119	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
120				PCF85063_REG_CTRL1_STOP,
121				PCF85063_REG_CTRL1_STOP);
122	if (rc)
123		return rc;
124
125	/* hours, minutes and seconds */
126	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
127
128	regs[1] = bin2bcd(tm->tm_min);
129	regs[2] = bin2bcd(tm->tm_hour);
130
131	/* Day of month, 1 - 31 */
132	regs[3] = bin2bcd(tm->tm_mday);
133
134	/* Day, 0 - 6 */
135	regs[4] = tm->tm_wday & 0x07;
136
137	/* month, 1 - 12 */
138	regs[5] = bin2bcd(tm->tm_mon + 1);
139
140	/* year and century */
141	regs[6] = bin2bcd(tm->tm_year - 100);
142
143	/* write all registers at once */
144	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
145			       regs, sizeof(regs));
146	if (rc)
147		return rc;
148
149	/*
150	 * Write the control register as a separate action since the size of
151	 * the register space is different between the PCF85063TP and
152	 * PCF85063A devices.  The rollover point can not be used.
153	 */
154	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
155				  PCF85063_REG_CTRL1_STOP, 0);
156}
157
158static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
159{
160	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
161	u8 buf[4];
162	unsigned int val;
163	int ret;
164
165	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
166			       buf, sizeof(buf));
167	if (ret)
168		return ret;
169
170	alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
171	alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
172	alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
173	alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
174
175	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
176	if (ret)
177		return ret;
178
179	alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);
180
181	return 0;
182}
183
184static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
185{
186	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
187	u8 buf[5];
188	int ret;
189
190	buf[0] = bin2bcd(alrm->time.tm_sec);
191	buf[1] = bin2bcd(alrm->time.tm_min);
192	buf[2] = bin2bcd(alrm->time.tm_hour);
193	buf[3] = bin2bcd(alrm->time.tm_mday);
194	buf[4] = PCF85063_AEN; /* Do not match on week day */
195
196	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
197				 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
198	if (ret)
199		return ret;
200
201	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
202				buf, sizeof(buf));
203	if (ret)
204		return ret;
205
206	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
207				  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
208				  alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
209}
210
211static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
212					 unsigned int enabled)
213{
214	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
215
216	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
217				  PCF85063_CTRL2_AIE,
218				  enabled ? PCF85063_CTRL2_AIE : 0);
219}
220
221static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
222{
223	struct pcf85063 *pcf85063 = dev_id;
224	unsigned int val;
225	int err;
226
227	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
228	if (err)
229		return IRQ_NONE;
230
231	if (val & PCF85063_CTRL2_AF) {
232		rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
233		regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
234				   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
235				   0);
236		return IRQ_HANDLED;
237	}
238
239	return IRQ_NONE;
240}
241
242static int pcf85063_read_offset(struct device *dev, long *offset)
243{
244	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
245	long val;
246	u32 reg;
247	int ret;
248
249	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
250	if (ret < 0)
251		return ret;
252
253	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
254			    PCF85063_OFFSET_SIGN_BIT);
255
256	if (reg & PCF85063_OFFSET_MODE)
257		*offset = val * PCF85063_OFFSET_STEP1;
258	else
259		*offset = val * PCF85063_OFFSET_STEP0;
260
261	return 0;
262}
263
264static int pcf85063_set_offset(struct device *dev, long offset)
265{
266	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
267	s8 mode0, mode1, reg;
268	unsigned int error0, error1;
269
270	if (offset > PCF85063_OFFSET_STEP0 * 63)
271		return -ERANGE;
272	if (offset < PCF85063_OFFSET_STEP0 * -64)
273		return -ERANGE;
274
275	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
276	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
277
278	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
279	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
280	if (mode1 > 63 || mode1 < -64 || error0 < error1)
281		reg = mode0 & ~PCF85063_OFFSET_MODE;
282	else
283		reg = mode1 | PCF85063_OFFSET_MODE;
284
285	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
286}
287
288static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
289			  unsigned long arg)
290{
291	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
292	int status, ret = 0;
293
294	switch (cmd) {
295	case RTC_VL_READ:
296		ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
297		if (ret < 0)
298			return ret;
299
300		status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;
301
302		return put_user(status, (unsigned int __user *)arg);
303
304	default:
305		return -ENOIOCTLCMD;
306	}
307}
308
309static const struct rtc_class_ops pcf85063_rtc_ops = {
310	.read_time	= pcf85063_rtc_read_time,
311	.set_time	= pcf85063_rtc_set_time,
312	.read_offset	= pcf85063_read_offset,
313	.set_offset	= pcf85063_set_offset,
314	.ioctl		= pcf85063_ioctl,
315};
316
317static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
318	.read_time	= pcf85063_rtc_read_time,
319	.set_time	= pcf85063_rtc_set_time,
320	.read_offset	= pcf85063_read_offset,
321	.set_offset	= pcf85063_set_offset,
322	.read_alarm	= pcf85063_rtc_read_alarm,
323	.set_alarm	= pcf85063_rtc_set_alarm,
324	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
325	.ioctl		= pcf85063_ioctl,
326};
327
328static int pcf85063_nvmem_read(void *priv, unsigned int offset,
329			       void *val, size_t bytes)
330{
331	return regmap_read(priv, PCF85063_REG_RAM, val);
332}
333
334static int pcf85063_nvmem_write(void *priv, unsigned int offset,
335				void *val, size_t bytes)
336{
337	return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
338}
339
340static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
341				     const struct device_node *np,
342				     unsigned int force_cap)
343{
344	u32 load = 7000;
345	u8 reg = 0;
346
347	if (force_cap)
348		load = force_cap;
349	else
350		of_property_read_u32(np, "quartz-load-femtofarads", &load);
351
352	switch (load) {
353	default:
354		dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
355			 load);
356		fallthrough;
357	case 7000:
358		break;
359	case 12500:
360		reg = PCF85063_REG_CTRL1_CAP_SEL;
361		break;
362	}
363
364	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
365				  PCF85063_REG_CTRL1_CAP_SEL, reg);
366}
367
368#ifdef CONFIG_COMMON_CLK
369/*
370 * Handling of the clkout
371 */
372
373#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
374
375static int clkout_rates[] = {
376	32768,
377	16384,
378	8192,
379	4096,
380	2048,
381	1024,
382	1,
383	0
384};
385
386static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
387						 unsigned long parent_rate)
388{
389	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
390	unsigned int buf;
391	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
392
393	if (ret < 0)
394		return 0;
395
396	buf &= PCF85063_REG_CLKO_F_MASK;
397	return clkout_rates[buf];
398}
399
400static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
401				       unsigned long *prate)
402{
403	int i;
404
405	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
406		if (clkout_rates[i] <= rate)
407			return clkout_rates[i];
408
409	return 0;
410}
411
412static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
413				    unsigned long parent_rate)
414{
415	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
416	int i;
417
418	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
419		if (clkout_rates[i] == rate)
420			return regmap_update_bits(pcf85063->regmap,
421				PCF85063_REG_CTRL2,
422				PCF85063_REG_CLKO_F_MASK, i);
423
424	return -EINVAL;
425}
426
427static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
428{
429	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
430	unsigned int buf;
431	int ret;
432
433	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
434	if (ret < 0)
435		return ret;
436	buf &= PCF85063_REG_CLKO_F_MASK;
437
438	if (enable) {
439		if (buf == PCF85063_REG_CLKO_F_OFF)
440			buf = PCF85063_REG_CLKO_F_32768HZ;
441		else
442			return 0;
443	} else {
444		if (buf != PCF85063_REG_CLKO_F_OFF)
445			buf = PCF85063_REG_CLKO_F_OFF;
446		else
447			return 0;
448	}
449
450	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
451					PCF85063_REG_CLKO_F_MASK, buf);
452}
453
454static int pcf85063_clkout_prepare(struct clk_hw *hw)
455{
456	return pcf85063_clkout_control(hw, 1);
457}
458
459static void pcf85063_clkout_unprepare(struct clk_hw *hw)
460{
461	pcf85063_clkout_control(hw, 0);
462}
463
464static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
465{
466	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
467	unsigned int buf;
468	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
469
470	if (ret < 0)
471		return 0;
472
473	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
474}
475
476static const struct clk_ops pcf85063_clkout_ops = {
477	.prepare = pcf85063_clkout_prepare,
478	.unprepare = pcf85063_clkout_unprepare,
479	.is_prepared = pcf85063_clkout_is_prepared,
480	.recalc_rate = pcf85063_clkout_recalc_rate,
481	.round_rate = pcf85063_clkout_round_rate,
482	.set_rate = pcf85063_clkout_set_rate,
483};
484
485static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
486{
487	struct clk *clk;
488	struct clk_init_data init;
489	struct device_node *node = pcf85063->rtc->dev.parent->of_node;
490
491	init.name = "pcf85063-clkout";
492	init.ops = &pcf85063_clkout_ops;
493	init.flags = 0;
494	init.parent_names = NULL;
495	init.num_parents = 0;
496	pcf85063->clkout_hw.init = &init;
497
498	/* optional override of the clockname */
499	of_property_read_string(node, "clock-output-names", &init.name);
500
501	/* register the clock */
502	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
503
504	if (!IS_ERR(clk))
505		of_clk_add_provider(node, of_clk_src_simple_get, clk);
506
507	return clk;
508}
509#endif
510
511static const struct pcf85063_config pcf85063a_config = {
512	.regmap = {
513		.reg_bits = 8,
514		.val_bits = 8,
515		.max_register = 0x11,
516	},
517	.has_alarms = 1,
518};
519
520static const struct pcf85063_config pcf85063tp_config = {
521	.regmap = {
522		.reg_bits = 8,
523		.val_bits = 8,
524		.max_register = 0x0a,
525	},
526};
527
528static const struct pcf85063_config rv8263_config = {
529	.regmap = {
530		.reg_bits = 8,
531		.val_bits = 8,
532		.max_register = 0x11,
533	},
534	.has_alarms = 1,
535	.force_cap_7000 = 1,
536};
537
538static int pcf85063_probe(struct i2c_client *client)
539{
540	struct pcf85063 *pcf85063;
541	unsigned int tmp;
542	int err;
543	const struct pcf85063_config *config = &pcf85063tp_config;
544	const void *data = of_device_get_match_data(&client->dev);
545	struct nvmem_config nvmem_cfg = {
546		.name = "pcf85063_nvram",
547		.reg_read = pcf85063_nvmem_read,
548		.reg_write = pcf85063_nvmem_write,
549		.type = NVMEM_TYPE_BATTERY_BACKED,
550		.size = 1,
551	};
552
553	dev_dbg(&client->dev, "%s\n", __func__);
554
555	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
556				GFP_KERNEL);
557	if (!pcf85063)
558		return -ENOMEM;
559
560	if (data)
561		config = data;
562
563	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
564	if (IS_ERR(pcf85063->regmap))
565		return PTR_ERR(pcf85063->regmap);
566
567	i2c_set_clientdata(client, pcf85063);
568
569	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
570	if (err) {
571		dev_err(&client->dev, "RTC chip is not present\n");
572		return err;
573	}
574
575	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
576	if (IS_ERR(pcf85063->rtc))
577		return PTR_ERR(pcf85063->rtc);
578
579	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
580					config->force_cap_7000 ? 7000 : 0);
581	if (err < 0)
582		dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
583			 err);
584
585	pcf85063->rtc->ops = &pcf85063_rtc_ops;
586	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
587	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
588	pcf85063->rtc->uie_unsupported = 1;
589
590	if (config->has_alarms && client->irq > 0) {
591		err = devm_request_threaded_irq(&client->dev, client->irq,
592						NULL, pcf85063_rtc_handle_irq,
593						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
594						"pcf85063", pcf85063);
595		if (err) {
596			dev_warn(&pcf85063->rtc->dev,
597				 "unable to request IRQ, alarms disabled\n");
598		} else {
599			pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
600			device_init_wakeup(&client->dev, true);
601			err = dev_pm_set_wake_irq(&client->dev, client->irq);
602			if (err)
603				dev_err(&pcf85063->rtc->dev,
604					"failed to enable irq wake\n");
605		}
606	}
607
608	nvmem_cfg.priv = pcf85063->regmap;
609	rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
610
611#ifdef CONFIG_COMMON_CLK
612	/* register clk in common clk framework */
613	pcf85063_clkout_register_clk(pcf85063);
614#endif
615
616	return rtc_register_device(pcf85063->rtc);
617}
618
619#ifdef CONFIG_OF
620static const struct of_device_id pcf85063_of_match[] = {
621	{ .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
622	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
623	{ .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
624	{ .compatible = "microcrystal,rv8263", .data = &rv8263_config },
625	{}
626};
627MODULE_DEVICE_TABLE(of, pcf85063_of_match);
628#endif
629
630static struct i2c_driver pcf85063_driver = {
631	.driver		= {
632		.name	= "rtc-pcf85063",
633		.of_match_table = of_match_ptr(pcf85063_of_match),
634	},
635	.probe_new	= pcf85063_probe,
636};
637
638module_i2c_driver(pcf85063_driver);
639
640MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
641MODULE_DESCRIPTION("PCF85063 RTC driver");
642MODULE_LICENSE("GPL");
643