18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Broadcom STB generic reset controller for SW_INIT style reset controller 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Author: Florian Fainelli <f.fainelli@gmail.com> 68c2ecf20Sopenharmony_ci * Copyright (C) 2018 Broadcom 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci#include <linux/delay.h> 98c2ecf20Sopenharmony_ci#include <linux/device.h> 108c2ecf20Sopenharmony_ci#include <linux/io.h> 118c2ecf20Sopenharmony_ci#include <linux/module.h> 128c2ecf20Sopenharmony_ci#include <linux/of.h> 138c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 148c2ecf20Sopenharmony_ci#include <linux/reset-controller.h> 158c2ecf20Sopenharmony_ci#include <linux/types.h> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cistruct brcmstb_reset { 188c2ecf20Sopenharmony_ci void __iomem *base; 198c2ecf20Sopenharmony_ci struct reset_controller_dev rcdev; 208c2ecf20Sopenharmony_ci}; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define SW_INIT_SET 0x00 238c2ecf20Sopenharmony_ci#define SW_INIT_CLEAR 0x04 248c2ecf20Sopenharmony_ci#define SW_INIT_STATUS 0x08 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#define SW_INIT_BIT(id) BIT((id) & 0x1f) 278c2ecf20Sopenharmony_ci#define SW_INIT_BANK(id) ((id) >> 5) 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci/* A full bank contains extra registers that we are not utilizing but still 308c2ecf20Sopenharmony_ci * qualify as a single bank. 318c2ecf20Sopenharmony_ci */ 328c2ecf20Sopenharmony_ci#define SW_INIT_BANK_SIZE 0x18 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cistatic inline 358c2ecf20Sopenharmony_cistruct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev) 368c2ecf20Sopenharmony_ci{ 378c2ecf20Sopenharmony_ci return container_of(rcdev, struct brcmstb_reset, rcdev); 388c2ecf20Sopenharmony_ci} 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_cistatic int brcmstb_reset_assert(struct reset_controller_dev *rcdev, 418c2ecf20Sopenharmony_ci unsigned long id) 428c2ecf20Sopenharmony_ci{ 438c2ecf20Sopenharmony_ci unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE; 448c2ecf20Sopenharmony_ci struct brcmstb_reset *priv = to_brcmstb(rcdev); 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci return 0; 498c2ecf20Sopenharmony_ci} 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_cistatic int brcmstb_reset_deassert(struct reset_controller_dev *rcdev, 528c2ecf20Sopenharmony_ci unsigned long id) 538c2ecf20Sopenharmony_ci{ 548c2ecf20Sopenharmony_ci unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE; 558c2ecf20Sopenharmony_ci struct brcmstb_reset *priv = to_brcmstb(rcdev); 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); 588c2ecf20Sopenharmony_ci /* Maximum reset delay after de-asserting a line and seeing block 598c2ecf20Sopenharmony_ci * operation is typically 14us for the worst case, build some slack 608c2ecf20Sopenharmony_ci * here. 618c2ecf20Sopenharmony_ci */ 628c2ecf20Sopenharmony_ci usleep_range(100, 200); 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci return 0; 658c2ecf20Sopenharmony_ci} 668c2ecf20Sopenharmony_ci 678c2ecf20Sopenharmony_cistatic int brcmstb_reset_status(struct reset_controller_dev *rcdev, 688c2ecf20Sopenharmony_ci unsigned long id) 698c2ecf20Sopenharmony_ci{ 708c2ecf20Sopenharmony_ci unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE; 718c2ecf20Sopenharmony_ci struct brcmstb_reset *priv = to_brcmstb(rcdev); 728c2ecf20Sopenharmony_ci 738c2ecf20Sopenharmony_ci return readl_relaxed(priv->base + off + SW_INIT_STATUS) & 748c2ecf20Sopenharmony_ci SW_INIT_BIT(id); 758c2ecf20Sopenharmony_ci} 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_cistatic const struct reset_control_ops brcmstb_reset_ops = { 788c2ecf20Sopenharmony_ci .assert = brcmstb_reset_assert, 798c2ecf20Sopenharmony_ci .deassert = brcmstb_reset_deassert, 808c2ecf20Sopenharmony_ci .status = brcmstb_reset_status, 818c2ecf20Sopenharmony_ci}; 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_cistatic int brcmstb_reset_probe(struct platform_device *pdev) 848c2ecf20Sopenharmony_ci{ 858c2ecf20Sopenharmony_ci struct device *kdev = &pdev->dev; 868c2ecf20Sopenharmony_ci struct brcmstb_reset *priv; 878c2ecf20Sopenharmony_ci struct resource *res; 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); 908c2ecf20Sopenharmony_ci if (!priv) 918c2ecf20Sopenharmony_ci return -ENOMEM; 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 948c2ecf20Sopenharmony_ci priv->base = devm_ioremap_resource(kdev, res); 958c2ecf20Sopenharmony_ci if (IS_ERR(priv->base)) 968c2ecf20Sopenharmony_ci return PTR_ERR(priv->base); 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ci dev_set_drvdata(kdev, priv); 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci priv->rcdev.owner = THIS_MODULE; 1018c2ecf20Sopenharmony_ci priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res), 1028c2ecf20Sopenharmony_ci SW_INIT_BANK_SIZE) * 32; 1038c2ecf20Sopenharmony_ci priv->rcdev.ops = &brcmstb_reset_ops; 1048c2ecf20Sopenharmony_ci priv->rcdev.of_node = kdev->of_node; 1058c2ecf20Sopenharmony_ci /* Use defaults: 1 cell and simple xlate function */ 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ci return devm_reset_controller_register(kdev, &priv->rcdev); 1088c2ecf20Sopenharmony_ci} 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_cistatic const struct of_device_id brcmstb_reset_of_match[] = { 1118c2ecf20Sopenharmony_ci { .compatible = "brcm,brcmstb-reset" }, 1128c2ecf20Sopenharmony_ci { /* sentinel */ } 1138c2ecf20Sopenharmony_ci}; 1148c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, brcmstb_reset_of_match); 1158c2ecf20Sopenharmony_ci 1168c2ecf20Sopenharmony_cistatic struct platform_driver brcmstb_reset_driver = { 1178c2ecf20Sopenharmony_ci .probe = brcmstb_reset_probe, 1188c2ecf20Sopenharmony_ci .driver = { 1198c2ecf20Sopenharmony_ci .name = "brcmstb-reset", 1208c2ecf20Sopenharmony_ci .of_match_table = brcmstb_reset_of_match, 1218c2ecf20Sopenharmony_ci }, 1228c2ecf20Sopenharmony_ci}; 1238c2ecf20Sopenharmony_cimodule_platform_driver(brcmstb_reset_driver); 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_ciMODULE_AUTHOR("Broadcom"); 1268c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Broadcom STB reset controller"); 1278c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 128