1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
4 *
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/firmware.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/qcom_scm.h>
21#include <linux/regulator/consumer.h>
22#include <linux/remoteproc.h>
23#include <linux/soc/qcom/mdt_loader.h>
24#include <linux/soc/qcom/smem.h>
25#include <linux/soc/qcom/smem_state.h>
26#include <linux/rpmsg/qcom_smd.h>
27
28#include "qcom_common.h"
29#include "remoteproc_internal.h"
30#include "qcom_pil_info.h"
31#include "qcom_wcnss.h"
32
33#define WCNSS_CRASH_REASON_SMEM		422
34#define WCNSS_FIRMWARE_NAME		"wcnss.mdt"
35#define WCNSS_PAS_ID			6
36#define WCNSS_SSCTL_ID			0x13
37
38#define WCNSS_SPARE_NVBIN_DLND		BIT(25)
39
40#define WCNSS_PMU_IRIS_XO_CFG		BIT(3)
41#define WCNSS_PMU_IRIS_XO_EN		BIT(4)
42#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP	BIT(5)
43#define WCNSS_PMU_IRIS_XO_CFG_STS	BIT(6) /* 1: in progress, 0: done */
44
45#define WCNSS_PMU_IRIS_RESET		BIT(7)
46#define WCNSS_PMU_IRIS_RESET_STS	BIT(8) /* 1: in progress, 0: done */
47#define WCNSS_PMU_IRIS_XO_READ		BIT(9)
48#define WCNSS_PMU_IRIS_XO_READ_STS	BIT(10)
49
50#define WCNSS_PMU_XO_MODE_MASK		GENMASK(2, 1)
51#define WCNSS_PMU_XO_MODE_19p2		0
52#define WCNSS_PMU_XO_MODE_48		3
53
54struct wcnss_data {
55	size_t pmu_offset;
56	size_t spare_offset;
57
58	const struct wcnss_vreg_info *vregs;
59	size_t num_vregs;
60};
61
62struct qcom_wcnss {
63	struct device *dev;
64	struct rproc *rproc;
65
66	void __iomem *pmu_cfg;
67	void __iomem *spare_out;
68
69	bool use_48mhz_xo;
70
71	int wdog_irq;
72	int fatal_irq;
73	int ready_irq;
74	int handover_irq;
75	int stop_ack_irq;
76
77	struct qcom_smem_state *state;
78	unsigned stop_bit;
79
80	struct mutex iris_lock;
81	struct qcom_iris *iris;
82
83	struct regulator_bulk_data *vregs;
84	size_t num_vregs;
85
86	struct completion start_done;
87	struct completion stop_done;
88
89	phys_addr_t mem_phys;
90	phys_addr_t mem_reloc;
91	void *mem_region;
92	size_t mem_size;
93
94	struct qcom_rproc_subdev smd_subdev;
95	struct qcom_sysmon *sysmon;
96};
97
98static const struct wcnss_data riva_data = {
99	.pmu_offset = 0x28,
100	.spare_offset = 0xb4,
101
102	.vregs = (struct wcnss_vreg_info[]) {
103		{ "vddmx",  1050000, 1150000, 0 },
104		{ "vddcx",  1050000, 1150000, 0 },
105		{ "vddpx",  1800000, 1800000, 0 },
106	},
107	.num_vregs = 3,
108};
109
110static const struct wcnss_data pronto_v1_data = {
111	.pmu_offset = 0x1004,
112	.spare_offset = 0x1088,
113
114	.vregs = (struct wcnss_vreg_info[]) {
115		{ "vddmx", 950000, 1150000, 0 },
116		{ "vddcx", .super_turbo = true},
117		{ "vddpx", 1800000, 1800000, 0 },
118	},
119	.num_vregs = 3,
120};
121
122static const struct wcnss_data pronto_v2_data = {
123	.pmu_offset = 0x1004,
124	.spare_offset = 0x1088,
125
126	.vregs = (struct wcnss_vreg_info[]) {
127		{ "vddmx", 1287500, 1287500, 0 },
128		{ "vddcx", .super_turbo = true },
129		{ "vddpx", 1800000, 1800000, 0 },
130	},
131	.num_vregs = 3,
132};
133
134void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
135			    struct qcom_iris *iris,
136			    bool use_48mhz_xo)
137{
138	mutex_lock(&wcnss->iris_lock);
139
140	wcnss->iris = iris;
141	wcnss->use_48mhz_xo = use_48mhz_xo;
142
143	mutex_unlock(&wcnss->iris_lock);
144}
145
146static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
147{
148	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
149	int ret;
150
151	ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
152			    wcnss->mem_region, wcnss->mem_phys,
153			    wcnss->mem_size, &wcnss->mem_reloc);
154	if (ret)
155		return ret;
156
157	qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
158
159	return 0;
160}
161
162static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
163{
164	u32 val;
165
166	/* Indicate NV download capability */
167	val = readl(wcnss->spare_out);
168	val |= WCNSS_SPARE_NVBIN_DLND;
169	writel(val, wcnss->spare_out);
170}
171
172static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
173{
174	u32 val;
175
176	/* Clear PMU cfg register */
177	writel(0, wcnss->pmu_cfg);
178
179	val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
180	writel(val, wcnss->pmu_cfg);
181
182	/* Clear XO_MODE */
183	val &= ~WCNSS_PMU_XO_MODE_MASK;
184	if (wcnss->use_48mhz_xo)
185		val |= WCNSS_PMU_XO_MODE_48 << 1;
186	else
187		val |= WCNSS_PMU_XO_MODE_19p2 << 1;
188	writel(val, wcnss->pmu_cfg);
189
190	/* Reset IRIS */
191	val |= WCNSS_PMU_IRIS_RESET;
192	writel(val, wcnss->pmu_cfg);
193
194	/* Wait for PMU.iris_reg_reset_sts */
195	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
196		cpu_relax();
197
198	/* Clear IRIS reset */
199	val &= ~WCNSS_PMU_IRIS_RESET;
200	writel(val, wcnss->pmu_cfg);
201
202	/* Start IRIS XO configuration */
203	val |= WCNSS_PMU_IRIS_XO_CFG;
204	writel(val, wcnss->pmu_cfg);
205
206	/* Wait for XO configuration to finish */
207	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
208		cpu_relax();
209
210	/* Stop IRIS XO configuration */
211	val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
212	val &= ~WCNSS_PMU_IRIS_XO_CFG;
213	writel(val, wcnss->pmu_cfg);
214
215	/* Add some delay for XO to settle */
216	msleep(20);
217}
218
219static int wcnss_start(struct rproc *rproc)
220{
221	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
222	int ret;
223
224	mutex_lock(&wcnss->iris_lock);
225	if (!wcnss->iris) {
226		dev_err(wcnss->dev, "no iris registered\n");
227		ret = -EINVAL;
228		goto release_iris_lock;
229	}
230
231	ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
232	if (ret)
233		goto release_iris_lock;
234
235	ret = qcom_iris_enable(wcnss->iris);
236	if (ret)
237		goto disable_regulators;
238
239	wcnss_indicate_nv_download(wcnss);
240	wcnss_configure_iris(wcnss);
241
242	ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
243	if (ret) {
244		dev_err(wcnss->dev,
245			"failed to authenticate image and release reset\n");
246		goto disable_iris;
247	}
248
249	ret = wait_for_completion_timeout(&wcnss->start_done,
250					  msecs_to_jiffies(5000));
251	if (wcnss->ready_irq > 0 && ret == 0) {
252		/* We have a ready_irq, but it didn't fire in time. */
253		dev_err(wcnss->dev, "start timed out\n");
254		qcom_scm_pas_shutdown(WCNSS_PAS_ID);
255		ret = -ETIMEDOUT;
256		goto disable_iris;
257	}
258
259	ret = 0;
260
261disable_iris:
262	qcom_iris_disable(wcnss->iris);
263disable_regulators:
264	regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
265release_iris_lock:
266	mutex_unlock(&wcnss->iris_lock);
267
268	return ret;
269}
270
271static int wcnss_stop(struct rproc *rproc)
272{
273	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
274	int ret;
275
276	if (wcnss->state) {
277		qcom_smem_state_update_bits(wcnss->state,
278					    BIT(wcnss->stop_bit),
279					    BIT(wcnss->stop_bit));
280
281		ret = wait_for_completion_timeout(&wcnss->stop_done,
282						  msecs_to_jiffies(5000));
283		if (ret == 0)
284			dev_err(wcnss->dev, "timed out on wait\n");
285
286		qcom_smem_state_update_bits(wcnss->state,
287					    BIT(wcnss->stop_bit),
288					    0);
289	}
290
291	ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
292	if (ret)
293		dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
294
295	return ret;
296}
297
298static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len)
299{
300	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
301	int offset;
302
303	offset = da - wcnss->mem_reloc;
304	if (offset < 0 || offset + len > wcnss->mem_size)
305		return NULL;
306
307	return wcnss->mem_region + offset;
308}
309
310static const struct rproc_ops wcnss_ops = {
311	.start = wcnss_start,
312	.stop = wcnss_stop,
313	.da_to_va = wcnss_da_to_va,
314	.parse_fw = qcom_register_dump_segments,
315	.load = wcnss_load,
316};
317
318static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
319{
320	struct qcom_wcnss *wcnss = dev;
321
322	rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
323
324	return IRQ_HANDLED;
325}
326
327static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
328{
329	struct qcom_wcnss *wcnss = dev;
330	size_t len;
331	char *msg;
332
333	msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
334	if (!IS_ERR(msg) && len > 0 && msg[0])
335		dev_err(wcnss->dev, "fatal error received: %s\n", msg);
336
337	rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
338
339	return IRQ_HANDLED;
340}
341
342static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
343{
344	struct qcom_wcnss *wcnss = dev;
345
346	complete(&wcnss->start_done);
347
348	return IRQ_HANDLED;
349}
350
351static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
352{
353	/*
354	 * XXX: At this point we're supposed to release the resources that we
355	 * have been holding on behalf of the WCNSS. Unfortunately this
356	 * interrupt comes way before the other side seems to be done.
357	 *
358	 * So we're currently relying on the ready interrupt firing later then
359	 * this and we just disable the resources at the end of wcnss_start().
360	 */
361
362	return IRQ_HANDLED;
363}
364
365static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
366{
367	struct qcom_wcnss *wcnss = dev;
368
369	complete(&wcnss->stop_done);
370
371	return IRQ_HANDLED;
372}
373
374static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
375				 const struct wcnss_vreg_info *info,
376				 int num_vregs)
377{
378	struct regulator_bulk_data *bulk;
379	int ret;
380	int i;
381
382	bulk = devm_kcalloc(wcnss->dev,
383			    num_vregs, sizeof(struct regulator_bulk_data),
384			    GFP_KERNEL);
385	if (!bulk)
386		return -ENOMEM;
387
388	for (i = 0; i < num_vregs; i++)
389		bulk[i].supply = info[i].name;
390
391	ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
392	if (ret)
393		return ret;
394
395	for (i = 0; i < num_vregs; i++) {
396		if (info[i].max_voltage)
397			regulator_set_voltage(bulk[i].consumer,
398					      info[i].min_voltage,
399					      info[i].max_voltage);
400
401		if (info[i].load_uA)
402			regulator_set_load(bulk[i].consumer, info[i].load_uA);
403	}
404
405	wcnss->vregs = bulk;
406	wcnss->num_vregs = num_vregs;
407
408	return 0;
409}
410
411static int wcnss_request_irq(struct qcom_wcnss *wcnss,
412			     struct platform_device *pdev,
413			     const char *name,
414			     bool optional,
415			     irq_handler_t thread_fn)
416{
417	int ret;
418	int irq_number;
419
420	ret = platform_get_irq_byname(pdev, name);
421	if (ret < 0 && optional) {
422		dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
423		return 0;
424	} else if (ret < 0) {
425		dev_err(&pdev->dev, "no %s IRQ defined\n", name);
426		return ret;
427	}
428
429	irq_number = ret;
430
431	ret = devm_request_threaded_irq(&pdev->dev, ret,
432					NULL, thread_fn,
433					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
434					"wcnss", wcnss);
435	if (ret) {
436		dev_err(&pdev->dev, "request %s IRQ failed\n", name);
437		return ret;
438	}
439
440	/* Return the IRQ number if the IRQ was successfully acquired */
441	return irq_number;
442}
443
444static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
445{
446	struct device_node *node;
447	struct resource r;
448	int ret;
449
450	node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
451	if (!node) {
452		dev_err(wcnss->dev, "no memory-region specified\n");
453		return -EINVAL;
454	}
455
456	ret = of_address_to_resource(node, 0, &r);
457	of_node_put(node);
458	if (ret)
459		return ret;
460
461	wcnss->mem_phys = wcnss->mem_reloc = r.start;
462	wcnss->mem_size = resource_size(&r);
463	wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
464	if (!wcnss->mem_region) {
465		dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
466			&r.start, wcnss->mem_size);
467		return -EBUSY;
468	}
469
470	return 0;
471}
472
473static int wcnss_probe(struct platform_device *pdev)
474{
475	const struct wcnss_data *data;
476	struct qcom_wcnss *wcnss;
477	struct resource *res;
478	struct rproc *rproc;
479	void __iomem *mmio;
480	int ret;
481
482	data = of_device_get_match_data(&pdev->dev);
483
484	if (!qcom_scm_is_available())
485		return -EPROBE_DEFER;
486
487	if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
488		dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
489		return -ENXIO;
490	}
491
492	rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
493			    WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
494	if (!rproc) {
495		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
496		return -ENOMEM;
497	}
498	rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
499
500	wcnss = (struct qcom_wcnss *)rproc->priv;
501	wcnss->dev = &pdev->dev;
502	wcnss->rproc = rproc;
503	platform_set_drvdata(pdev, wcnss);
504
505	init_completion(&wcnss->start_done);
506	init_completion(&wcnss->stop_done);
507
508	mutex_init(&wcnss->iris_lock);
509
510	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
511	mmio = devm_ioremap_resource(&pdev->dev, res);
512	if (IS_ERR(mmio)) {
513		ret = PTR_ERR(mmio);
514		goto free_rproc;
515	};
516
517	ret = wcnss_alloc_memory_region(wcnss);
518	if (ret)
519		goto free_rproc;
520
521	wcnss->pmu_cfg = mmio + data->pmu_offset;
522	wcnss->spare_out = mmio + data->spare_offset;
523
524	ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
525	if (ret)
526		goto free_rproc;
527
528	ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
529	if (ret < 0)
530		goto free_rproc;
531	wcnss->wdog_irq = ret;
532
533	ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
534	if (ret < 0)
535		goto free_rproc;
536	wcnss->fatal_irq = ret;
537
538	ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
539	if (ret < 0)
540		goto free_rproc;
541	wcnss->ready_irq = ret;
542
543	ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
544	if (ret < 0)
545		goto free_rproc;
546	wcnss->handover_irq = ret;
547
548	ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
549	if (ret < 0)
550		goto free_rproc;
551	wcnss->stop_ack_irq = ret;
552
553	if (wcnss->stop_ack_irq) {
554		wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
555						   &wcnss->stop_bit);
556		if (IS_ERR(wcnss->state)) {
557			ret = PTR_ERR(wcnss->state);
558			goto free_rproc;
559		}
560	}
561
562	qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
563	wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
564	if (IS_ERR(wcnss->sysmon)) {
565		ret = PTR_ERR(wcnss->sysmon);
566		goto free_rproc;
567	}
568
569	ret = rproc_add(rproc);
570	if (ret)
571		goto free_rproc;
572
573	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
574
575free_rproc:
576	rproc_free(rproc);
577
578	return ret;
579}
580
581static int wcnss_remove(struct platform_device *pdev)
582{
583	struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
584
585	of_platform_depopulate(&pdev->dev);
586
587	qcom_smem_state_put(wcnss->state);
588	rproc_del(wcnss->rproc);
589
590	qcom_remove_sysmon_subdev(wcnss->sysmon);
591	qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
592	rproc_free(wcnss->rproc);
593
594	return 0;
595}
596
597static const struct of_device_id wcnss_of_match[] = {
598	{ .compatible = "qcom,riva-pil", &riva_data },
599	{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
600	{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
601	{ },
602};
603MODULE_DEVICE_TABLE(of, wcnss_of_match);
604
605static struct platform_driver wcnss_driver = {
606	.probe = wcnss_probe,
607	.remove = wcnss_remove,
608	.driver = {
609		.name = "qcom-wcnss-pil",
610		.of_match_table = wcnss_of_match,
611	},
612};
613
614static int __init wcnss_init(void)
615{
616	int ret;
617
618	ret = platform_driver_register(&wcnss_driver);
619	if (ret)
620		return ret;
621
622	ret = platform_driver_register(&qcom_iris_driver);
623	if (ret)
624		platform_driver_unregister(&wcnss_driver);
625
626	return ret;
627}
628module_init(wcnss_init);
629
630static void __exit wcnss_exit(void)
631{
632	platform_driver_unregister(&qcom_iris_driver);
633	platform_driver_unregister(&wcnss_driver);
634}
635module_exit(wcnss_exit);
636
637MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
638MODULE_LICENSE("GPL v2");
639