1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996 4 * 5 * Copyright (C) 2016 Linaro Ltd 6 * Copyright (C) 2014 Sony Mobile Communications AB 7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 8 */ 9 10#include <linux/clk.h> 11#include <linux/firmware.h> 12#include <linux/interrupt.h> 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/of_address.h> 16#include <linux/of_device.h> 17#include <linux/platform_device.h> 18#include <linux/pm_domain.h> 19#include <linux/pm_runtime.h> 20#include <linux/qcom_scm.h> 21#include <linux/regulator/consumer.h> 22#include <linux/remoteproc.h> 23#include <linux/soc/qcom/mdt_loader.h> 24#include <linux/soc/qcom/smem.h> 25#include <linux/soc/qcom/smem_state.h> 26 27#include "qcom_common.h" 28#include "qcom_pil_info.h" 29#include "qcom_q6v5.h" 30#include "remoteproc_internal.h" 31 32struct adsp_data { 33 int crash_reason_smem; 34 const char *firmware_name; 35 int pas_id; 36 bool has_aggre2_clk; 37 bool auto_boot; 38 39 char **active_pd_names; 40 char **proxy_pd_names; 41 42 const char *ssr_name; 43 const char *sysmon_name; 44 int ssctl_id; 45}; 46 47struct qcom_adsp { 48 struct device *dev; 49 struct rproc *rproc; 50 51 struct qcom_q6v5 q6v5; 52 53 struct clk *xo; 54 struct clk *aggre2_clk; 55 56 struct regulator *cx_supply; 57 struct regulator *px_supply; 58 59 struct device *active_pds[1]; 60 struct device *proxy_pds[3]; 61 62 int active_pd_count; 63 int proxy_pd_count; 64 65 int pas_id; 66 int crash_reason_smem; 67 bool has_aggre2_clk; 68 const char *info_name; 69 70 struct completion start_done; 71 struct completion stop_done; 72 73 phys_addr_t mem_phys; 74 phys_addr_t mem_reloc; 75 void *mem_region; 76 size_t mem_size; 77 78 struct qcom_rproc_glink glink_subdev; 79 struct qcom_rproc_subdev smd_subdev; 80 struct qcom_rproc_ssr ssr_subdev; 81 struct qcom_sysmon *sysmon; 82}; 83 84static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds, 85 size_t pd_count) 86{ 87 int ret; 88 int i; 89 90 for (i = 0; i < pd_count; i++) { 91 dev_pm_genpd_set_performance_state(pds[i], INT_MAX); 92 ret = pm_runtime_get_sync(pds[i]); 93 if (ret < 0) { 94 pm_runtime_put_noidle(pds[i]); 95 dev_pm_genpd_set_performance_state(pds[i], 0); 96 goto unroll_pd_votes; 97 } 98 } 99 100 return 0; 101 102unroll_pd_votes: 103 for (i--; i >= 0; i--) { 104 dev_pm_genpd_set_performance_state(pds[i], 0); 105 pm_runtime_put(pds[i]); 106 } 107 108 return ret; 109}; 110 111static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds, 112 size_t pd_count) 113{ 114 int i; 115 116 for (i = 0; i < pd_count; i++) { 117 dev_pm_genpd_set_performance_state(pds[i], 0); 118 pm_runtime_put(pds[i]); 119 } 120} 121 122static int adsp_load(struct rproc *rproc, const struct firmware *fw) 123{ 124 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 125 int ret; 126 127 ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id, 128 adsp->mem_region, adsp->mem_phys, adsp->mem_size, 129 &adsp->mem_reloc); 130 if (ret) 131 return ret; 132 133 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); 134 135 return 0; 136} 137 138static int adsp_start(struct rproc *rproc) 139{ 140 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 141 int ret; 142 143 qcom_q6v5_prepare(&adsp->q6v5); 144 145 ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count); 146 if (ret < 0) 147 goto disable_irqs; 148 149 ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 150 if (ret < 0) 151 goto disable_active_pds; 152 153 ret = clk_prepare_enable(adsp->xo); 154 if (ret) 155 goto disable_proxy_pds; 156 157 ret = clk_prepare_enable(adsp->aggre2_clk); 158 if (ret) 159 goto disable_xo_clk; 160 161 ret = regulator_enable(adsp->cx_supply); 162 if (ret) 163 goto disable_aggre2_clk; 164 165 ret = regulator_enable(adsp->px_supply); 166 if (ret) 167 goto disable_cx_supply; 168 169 ret = qcom_scm_pas_auth_and_reset(adsp->pas_id); 170 if (ret) { 171 dev_err(adsp->dev, 172 "failed to authenticate image and release reset\n"); 173 goto disable_px_supply; 174 } 175 176 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000)); 177 if (ret == -ETIMEDOUT) { 178 dev_err(adsp->dev, "start timed out\n"); 179 qcom_scm_pas_shutdown(adsp->pas_id); 180 goto disable_px_supply; 181 } 182 183 return 0; 184 185disable_px_supply: 186 regulator_disable(adsp->px_supply); 187disable_cx_supply: 188 regulator_disable(adsp->cx_supply); 189disable_aggre2_clk: 190 clk_disable_unprepare(adsp->aggre2_clk); 191disable_xo_clk: 192 clk_disable_unprepare(adsp->xo); 193disable_proxy_pds: 194 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 195disable_active_pds: 196 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count); 197disable_irqs: 198 qcom_q6v5_unprepare(&adsp->q6v5); 199 200 return ret; 201} 202 203static void qcom_pas_handover(struct qcom_q6v5 *q6v5) 204{ 205 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); 206 207 regulator_disable(adsp->px_supply); 208 regulator_disable(adsp->cx_supply); 209 clk_disable_unprepare(adsp->aggre2_clk); 210 clk_disable_unprepare(adsp->xo); 211 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 212} 213 214static int adsp_stop(struct rproc *rproc) 215{ 216 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 217 int handover; 218 int ret; 219 220 ret = qcom_q6v5_request_stop(&adsp->q6v5); 221 if (ret == -ETIMEDOUT) 222 dev_err(adsp->dev, "timed out on wait\n"); 223 224 ret = qcom_scm_pas_shutdown(adsp->pas_id); 225 if (ret) 226 dev_err(adsp->dev, "failed to shutdown: %d\n", ret); 227 228 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count); 229 handover = qcom_q6v5_unprepare(&adsp->q6v5); 230 if (handover) 231 qcom_pas_handover(&adsp->q6v5); 232 233 return ret; 234} 235 236static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len) 237{ 238 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 239 int offset; 240 241 offset = da - adsp->mem_reloc; 242 if (offset < 0 || offset + len > adsp->mem_size) 243 return NULL; 244 245 return adsp->mem_region + offset; 246} 247 248static unsigned long adsp_panic(struct rproc *rproc) 249{ 250 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; 251 252 return qcom_q6v5_panic(&adsp->q6v5); 253} 254 255static const struct rproc_ops adsp_ops = { 256 .start = adsp_start, 257 .stop = adsp_stop, 258 .da_to_va = adsp_da_to_va, 259 .parse_fw = qcom_register_dump_segments, 260 .load = adsp_load, 261 .panic = adsp_panic, 262}; 263 264static int adsp_init_clock(struct qcom_adsp *adsp) 265{ 266 int ret; 267 268 adsp->xo = devm_clk_get(adsp->dev, "xo"); 269 if (IS_ERR(adsp->xo)) { 270 ret = PTR_ERR(adsp->xo); 271 if (ret != -EPROBE_DEFER) 272 dev_err(adsp->dev, "failed to get xo clock"); 273 return ret; 274 } 275 276 if (adsp->has_aggre2_clk) { 277 adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2"); 278 if (IS_ERR(adsp->aggre2_clk)) { 279 ret = PTR_ERR(adsp->aggre2_clk); 280 if (ret != -EPROBE_DEFER) 281 dev_err(adsp->dev, 282 "failed to get aggre2 clock"); 283 return ret; 284 } 285 } 286 287 return 0; 288} 289 290static int adsp_init_regulator(struct qcom_adsp *adsp) 291{ 292 adsp->cx_supply = devm_regulator_get(adsp->dev, "cx"); 293 if (IS_ERR(adsp->cx_supply)) 294 return PTR_ERR(adsp->cx_supply); 295 296 regulator_set_load(adsp->cx_supply, 100000); 297 298 adsp->px_supply = devm_regulator_get(adsp->dev, "px"); 299 return PTR_ERR_OR_ZERO(adsp->px_supply); 300} 301 302static int adsp_pds_attach(struct device *dev, struct device **devs, 303 char **pd_names) 304{ 305 size_t num_pds = 0; 306 int ret; 307 int i; 308 309 if (!pd_names) 310 return 0; 311 312 /* Handle single power domain */ 313 if (dev->pm_domain) { 314 devs[0] = dev; 315 pm_runtime_enable(dev); 316 return 1; 317 } 318 319 while (pd_names[num_pds]) 320 num_pds++; 321 322 for (i = 0; i < num_pds; i++) { 323 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); 324 if (IS_ERR_OR_NULL(devs[i])) { 325 ret = PTR_ERR(devs[i]) ? : -ENODATA; 326 goto unroll_attach; 327 } 328 } 329 330 return num_pds; 331 332unroll_attach: 333 for (i--; i >= 0; i--) 334 dev_pm_domain_detach(devs[i], false); 335 336 return ret; 337}; 338 339static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds, 340 size_t pd_count) 341{ 342 struct device *dev = adsp->dev; 343 int i; 344 345 /* Handle single power domain */ 346 if (dev->pm_domain && pd_count) { 347 pm_runtime_disable(dev); 348 return; 349 } 350 351 for (i = 0; i < pd_count; i++) 352 dev_pm_domain_detach(pds[i], false); 353} 354 355static int adsp_alloc_memory_region(struct qcom_adsp *adsp) 356{ 357 struct device_node *node; 358 struct resource r; 359 int ret; 360 361 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0); 362 if (!node) { 363 dev_err(adsp->dev, "no memory-region specified\n"); 364 return -EINVAL; 365 } 366 367 ret = of_address_to_resource(node, 0, &r); 368 of_node_put(node); 369 if (ret) 370 return ret; 371 372 adsp->mem_phys = adsp->mem_reloc = r.start; 373 adsp->mem_size = resource_size(&r); 374 adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size); 375 if (!adsp->mem_region) { 376 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n", 377 &r.start, adsp->mem_size); 378 return -EBUSY; 379 } 380 381 return 0; 382} 383 384static int adsp_probe(struct platform_device *pdev) 385{ 386 const struct adsp_data *desc; 387 struct qcom_adsp *adsp; 388 struct rproc *rproc; 389 const char *fw_name; 390 int ret; 391 392 desc = of_device_get_match_data(&pdev->dev); 393 if (!desc) 394 return -EINVAL; 395 396 if (!qcom_scm_is_available()) 397 return -EPROBE_DEFER; 398 399 fw_name = desc->firmware_name; 400 ret = of_property_read_string(pdev->dev.of_node, "firmware-name", 401 &fw_name); 402 if (ret < 0 && ret != -EINVAL) 403 return ret; 404 405 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops, 406 fw_name, sizeof(*adsp)); 407 if (!rproc) { 408 dev_err(&pdev->dev, "unable to allocate remoteproc\n"); 409 return -ENOMEM; 410 } 411 412 rproc->auto_boot = desc->auto_boot; 413 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); 414 415 adsp = (struct qcom_adsp *)rproc->priv; 416 adsp->dev = &pdev->dev; 417 adsp->rproc = rproc; 418 adsp->pas_id = desc->pas_id; 419 adsp->has_aggre2_clk = desc->has_aggre2_clk; 420 adsp->info_name = desc->sysmon_name; 421 platform_set_drvdata(pdev, adsp); 422 423 device_wakeup_enable(adsp->dev); 424 425 ret = adsp_alloc_memory_region(adsp); 426 if (ret) 427 goto free_rproc; 428 429 ret = adsp_init_clock(adsp); 430 if (ret) 431 goto free_rproc; 432 433 ret = adsp_init_regulator(adsp); 434 if (ret) 435 goto free_rproc; 436 437 ret = adsp_pds_attach(&pdev->dev, adsp->active_pds, 438 desc->active_pd_names); 439 if (ret < 0) 440 goto free_rproc; 441 adsp->active_pd_count = ret; 442 443 ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds, 444 desc->proxy_pd_names); 445 if (ret < 0) 446 goto detach_active_pds; 447 adsp->proxy_pd_count = ret; 448 449 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, 450 qcom_pas_handover); 451 if (ret) 452 goto detach_proxy_pds; 453 454 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); 455 qcom_add_smd_subdev(rproc, &adsp->smd_subdev); 456 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); 457 adsp->sysmon = qcom_add_sysmon_subdev(rproc, 458 desc->sysmon_name, 459 desc->ssctl_id); 460 if (IS_ERR(adsp->sysmon)) { 461 ret = PTR_ERR(adsp->sysmon); 462 goto detach_proxy_pds; 463 } 464 465 ret = rproc_add(rproc); 466 if (ret) 467 goto detach_proxy_pds; 468 469 return 0; 470 471detach_proxy_pds: 472 adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 473detach_active_pds: 474 adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count); 475free_rproc: 476 device_init_wakeup(adsp->dev, false); 477 rproc_free(rproc); 478 479 return ret; 480} 481 482static int adsp_remove(struct platform_device *pdev) 483{ 484 struct qcom_adsp *adsp = platform_get_drvdata(pdev); 485 486 rproc_del(adsp->rproc); 487 488 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); 489 qcom_remove_sysmon_subdev(adsp->sysmon); 490 qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev); 491 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); 492 adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); 493 device_init_wakeup(adsp->dev, false); 494 rproc_free(adsp->rproc); 495 496 return 0; 497} 498 499static const struct adsp_data adsp_resource_init = { 500 .crash_reason_smem = 423, 501 .firmware_name = "adsp.mdt", 502 .pas_id = 1, 503 .has_aggre2_clk = false, 504 .auto_boot = true, 505 .ssr_name = "lpass", 506 .sysmon_name = "adsp", 507 .ssctl_id = 0x14, 508}; 509 510static const struct adsp_data sm8150_adsp_resource = { 511 .crash_reason_smem = 423, 512 .firmware_name = "adsp.mdt", 513 .pas_id = 1, 514 .has_aggre2_clk = false, 515 .auto_boot = true, 516 .active_pd_names = (char*[]){ 517 "load_state", 518 NULL 519 }, 520 .proxy_pd_names = (char*[]){ 521 "cx", 522 NULL 523 }, 524 .ssr_name = "lpass", 525 .sysmon_name = "adsp", 526 .ssctl_id = 0x14, 527}; 528 529static const struct adsp_data sm8250_adsp_resource = { 530 .crash_reason_smem = 423, 531 .firmware_name = "adsp.mdt", 532 .pas_id = 1, 533 .has_aggre2_clk = false, 534 .auto_boot = true, 535 .active_pd_names = (char*[]){ 536 "load_state", 537 NULL 538 }, 539 .proxy_pd_names = (char*[]){ 540 "lcx", 541 "lmx", 542 NULL 543 }, 544 .ssr_name = "lpass", 545 .sysmon_name = "adsp", 546 .ssctl_id = 0x14, 547}; 548 549static const struct adsp_data msm8998_adsp_resource = { 550 .crash_reason_smem = 423, 551 .firmware_name = "adsp.mdt", 552 .pas_id = 1, 553 .has_aggre2_clk = false, 554 .auto_boot = true, 555 .proxy_pd_names = (char*[]){ 556 "cx", 557 NULL 558 }, 559 .ssr_name = "lpass", 560 .sysmon_name = "adsp", 561 .ssctl_id = 0x14, 562}; 563 564static const struct adsp_data cdsp_resource_init = { 565 .crash_reason_smem = 601, 566 .firmware_name = "cdsp.mdt", 567 .pas_id = 18, 568 .has_aggre2_clk = false, 569 .auto_boot = true, 570 .ssr_name = "cdsp", 571 .sysmon_name = "cdsp", 572 .ssctl_id = 0x17, 573}; 574 575static const struct adsp_data sm8150_cdsp_resource = { 576 .crash_reason_smem = 601, 577 .firmware_name = "cdsp.mdt", 578 .pas_id = 18, 579 .has_aggre2_clk = false, 580 .auto_boot = true, 581 .active_pd_names = (char*[]){ 582 "load_state", 583 NULL 584 }, 585 .proxy_pd_names = (char*[]){ 586 "cx", 587 NULL 588 }, 589 .ssr_name = "cdsp", 590 .sysmon_name = "cdsp", 591 .ssctl_id = 0x17, 592}; 593 594static const struct adsp_data sm8250_cdsp_resource = { 595 .crash_reason_smem = 601, 596 .firmware_name = "cdsp.mdt", 597 .pas_id = 18, 598 .has_aggre2_clk = false, 599 .auto_boot = true, 600 .active_pd_names = (char*[]){ 601 "load_state", 602 NULL 603 }, 604 .proxy_pd_names = (char*[]){ 605 "cx", 606 NULL 607 }, 608 .ssr_name = "cdsp", 609 .sysmon_name = "cdsp", 610 .ssctl_id = 0x17, 611}; 612 613static const struct adsp_data mpss_resource_init = { 614 .crash_reason_smem = 421, 615 .firmware_name = "modem.mdt", 616 .pas_id = 4, 617 .has_aggre2_clk = false, 618 .auto_boot = false, 619 .active_pd_names = (char*[]){ 620 "load_state", 621 NULL 622 }, 623 .proxy_pd_names = (char*[]){ 624 "cx", 625 "mss", 626 NULL 627 }, 628 .ssr_name = "mpss", 629 .sysmon_name = "modem", 630 .ssctl_id = 0x12, 631}; 632 633static const struct adsp_data slpi_resource_init = { 634 .crash_reason_smem = 424, 635 .firmware_name = "slpi.mdt", 636 .pas_id = 12, 637 .has_aggre2_clk = true, 638 .auto_boot = true, 639 .ssr_name = "dsps", 640 .sysmon_name = "slpi", 641 .ssctl_id = 0x16, 642}; 643 644static const struct adsp_data sm8150_slpi_resource = { 645 .crash_reason_smem = 424, 646 .firmware_name = "slpi.mdt", 647 .pas_id = 12, 648 .has_aggre2_clk = false, 649 .auto_boot = true, 650 .active_pd_names = (char*[]){ 651 "load_state", 652 NULL 653 }, 654 .proxy_pd_names = (char*[]){ 655 "lcx", 656 "lmx", 657 NULL 658 }, 659 .ssr_name = "dsps", 660 .sysmon_name = "slpi", 661 .ssctl_id = 0x16, 662}; 663 664static const struct adsp_data sm8250_slpi_resource = { 665 .crash_reason_smem = 424, 666 .firmware_name = "slpi.mdt", 667 .pas_id = 12, 668 .has_aggre2_clk = false, 669 .auto_boot = true, 670 .active_pd_names = (char*[]){ 671 "load_state", 672 NULL 673 }, 674 .proxy_pd_names = (char*[]){ 675 "lcx", 676 "lmx", 677 NULL 678 }, 679 .ssr_name = "dsps", 680 .sysmon_name = "slpi", 681 .ssctl_id = 0x16, 682}; 683 684static const struct adsp_data msm8998_slpi_resource = { 685 .crash_reason_smem = 424, 686 .firmware_name = "slpi.mdt", 687 .pas_id = 12, 688 .has_aggre2_clk = true, 689 .auto_boot = true, 690 .proxy_pd_names = (char*[]){ 691 "ssc_cx", 692 NULL 693 }, 694 .ssr_name = "dsps", 695 .sysmon_name = "slpi", 696 .ssctl_id = 0x16, 697}; 698 699static const struct adsp_data wcss_resource_init = { 700 .crash_reason_smem = 421, 701 .firmware_name = "wcnss.mdt", 702 .pas_id = 6, 703 .auto_boot = true, 704 .ssr_name = "mpss", 705 .sysmon_name = "wcnss", 706 .ssctl_id = 0x12, 707}; 708 709static const struct of_device_id adsp_of_match[] = { 710 { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init}, 711 { .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init}, 712 { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init}, 713 { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource}, 714 { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource}, 715 { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init }, 716 { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init }, 717 { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init }, 718 { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init}, 719 { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init}, 720 { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init}, 721 { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource}, 722 { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource}, 723 { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init}, 724 { .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource}, 725 { .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource}, 726 { .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource}, 727 { .compatible = "qcom,sm8250-slpi-pas", .data = &sm8250_slpi_resource}, 728 { }, 729}; 730MODULE_DEVICE_TABLE(of, adsp_of_match); 731 732static struct platform_driver adsp_driver = { 733 .probe = adsp_probe, 734 .remove = adsp_remove, 735 .driver = { 736 .name = "qcom_q6v5_pas", 737 .of_match_table = adsp_of_match, 738 }, 739}; 740 741module_platform_driver(adsp_driver); 742MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver"); 743MODULE_LICENSE("GPL v2"); 744