1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, Sony Mobile Communications AB. 4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/of_device.h> 10#include <linux/platform_device.h> 11#include <linux/regulator/driver.h> 12#include <linux/regulator/of_regulator.h> 13#include <linux/soc/qcom/smd-rpm.h> 14 15struct qcom_rpm_reg { 16 struct device *dev; 17 18 struct qcom_smd_rpm *rpm; 19 20 u32 type; 21 u32 id; 22 23 struct regulator_desc desc; 24 25 int is_enabled; 26 int uV; 27 u32 load; 28 29 unsigned int enabled_updated:1; 30 unsigned int uv_updated:1; 31 unsigned int load_updated:1; 32}; 33 34struct rpm_regulator_req { 35 __le32 key; 36 __le32 nbytes; 37 __le32 value; 38}; 39 40#define RPM_KEY_SWEN 0x6e657773 /* "swen" */ 41#define RPM_KEY_UV 0x00007675 /* "uv" */ 42#define RPM_KEY_MA 0x0000616d /* "ma" */ 43 44static int rpm_reg_write_active(struct qcom_rpm_reg *vreg) 45{ 46 struct rpm_regulator_req req[3]; 47 int reqlen = 0; 48 int ret; 49 50 if (vreg->enabled_updated) { 51 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN); 52 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 53 req[reqlen].value = cpu_to_le32(vreg->is_enabled); 54 reqlen++; 55 } 56 57 if (vreg->uv_updated && vreg->is_enabled) { 58 req[reqlen].key = cpu_to_le32(RPM_KEY_UV); 59 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 60 req[reqlen].value = cpu_to_le32(vreg->uV); 61 reqlen++; 62 } 63 64 if (vreg->load_updated && vreg->is_enabled) { 65 req[reqlen].key = cpu_to_le32(RPM_KEY_MA); 66 req[reqlen].nbytes = cpu_to_le32(sizeof(u32)); 67 req[reqlen].value = cpu_to_le32(vreg->load / 1000); 68 reqlen++; 69 } 70 71 if (!reqlen) 72 return 0; 73 74 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 75 vreg->type, vreg->id, 76 req, sizeof(req[0]) * reqlen); 77 if (!ret) { 78 vreg->enabled_updated = 0; 79 vreg->uv_updated = 0; 80 vreg->load_updated = 0; 81 } 82 83 return ret; 84} 85 86static int rpm_reg_enable(struct regulator_dev *rdev) 87{ 88 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 89 int ret; 90 91 vreg->is_enabled = 1; 92 vreg->enabled_updated = 1; 93 94 ret = rpm_reg_write_active(vreg); 95 if (ret) 96 vreg->is_enabled = 0; 97 98 return ret; 99} 100 101static int rpm_reg_is_enabled(struct regulator_dev *rdev) 102{ 103 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 104 105 return vreg->is_enabled; 106} 107 108static int rpm_reg_disable(struct regulator_dev *rdev) 109{ 110 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 111 int ret; 112 113 vreg->is_enabled = 0; 114 vreg->enabled_updated = 1; 115 116 ret = rpm_reg_write_active(vreg); 117 if (ret) 118 vreg->is_enabled = 1; 119 120 return ret; 121} 122 123static int rpm_reg_get_voltage(struct regulator_dev *rdev) 124{ 125 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 126 127 return vreg->uV; 128} 129 130static int rpm_reg_set_voltage(struct regulator_dev *rdev, 131 int min_uV, 132 int max_uV, 133 unsigned *selector) 134{ 135 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 136 int ret; 137 int old_uV = vreg->uV; 138 139 vreg->uV = min_uV; 140 vreg->uv_updated = 1; 141 142 ret = rpm_reg_write_active(vreg); 143 if (ret) 144 vreg->uV = old_uV; 145 146 return ret; 147} 148 149static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA) 150{ 151 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev); 152 u32 old_load = vreg->load; 153 int ret; 154 155 vreg->load = load_uA; 156 vreg->load_updated = 1; 157 ret = rpm_reg_write_active(vreg); 158 if (ret) 159 vreg->load = old_load; 160 161 return ret; 162} 163 164static const struct regulator_ops rpm_smps_ldo_ops = { 165 .enable = rpm_reg_enable, 166 .disable = rpm_reg_disable, 167 .is_enabled = rpm_reg_is_enabled, 168 .list_voltage = regulator_list_voltage_linear_range, 169 170 .get_voltage = rpm_reg_get_voltage, 171 .set_voltage = rpm_reg_set_voltage, 172 173 .set_load = rpm_reg_set_load, 174}; 175 176static const struct regulator_ops rpm_smps_ldo_ops_fixed = { 177 .enable = rpm_reg_enable, 178 .disable = rpm_reg_disable, 179 .is_enabled = rpm_reg_is_enabled, 180 181 .get_voltage = rpm_reg_get_voltage, 182 .set_voltage = rpm_reg_set_voltage, 183 184 .set_load = rpm_reg_set_load, 185}; 186 187static const struct regulator_ops rpm_switch_ops = { 188 .enable = rpm_reg_enable, 189 .disable = rpm_reg_disable, 190 .is_enabled = rpm_reg_is_enabled, 191}; 192 193static const struct regulator_ops rpm_bob_ops = { 194 .enable = rpm_reg_enable, 195 .disable = rpm_reg_disable, 196 .is_enabled = rpm_reg_is_enabled, 197 198 .get_voltage = rpm_reg_get_voltage, 199 .set_voltage = rpm_reg_set_voltage, 200}; 201 202static const struct regulator_ops rpm_mp5496_ops = { 203 .enable = rpm_reg_enable, 204 .disable = rpm_reg_disable, 205 .is_enabled = rpm_reg_is_enabled, 206 .list_voltage = regulator_list_voltage_linear_range, 207 208 .set_voltage = rpm_reg_set_voltage, 209}; 210 211static const struct regulator_desc pma8084_hfsmps = { 212 .linear_ranges = (struct linear_range[]) { 213 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 214 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000), 215 }, 216 .n_linear_ranges = 2, 217 .n_voltages = 159, 218 .ops = &rpm_smps_ldo_ops, 219}; 220 221static const struct regulator_desc pma8084_ftsmps = { 222 .linear_ranges = (struct linear_range[]) { 223 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000), 224 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000), 225 }, 226 .n_linear_ranges = 2, 227 .n_voltages = 262, 228 .ops = &rpm_smps_ldo_ops, 229}; 230 231static const struct regulator_desc pma8084_pldo = { 232 .linear_ranges = (struct linear_range[]) { 233 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 234 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 235 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 236 }, 237 .n_linear_ranges = 3, 238 .n_voltages = 164, 239 .ops = &rpm_smps_ldo_ops, 240}; 241 242static const struct regulator_desc pma8084_nldo = { 243 .linear_ranges = (struct linear_range[]) { 244 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 245 }, 246 .n_linear_ranges = 1, 247 .n_voltages = 64, 248 .ops = &rpm_smps_ldo_ops, 249}; 250 251static const struct regulator_desc pma8084_switch = { 252 .ops = &rpm_switch_ops, 253}; 254 255static const struct regulator_desc pm8x41_hfsmps = { 256 .linear_ranges = (struct linear_range[]) { 257 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500), 258 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000), 259 }, 260 .n_linear_ranges = 2, 261 .n_voltages = 159, 262 .ops = &rpm_smps_ldo_ops, 263}; 264 265static const struct regulator_desc pm8841_ftsmps = { 266 .linear_ranges = (struct linear_range[]) { 267 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000), 268 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000), 269 }, 270 .n_linear_ranges = 2, 271 .n_voltages = 262, 272 .ops = &rpm_smps_ldo_ops, 273}; 274 275static const struct regulator_desc pm8941_boost = { 276 .linear_ranges = (struct linear_range[]) { 277 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000), 278 }, 279 .n_linear_ranges = 1, 280 .n_voltages = 31, 281 .ops = &rpm_smps_ldo_ops, 282}; 283 284static const struct regulator_desc pm8941_pldo = { 285 .linear_ranges = (struct linear_range[]) { 286 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 287 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 288 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 289 }, 290 .n_linear_ranges = 3, 291 .n_voltages = 164, 292 .ops = &rpm_smps_ldo_ops, 293}; 294 295static const struct regulator_desc pm8941_nldo = { 296 .linear_ranges = (struct linear_range[]) { 297 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 298 }, 299 .n_linear_ranges = 1, 300 .n_voltages = 64, 301 .ops = &rpm_smps_ldo_ops, 302}; 303 304static const struct regulator_desc pm8941_lnldo = { 305 .fixed_uV = 1740000, 306 .n_voltages = 1, 307 .ops = &rpm_smps_ldo_ops_fixed, 308}; 309 310static const struct regulator_desc pm8941_switch = { 311 .ops = &rpm_switch_ops, 312}; 313 314static const struct regulator_desc pm8916_pldo = { 315 .linear_ranges = (struct linear_range[]) { 316 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500), 317 }, 318 .n_linear_ranges = 1, 319 .n_voltages = 128, 320 .ops = &rpm_smps_ldo_ops, 321}; 322 323static const struct regulator_desc pm8916_nldo = { 324 .linear_ranges = (struct linear_range[]) { 325 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500), 326 }, 327 .n_linear_ranges = 1, 328 .n_voltages = 94, 329 .ops = &rpm_smps_ldo_ops, 330}; 331 332static const struct regulator_desc pm8916_buck_lvo_smps = { 333 .linear_ranges = (struct linear_range[]) { 334 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 335 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000), 336 }, 337 .n_linear_ranges = 2, 338 .n_voltages = 128, 339 .ops = &rpm_smps_ldo_ops, 340}; 341 342static const struct regulator_desc pm8916_buck_hvo_smps = { 343 .linear_ranges = (struct linear_range[]) { 344 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000), 345 }, 346 .n_linear_ranges = 1, 347 .n_voltages = 32, 348 .ops = &rpm_smps_ldo_ops, 349}; 350 351static const struct regulator_desc pm8950_hfsmps = { 352 .linear_ranges = (struct linear_range[]) { 353 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), 354 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000), 355 }, 356 .n_linear_ranges = 2, 357 .n_voltages = 128, 358 .ops = &rpm_smps_ldo_ops, 359}; 360 361static const struct regulator_desc pm8950_ftsmps2p5 = { 362 .linear_ranges = (struct linear_range[]) { 363 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000), 364 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000), 365 }, 366 .n_linear_ranges = 2, 367 .n_voltages = 461, 368 .ops = &rpm_smps_ldo_ops, 369}; 370 371static const struct regulator_desc pm8950_ult_nldo = { 372 .linear_ranges = (struct linear_range[]) { 373 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500), 374 }, 375 .n_linear_ranges = 1, 376 .n_voltages = 203, 377 .ops = &rpm_smps_ldo_ops, 378}; 379 380static const struct regulator_desc pm8950_ult_pldo = { 381 .linear_ranges = (struct linear_range[]) { 382 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500), 383 }, 384 .n_linear_ranges = 1, 385 .n_voltages = 128, 386 .ops = &rpm_smps_ldo_ops, 387}; 388 389static const struct regulator_desc pm8950_pldo_lv = { 390 .linear_ranges = (struct linear_range[]) { 391 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000), 392 }, 393 .n_linear_ranges = 1, 394 .n_voltages = 17, 395 .ops = &rpm_smps_ldo_ops, 396}; 397 398static const struct regulator_desc pm8950_pldo = { 399 .linear_ranges = (struct linear_range[]) { 400 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500), 401 }, 402 .n_linear_ranges = 1, 403 .n_voltages = 165, 404 .ops = &rpm_smps_ldo_ops, 405}; 406 407static const struct regulator_desc pm8953_lnldo = { 408 .linear_ranges = (struct linear_range[]) { 409 REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000), 410 REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000), 411 }, 412 .n_linear_ranges = 2, 413 .n_voltages = 16, 414 .ops = &rpm_smps_ldo_ops, 415}; 416 417static const struct regulator_desc pm8953_ult_nldo = { 418 .linear_ranges = (struct linear_range[]) { 419 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500), 420 }, 421 .n_linear_ranges = 1, 422 .n_voltages = 94, 423 .ops = &rpm_smps_ldo_ops, 424}; 425 426static const struct regulator_desc pm8994_hfsmps = { 427 .linear_ranges = (struct linear_range[]) { 428 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500), 429 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000), 430 }, 431 .n_linear_ranges = 2, 432 .n_voltages = 159, 433 .ops = &rpm_smps_ldo_ops, 434}; 435 436static const struct regulator_desc pm8994_ftsmps = { 437 .linear_ranges = (struct linear_range[]) { 438 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000), 439 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000), 440 }, 441 .n_linear_ranges = 2, 442 .n_voltages = 350, 443 .ops = &rpm_smps_ldo_ops, 444}; 445 446static const struct regulator_desc pm8994_nldo = { 447 .linear_ranges = (struct linear_range[]) { 448 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500), 449 }, 450 .n_linear_ranges = 1, 451 .n_voltages = 64, 452 .ops = &rpm_smps_ldo_ops, 453}; 454 455static const struct regulator_desc pm8994_pldo = { 456 .linear_ranges = (struct linear_range[]) { 457 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500), 458 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000), 459 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000), 460 }, 461 .n_linear_ranges = 3, 462 .n_voltages = 164, 463 .ops = &rpm_smps_ldo_ops, 464}; 465 466static const struct regulator_desc pm8994_switch = { 467 .ops = &rpm_switch_ops, 468}; 469 470static const struct regulator_desc pm8994_lnldo = { 471 .fixed_uV = 1740000, 472 .n_voltages = 1, 473 .ops = &rpm_smps_ldo_ops_fixed, 474}; 475 476static const struct regulator_desc pmi8994_ftsmps = { 477 .linear_ranges = (struct linear_range[]) { 478 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000), 479 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000), 480 }, 481 .n_linear_ranges = 2, 482 .n_voltages = 350, 483 .ops = &rpm_smps_ldo_ops, 484}; 485 486static const struct regulator_desc pmi8994_hfsmps = { 487 .linear_ranges = (struct linear_range[]) { 488 REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500), 489 REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000), 490 }, 491 .n_linear_ranges = 2, 492 .n_voltages = 142, 493 .ops = &rpm_smps_ldo_ops, 494}; 495 496static const struct regulator_desc pmi8994_bby = { 497 .linear_ranges = (struct linear_range[]) { 498 REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000), 499 }, 500 .n_linear_ranges = 1, 501 .n_voltages = 45, 502 .ops = &rpm_bob_ops, 503}; 504 505static const struct regulator_desc pm8998_ftsmps = { 506 .linear_ranges = (struct linear_range[]) { 507 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), 508 }, 509 .n_linear_ranges = 1, 510 .n_voltages = 259, 511 .ops = &rpm_smps_ldo_ops, 512}; 513 514static const struct regulator_desc pm8998_hfsmps = { 515 .linear_ranges = (struct linear_range[]) { 516 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), 517 }, 518 .n_linear_ranges = 1, 519 .n_voltages = 216, 520 .ops = &rpm_smps_ldo_ops, 521}; 522 523static const struct regulator_desc pm8998_nldo = { 524 .linear_ranges = (struct linear_range[]) { 525 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 526 }, 527 .n_linear_ranges = 1, 528 .n_voltages = 128, 529 .ops = &rpm_smps_ldo_ops, 530}; 531 532static const struct regulator_desc pm8998_pldo = { 533 .linear_ranges = (struct linear_range[]) { 534 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), 535 }, 536 .n_linear_ranges = 1, 537 .n_voltages = 256, 538 .ops = &rpm_smps_ldo_ops, 539}; 540 541static const struct regulator_desc pm8998_pldo_lv = { 542 .linear_ranges = (struct linear_range[]) { 543 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), 544 }, 545 .n_linear_ranges = 1, 546 .n_voltages = 128, 547 .ops = &rpm_smps_ldo_ops, 548}; 549 550static const struct regulator_desc pm8998_switch = { 551 .ops = &rpm_switch_ops, 552}; 553 554static const struct regulator_desc pmi8998_bob = { 555 .linear_ranges = (struct linear_range[]) { 556 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), 557 }, 558 .n_linear_ranges = 1, 559 .n_voltages = 84, 560 .ops = &rpm_bob_ops, 561}; 562 563static const struct regulator_desc pm660_ftsmps = { 564 .linear_ranges = (struct linear_range[]) { 565 REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000), 566 }, 567 .n_linear_ranges = 1, 568 .n_voltages = 200, 569 .ops = &rpm_smps_ldo_ops, 570}; 571 572static const struct regulator_desc pm660_hfsmps = { 573 .linear_ranges = (struct linear_range[]) { 574 REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000), 575 }, 576 .n_linear_ranges = 1, 577 .n_voltages = 217, 578 .ops = &rpm_smps_ldo_ops, 579}; 580 581static const struct regulator_desc pm660_ht_nldo = { 582 .linear_ranges = (struct linear_range[]) { 583 REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000), 584 }, 585 .n_linear_ranges = 1, 586 .n_voltages = 125, 587 .ops = &rpm_smps_ldo_ops, 588}; 589 590static const struct regulator_desc pm660_ht_lvpldo = { 591 .linear_ranges = (struct linear_range[]) { 592 REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000), 593 }, 594 .n_linear_ranges = 1, 595 .n_voltages = 63, 596 .ops = &rpm_smps_ldo_ops, 597}; 598 599static const struct regulator_desc pm660_nldo660 = { 600 .linear_ranges = (struct linear_range[]) { 601 REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000), 602 }, 603 .n_linear_ranges = 1, 604 .n_voltages = 124, 605 .ops = &rpm_smps_ldo_ops, 606}; 607 608static const struct regulator_desc pm660_pldo660 = { 609 .linear_ranges = (struct linear_range[]) { 610 REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), 611 }, 612 .n_linear_ranges = 1, 613 .n_voltages = 256, 614 .ops = &rpm_smps_ldo_ops, 615}; 616 617static const struct regulator_desc pm660l_bob = { 618 .linear_ranges = (struct linear_range[]) { 619 REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000), 620 }, 621 .n_linear_ranges = 1, 622 .n_voltages = 85, 623 .ops = &rpm_bob_ops, 624}; 625 626static const struct regulator_desc pms405_hfsmps3 = { 627 .linear_ranges = (struct linear_range[]) { 628 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), 629 }, 630 .n_linear_ranges = 1, 631 .n_voltages = 216, 632 .ops = &rpm_smps_ldo_ops, 633}; 634 635static const struct regulator_desc pms405_nldo300 = { 636 .linear_ranges = (struct linear_range[]) { 637 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 638 }, 639 .n_linear_ranges = 1, 640 .n_voltages = 128, 641 .ops = &rpm_smps_ldo_ops, 642}; 643 644static const struct regulator_desc pms405_nldo1200 = { 645 .linear_ranges = (struct linear_range[]) { 646 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), 647 }, 648 .n_linear_ranges = 1, 649 .n_voltages = 128, 650 .ops = &rpm_smps_ldo_ops, 651}; 652 653static const struct regulator_desc pms405_pldo50 = { 654 .linear_ranges = (struct linear_range[]) { 655 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000), 656 }, 657 .n_linear_ranges = 1, 658 .n_voltages = 129, 659 .ops = &rpm_smps_ldo_ops, 660}; 661 662static const struct regulator_desc pms405_pldo150 = { 663 .linear_ranges = (struct linear_range[]) { 664 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000), 665 }, 666 .n_linear_ranges = 1, 667 .n_voltages = 129, 668 .ops = &rpm_smps_ldo_ops, 669}; 670 671static const struct regulator_desc pms405_pldo600 = { 672 .linear_ranges = (struct linear_range[]) { 673 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000), 674 }, 675 .n_linear_ranges = 1, 676 .n_voltages = 99, 677 .ops = &rpm_smps_ldo_ops, 678}; 679 680static const struct regulator_desc mp5496_smpa2 = { 681 .linear_ranges = (struct linear_range[]) { 682 REGULATOR_LINEAR_RANGE(725000, 0, 27, 12500), 683 }, 684 .n_linear_ranges = 1, 685 .n_voltages = 28, 686 .ops = &rpm_mp5496_ops, 687}; 688 689static const struct regulator_desc mp5496_ldoa2 = { 690 .linear_ranges = (struct linear_range[]) { 691 REGULATOR_LINEAR_RANGE(1800000, 0, 60, 25000), 692 }, 693 .n_linear_ranges = 1, 694 .n_voltages = 61, 695 .ops = &rpm_mp5496_ops, 696}; 697 698struct rpm_regulator_data { 699 const char *name; 700 u32 type; 701 u32 id; 702 const struct regulator_desc *desc; 703 const char *supply; 704}; 705 706static const struct rpm_regulator_data rpm_mp5496_regulators[] = { 707 { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" }, 708 { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" }, 709 {} 710}; 711 712static const struct rpm_regulator_data rpm_pm8841_regulators[] = { 713 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" }, 714 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" }, 715 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" }, 716 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" }, 717 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" }, 718 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" }, 719 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" }, 720 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" }, 721 {} 722}; 723 724static const struct rpm_regulator_data rpm_pm8916_regulators[] = { 725 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" }, 726 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" }, 727 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" }, 728 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" }, 729 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" }, 730 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" }, 731 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" }, 732 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" }, 733 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" }, 734 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" }, 735 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" }, 736 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" }, 737 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" }, 738 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 739 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 740 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 741 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 742 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 743 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 744 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 745 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 746 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"}, 747 {} 748}; 749 750static const struct rpm_regulator_data rpm_pm8941_regulators[] = { 751 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" }, 752 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" }, 753 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" }, 754 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost }, 755 756 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" }, 757 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" }, 758 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" }, 759 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" }, 760 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" }, 761 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 762 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" }, 763 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 764 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 765 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 766 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" }, 767 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 768 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 769 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 770 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" }, 771 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 772 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 773 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 774 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" }, 775 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 776 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" }, 777 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" }, 778 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 779 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" }, 780 781 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 782 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 783 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" }, 784 785 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" }, 786 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" }, 787 788 {} 789}; 790 791static const struct rpm_regulator_data rpm_pma8084_regulators[] = { 792 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, 793 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, 794 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, 795 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, 796 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, 797 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, 798 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, 799 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" }, 800 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" }, 801 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" }, 802 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" }, 803 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" }, 804 805 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, 806 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 807 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 808 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 809 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, 810 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 811 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, 812 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, 813 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 814 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 815 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, 816 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 817 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 818 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 819 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 820 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, 821 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, 822 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, 823 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, 824 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 825 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, 826 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, 827 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 828 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, 829 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, 830 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, 831 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, 832 833 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, 834 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, 835 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch }, 836 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch }, 837 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch }, 838 839 {} 840}; 841 842static const struct rpm_regulator_data rpm_pm8950_regulators[] = { 843 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" }, 844 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" }, 845 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" }, 846 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" }, 847 /* S5 is managed via SPMI. */ 848 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" }, 849 850 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" }, 851 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" }, 852 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" }, 853 /* L4 seems not to exist. */ 854 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" }, 855 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" }, 856 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" }, 857 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" }, 858 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" }, 859 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"}, 860 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" }, 861 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" }, 862 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" }, 863 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" }, 864 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" }, 865 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" }, 866 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" }, 867 /* L18 seems not to exist. */ 868 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" }, 869 /* L20 & L21 seem not to exist. */ 870 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" }, 871 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" }, 872 {} 873}; 874 875static const struct rpm_regulator_data rpm_pm8953_regulators[] = { 876 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" }, 877 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" }, 878 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" }, 879 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, 880 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" }, 881 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" }, 882 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" }, 883 884 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" }, 885 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" }, 886 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" }, 887 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" }, 888 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" }, 889 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" }, 890 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" }, 891 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 892 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" }, 893 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" }, 894 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 895 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 896 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 897 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 898 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" }, 899 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" }, 900 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" }, 901 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" }, 902 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" }, 903 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" }, 904 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" }, 905 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" }, 906 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" }, 907 {} 908}; 909 910static const struct rpm_regulator_data rpm_pm8994_regulators[] = { 911 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" }, 912 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" }, 913 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" }, 914 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" }, 915 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" }, 916 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" }, 917 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" }, 918 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" }, 919 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" }, 920 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" }, 921 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" }, 922 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" }, 923 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" }, 924 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" }, 925 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" }, 926 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" }, 927 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" }, 928 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" }, 929 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" }, 930 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" }, 931 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 932 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 933 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" }, 934 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" }, 935 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 936 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" }, 937 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" }, 938 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" }, 939 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" }, 940 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 941 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 942 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" }, 943 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" }, 944 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" }, 945 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 946 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" }, 947 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" }, 948 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" }, 949 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" }, 950 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" }, 951 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" }, 952 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" }, 953 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" }, 954 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" }, 955 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" }, 956 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" }, 957 958 {} 959}; 960 961static const struct rpm_regulator_data rpm_pmi8994_regulators[] = { 962 { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" }, 963 { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" }, 964 { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" }, 965 { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" }, 966 {} 967}; 968 969static const struct rpm_regulator_data rpm_pm8998_regulators[] = { 970 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" }, 971 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" }, 972 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" }, 973 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, 974 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, 975 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" }, 976 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" }, 977 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" }, 978 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" }, 979 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" }, 980 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" }, 981 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" }, 982 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" }, 983 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" }, 984 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" }, 985 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" }, 986 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" }, 987 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" }, 988 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" }, 989 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 990 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" }, 991 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" }, 992 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" }, 993 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" }, 994 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 995 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" }, 996 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 997 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, 998 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" }, 999 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" }, 1000 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" }, 1001 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" }, 1002 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" }, 1003 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" }, 1004 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" }, 1005 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" }, 1006 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" }, 1007 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" }, 1008 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" }, 1009 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" }, 1010 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" }, 1011 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" }, 1012 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" }, 1013 {} 1014}; 1015 1016static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { 1017 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, 1018 {} 1019}; 1020 1021static const struct rpm_regulator_data rpm_pm660_regulators[] = { 1022 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" }, 1023 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" }, 1024 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" }, 1025 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" }, 1026 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" }, 1027 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" }, 1028 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" }, 1029 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" }, 1030 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" }, 1031 /* l4 is unaccessible on PM660 */ 1032 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" }, 1033 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 1034 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" }, 1035 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1036 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1037 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1038 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1039 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1040 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1041 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" }, 1042 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1043 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1044 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1045 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1046 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" }, 1047 { } 1048}; 1049 1050static const struct rpm_regulator_data rpm_pm660l_regulators[] = { 1051 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" }, 1052 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" }, 1053 { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" }, 1054 { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" }, 1055 { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" }, 1056 { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" }, 1057 { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1058 { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" }, 1059 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1060 { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" }, 1061 { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1062 { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" }, 1063 { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 1064 { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" }, 1065 { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", }, 1066 { } 1067}; 1068 1069static const struct rpm_regulator_data rpm_pms405_regulators[] = { 1070 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" }, 1071 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" }, 1072 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" }, 1073 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" }, 1074 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" }, 1075 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" }, 1076 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" }, 1077 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" }, 1078 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" }, 1079 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" }, 1080 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" }, 1081 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" }, 1082 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" }, 1083 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" }, 1084 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" }, 1085 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 1086 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 1087 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" }, 1088 {} 1089}; 1090 1091static const struct of_device_id rpm_of_match[] = { 1092 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators }, 1093 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, 1094 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, 1095 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, 1096 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators }, 1097 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators }, 1098 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, 1099 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators }, 1100 { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators }, 1101 { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators }, 1102 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, 1103 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators }, 1104 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators }, 1105 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators }, 1106 {} 1107}; 1108MODULE_DEVICE_TABLE(of, rpm_of_match); 1109 1110/** 1111 * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator 1112 * @vreg: Pointer to the individual qcom_smd-regulator resource 1113 * @dev: Pointer to the top level qcom_smd-regulator PMIC device 1114 * @node: Pointer to the individual qcom_smd-regulator resource 1115 * device node 1116 * @rpm: Pointer to the rpm bus node 1117 * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator 1118 * resources defined for the top level PMIC device 1119 * 1120 * Return: 0 on success, errno on failure 1121 */ 1122static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev, 1123 struct device_node *node, struct qcom_smd_rpm *rpm, 1124 const struct rpm_regulator_data *pmic_rpm_data) 1125{ 1126 struct regulator_config config = {}; 1127 const struct rpm_regulator_data *rpm_data; 1128 struct regulator_dev *rdev; 1129 int ret; 1130 1131 for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++) 1132 if (of_node_name_eq(node, rpm_data->name)) 1133 break; 1134 1135 if (!rpm_data->name) { 1136 dev_err(dev, "Unknown regulator %pOFn\n", node); 1137 return -EINVAL; 1138 } 1139 1140 vreg->dev = dev; 1141 vreg->rpm = rpm; 1142 vreg->type = rpm_data->type; 1143 vreg->id = rpm_data->id; 1144 1145 memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc)); 1146 vreg->desc.name = rpm_data->name; 1147 vreg->desc.supply_name = rpm_data->supply; 1148 vreg->desc.owner = THIS_MODULE; 1149 vreg->desc.type = REGULATOR_VOLTAGE; 1150 vreg->desc.of_match = rpm_data->name; 1151 1152 config.dev = dev; 1153 config.of_node = node; 1154 config.driver_data = vreg; 1155 1156 rdev = devm_regulator_register(dev, &vreg->desc, &config); 1157 if (IS_ERR(rdev)) { 1158 ret = PTR_ERR(rdev); 1159 dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret); 1160 return ret; 1161 } 1162 1163 return 0; 1164} 1165 1166static int rpm_reg_probe(struct platform_device *pdev) 1167{ 1168 struct device *dev = &pdev->dev; 1169 const struct rpm_regulator_data *vreg_data; 1170 struct device_node *node; 1171 struct qcom_rpm_reg *vreg; 1172 struct qcom_smd_rpm *rpm; 1173 int ret; 1174 1175 rpm = dev_get_drvdata(pdev->dev.parent); 1176 if (!rpm) { 1177 dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n"); 1178 return -ENODEV; 1179 } 1180 1181 vreg_data = of_device_get_match_data(dev); 1182 if (!vreg_data) 1183 return -ENODEV; 1184 1185 for_each_available_child_of_node(dev->of_node, node) { 1186 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL); 1187 if (!vreg) { 1188 of_node_put(node); 1189 return -ENOMEM; 1190 } 1191 1192 ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data); 1193 1194 if (ret < 0) { 1195 of_node_put(node); 1196 return ret; 1197 } 1198 } 1199 1200 return 0; 1201} 1202 1203static struct platform_driver rpm_reg_driver = { 1204 .probe = rpm_reg_probe, 1205 .driver = { 1206 .name = "qcom_rpm_smd_regulator", 1207 .of_match_table = rpm_of_match, 1208 }, 1209}; 1210 1211static int __init rpm_reg_init(void) 1212{ 1213 return platform_driver_register(&rpm_reg_driver); 1214} 1215subsys_initcall(rpm_reg_init); 1216 1217static void __exit rpm_reg_exit(void) 1218{ 1219 platform_driver_unregister(&rpm_reg_driver); 1220} 1221module_exit(rpm_reg_exit) 1222 1223MODULE_DESCRIPTION("Qualcomm RPM regulator driver"); 1224MODULE_LICENSE("GPL v2"); 1225