1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/pwm/pwm-tegra.c
4 *
5 * Tegra pulse-width-modulation controller driver
6 *
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
9 *
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
14 *
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
17 * frequency for PWM output. The maximum output frequency that can be
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
20 * 408 MHz/256 = 1.6 MHz.
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
22 *
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
24 * To achieve 100% duty cycle, program Bit [24] of this register to
25 * 1’b1. In which case the other bits [23:16] are set to don't care.
26 *
27 * Limitations:
28 * -	When PWM is disabled, the output is driven to inactive.
29 * -	It does not allow the current PWM period to complete and
30 *	stops abruptly.
31 *
32 * -	If the register is reconfigured while PWM is running,
33 *	it does not complete the currently running period.
34 *
35 * -	If the user input duty is beyond acceptible limits,
36 *	-EINVAL is returned.
37 */
38
39#include <linux/clk.h>
40#include <linux/err.h>
41#include <linux/io.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/of_device.h>
45#include <linux/pwm.h>
46#include <linux/platform_device.h>
47#include <linux/pinctrl/consumer.h>
48#include <linux/slab.h>
49#include <linux/reset.h>
50
51#define PWM_ENABLE	(1 << 31)
52#define PWM_DUTY_WIDTH	8
53#define PWM_DUTY_SHIFT	16
54#define PWM_SCALE_WIDTH	13
55#define PWM_SCALE_SHIFT	0
56
57struct tegra_pwm_soc {
58	unsigned int num_channels;
59
60	/* Maximum IP frequency for given SoCs */
61	unsigned long max_frequency;
62};
63
64struct tegra_pwm_chip {
65	struct pwm_chip chip;
66	struct device *dev;
67
68	struct clk *clk;
69	struct reset_control*rst;
70
71	unsigned long clk_rate;
72	unsigned long min_period_ns;
73
74	void __iomem *regs;
75
76	const struct tegra_pwm_soc *soc;
77};
78
79static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
80{
81	return container_of(chip, struct tegra_pwm_chip, chip);
82}
83
84static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
85{
86	return readl(chip->regs + (num << 4));
87}
88
89static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
90			     unsigned long val)
91{
92	writel(val, chip->regs + (num << 4));
93}
94
95static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96			    int duty_ns, int period_ns)
97{
98	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
99	unsigned long long c = duty_ns, hz;
100	unsigned long rate, required_clk_rate;
101	u32 val = 0;
102	int err;
103
104	/*
105	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
106	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
107	 * nearest integer during division.
108	 */
109	c *= (1 << PWM_DUTY_WIDTH);
110	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
111
112	val = (u32)c << PWM_DUTY_SHIFT;
113
114	/*
115	 *  min period = max clock limit >> PWM_DUTY_WIDTH
116	 */
117	if (period_ns < pc->min_period_ns)
118		return -EINVAL;
119
120	/*
121	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
122	 * cycles at the PWM clock rate will take period_ns nanoseconds.
123	 *
124	 * num_channels: If single instance of PWM controller has multiple
125	 * channels (e.g. Tegra210 or older) then it is not possible to
126	 * configure separate clock rates to each of the channels, in such
127	 * case the value stored during probe will be referred.
128	 *
129	 * If every PWM controller instance has one channel respectively, i.e.
130	 * nums_channels == 1 then only the clock rate can be modified
131	 * dynamically (e.g. Tegra186 or Tegra194).
132	 */
133	if (pc->soc->num_channels == 1) {
134		/*
135		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
136		 * with the maximum possible rate that the controller can
137		 * provide. Any further lower value can be derived by setting
138		 * PFM bits[0:12].
139		 *
140		 * required_clk_rate is a reference rate for source clock and
141		 * it is derived based on user requested period. By setting the
142		 * source clock rate as required_clk_rate, PWM controller will
143		 * be able to configure the requested period.
144		 */
145		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
146						     period_ns);
147
148		err = clk_set_rate(pc->clk, required_clk_rate);
149		if (err < 0)
150			return -EINVAL;
151
152		/* Store the new rate for further references */
153		pc->clk_rate = clk_get_rate(pc->clk);
154	}
155
156	rate = pc->clk_rate >> PWM_DUTY_WIDTH;
157
158	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
159	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
160	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
161
162	/*
163	 * Since the actual PWM divider is the register's frequency divider
164	 * field plus 1, we need to decrement to get the correct value to
165	 * write to the register.
166	 */
167	if (rate > 0)
168		rate--;
169
170	/*
171	 * Make sure that the rate will fit in the register's frequency
172	 * divider field.
173	 */
174	if (rate >> PWM_SCALE_WIDTH)
175		return -EINVAL;
176
177	val |= rate << PWM_SCALE_SHIFT;
178
179	/*
180	 * If the PWM channel is disabled, make sure to turn on the clock
181	 * before writing the register. Otherwise, keep it enabled.
182	 */
183	if (!pwm_is_enabled(pwm)) {
184		err = clk_prepare_enable(pc->clk);
185		if (err < 0)
186			return err;
187	} else
188		val |= PWM_ENABLE;
189
190	pwm_writel(pc, pwm->hwpwm, val);
191
192	/*
193	 * If the PWM is not enabled, turn the clock off again to save power.
194	 */
195	if (!pwm_is_enabled(pwm))
196		clk_disable_unprepare(pc->clk);
197
198	return 0;
199}
200
201static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
202{
203	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
204	int rc = 0;
205	u32 val;
206
207	rc = clk_prepare_enable(pc->clk);
208	if (rc < 0)
209		return rc;
210
211	val = pwm_readl(pc, pwm->hwpwm);
212	val |= PWM_ENABLE;
213	pwm_writel(pc, pwm->hwpwm, val);
214
215	return 0;
216}
217
218static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
219{
220	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
221	u32 val;
222
223	val = pwm_readl(pc, pwm->hwpwm);
224	val &= ~PWM_ENABLE;
225	pwm_writel(pc, pwm->hwpwm, val);
226
227	clk_disable_unprepare(pc->clk);
228}
229
230static const struct pwm_ops tegra_pwm_ops = {
231	.config = tegra_pwm_config,
232	.enable = tegra_pwm_enable,
233	.disable = tegra_pwm_disable,
234	.owner = THIS_MODULE,
235};
236
237static int tegra_pwm_probe(struct platform_device *pdev)
238{
239	struct tegra_pwm_chip *pwm;
240	struct resource *r;
241	int ret;
242
243	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
244	if (!pwm)
245		return -ENOMEM;
246
247	pwm->soc = of_device_get_match_data(&pdev->dev);
248	pwm->dev = &pdev->dev;
249
250	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
252	if (IS_ERR(pwm->regs))
253		return PTR_ERR(pwm->regs);
254
255	platform_set_drvdata(pdev, pwm);
256
257	pwm->clk = devm_clk_get(&pdev->dev, NULL);
258	if (IS_ERR(pwm->clk))
259		return PTR_ERR(pwm->clk);
260
261	/* Set maximum frequency of the IP */
262	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
263	if (ret < 0) {
264		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
265		return ret;
266	}
267
268	/*
269	 * The requested and configured frequency may differ due to
270	 * clock register resolutions. Get the configured frequency
271	 * so that PWM period can be calculated more accurately.
272	 */
273	pwm->clk_rate = clk_get_rate(pwm->clk);
274
275	/* Set minimum limit of PWM period for the IP */
276	pwm->min_period_ns =
277	    (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
278
279	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
280	if (IS_ERR(pwm->rst)) {
281		ret = PTR_ERR(pwm->rst);
282		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
283		return ret;
284	}
285
286	reset_control_deassert(pwm->rst);
287
288	pwm->chip.dev = &pdev->dev;
289	pwm->chip.ops = &tegra_pwm_ops;
290	pwm->chip.base = -1;
291	pwm->chip.npwm = pwm->soc->num_channels;
292
293	ret = pwmchip_add(&pwm->chip);
294	if (ret < 0) {
295		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
296		reset_control_assert(pwm->rst);
297		return ret;
298	}
299
300	return 0;
301}
302
303static int tegra_pwm_remove(struct platform_device *pdev)
304{
305	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
306	int err;
307
308	if (WARN_ON(!pc))
309		return -ENODEV;
310
311	err = clk_prepare_enable(pc->clk);
312	if (err < 0)
313		return err;
314
315	reset_control_assert(pc->rst);
316	clk_disable_unprepare(pc->clk);
317
318	return pwmchip_remove(&pc->chip);
319}
320
321#ifdef CONFIG_PM_SLEEP
322static int tegra_pwm_suspend(struct device *dev)
323{
324	return pinctrl_pm_select_sleep_state(dev);
325}
326
327static int tegra_pwm_resume(struct device *dev)
328{
329	return pinctrl_pm_select_default_state(dev);
330}
331#endif
332
333static const struct tegra_pwm_soc tegra20_pwm_soc = {
334	.num_channels = 4,
335	.max_frequency = 48000000UL,
336};
337
338static const struct tegra_pwm_soc tegra186_pwm_soc = {
339	.num_channels = 1,
340	.max_frequency = 102000000UL,
341};
342
343static const struct tegra_pwm_soc tegra194_pwm_soc = {
344	.num_channels = 1,
345	.max_frequency = 408000000UL,
346};
347
348static const struct of_device_id tegra_pwm_of_match[] = {
349	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
350	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
351	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
352	{ }
353};
354MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
355
356static const struct dev_pm_ops tegra_pwm_pm_ops = {
357	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
358};
359
360static struct platform_driver tegra_pwm_driver = {
361	.driver = {
362		.name = "tegra-pwm",
363		.of_match_table = tegra_pwm_of_match,
364		.pm = &tegra_pwm_pm_ops,
365	},
366	.probe = tegra_pwm_probe,
367	.remove = tegra_pwm_remove,
368};
369
370module_platform_driver(tegra_pwm_driver);
371
372MODULE_LICENSE("GPL");
373MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
374MODULE_DESCRIPTION("Tegra PWM controller driver");
375MODULE_ALIAS("platform:tegra-pwm");
376