1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Spreadtrum Communications Inc. 4 */ 5 6#include <linux/clk.h> 7#include <linux/err.h> 8#include <linux/io.h> 9#include <linux/math64.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <linux/pwm.h> 13 14#define SPRD_PWM_PRESCALE 0x0 15#define SPRD_PWM_MOD 0x4 16#define SPRD_PWM_DUTY 0x8 17#define SPRD_PWM_ENABLE 0x18 18 19#define SPRD_PWM_MOD_MAX GENMASK(7, 0) 20#define SPRD_PWM_DUTY_MSK GENMASK(15, 0) 21#define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) 22#define SPRD_PWM_ENABLE_BIT BIT(0) 23 24#define SPRD_PWM_CHN_NUM 4 25#define SPRD_PWM_REGS_SHIFT 5 26#define SPRD_PWM_CHN_CLKS_NUM 2 27#define SPRD_PWM_CHN_OUTPUT_CLK 1 28 29struct sprd_pwm_chn { 30 struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM]; 31 u32 clk_rate; 32}; 33 34struct sprd_pwm_chip { 35 void __iomem *base; 36 struct device *dev; 37 struct pwm_chip chip; 38 int num_pwms; 39 struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; 40}; 41 42/* 43 * The list of clocks required by PWM channels, and each channel has 2 clocks: 44 * enable clock and pwm clock. 45 */ 46static const char * const sprd_pwm_clks[] = { 47 "enable0", "pwm0", 48 "enable1", "pwm1", 49 "enable2", "pwm2", 50 "enable3", "pwm3", 51}; 52 53static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) 54{ 55 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 56 57 return readl_relaxed(spc->base + offset); 58} 59 60static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, 61 u32 reg, u32 val) 62{ 63 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); 64 65 writel_relaxed(val, spc->base + offset); 66} 67 68static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 69 struct pwm_state *state) 70{ 71 struct sprd_pwm_chip *spc = 72 container_of(chip, struct sprd_pwm_chip, chip); 73 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 74 u32 val, duty, prescale; 75 u64 tmp; 76 int ret; 77 78 /* 79 * The clocks to PWM channel has to be enabled first before 80 * reading to the registers. 81 */ 82 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 83 if (ret) { 84 dev_err(spc->dev, "failed to enable pwm%u clocks\n", 85 pwm->hwpwm); 86 return; 87 } 88 89 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); 90 if (val & SPRD_PWM_ENABLE_BIT) 91 state->enabled = true; 92 else 93 state->enabled = false; 94 95 /* 96 * The hardware provides a counter that is feed by the source clock. 97 * The period length is (PRESCALE + 1) * MOD counter steps. 98 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 99 * Thus the period_ns and duty_ns calculation formula should be: 100 * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate 101 * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate 102 */ 103 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); 104 prescale = val & SPRD_PWM_PRESCALE_MSK; 105 tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; 106 state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 107 108 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); 109 duty = val & SPRD_PWM_DUTY_MSK; 110 tmp = (prescale + 1) * NSEC_PER_SEC * duty; 111 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); 112 state->polarity = PWM_POLARITY_NORMAL; 113 114 /* Disable PWM clocks if the PWM channel is not in enable state. */ 115 if (!state->enabled) 116 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 117} 118 119static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm, 120 int duty_ns, int period_ns) 121{ 122 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 123 u32 prescale, duty; 124 u64 tmp; 125 126 /* 127 * The hardware provides a counter that is feed by the source clock. 128 * The period length is (PRESCALE + 1) * MOD counter steps. 129 * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. 130 * 131 * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX. 132 * The value for PRESCALE is selected such that the resulting period 133 * gets the maximal length not bigger than the requested one with the 134 * given settings (MOD = SPRD_PWM_MOD_MAX and input clock). 135 */ 136 duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; 137 138 tmp = (u64)chn->clk_rate * period_ns; 139 do_div(tmp, NSEC_PER_SEC); 140 prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; 141 if (prescale > SPRD_PWM_PRESCALE_MSK) 142 prescale = SPRD_PWM_PRESCALE_MSK; 143 144 /* 145 * Note: Writing DUTY triggers the hardware to actually apply the 146 * values written to MOD and DUTY to the output, so must keep writing 147 * DUTY last. 148 * 149 * The hardware can ensures that current running period is completed 150 * before changing a new configuration to avoid mixed settings. 151 */ 152 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); 153 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); 154 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); 155 156 return 0; 157} 158 159static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 160 const struct pwm_state *state) 161{ 162 struct sprd_pwm_chip *spc = 163 container_of(chip, struct sprd_pwm_chip, chip); 164 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; 165 struct pwm_state *cstate = &pwm->state; 166 int ret; 167 168 if (state->enabled) { 169 if (!cstate->enabled) { 170 /* 171 * The clocks to PWM channel has to be enabled first 172 * before writing to the registers. 173 */ 174 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, 175 chn->clks); 176 if (ret) { 177 dev_err(spc->dev, 178 "failed to enable pwm%u clocks\n", 179 pwm->hwpwm); 180 return ret; 181 } 182 } 183 184 ret = sprd_pwm_config(spc, pwm, state->duty_cycle, 185 state->period); 186 if (ret) 187 return ret; 188 189 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); 190 } else if (cstate->enabled) { 191 /* 192 * Note: After setting SPRD_PWM_ENABLE to zero, the controller 193 * will not wait for current period to be completed, instead it 194 * will stop the PWM channel immediately. 195 */ 196 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); 197 198 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks); 199 } 200 201 return 0; 202} 203 204static const struct pwm_ops sprd_pwm_ops = { 205 .apply = sprd_pwm_apply, 206 .get_state = sprd_pwm_get_state, 207 .owner = THIS_MODULE, 208}; 209 210static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) 211{ 212 struct clk *clk_pwm; 213 int ret, i; 214 215 for (i = 0; i < SPRD_PWM_CHN_NUM; i++) { 216 struct sprd_pwm_chn *chn = &spc->chn[i]; 217 int j; 218 219 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j) 220 chn->clks[j].id = 221 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j]; 222 223 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM, 224 chn->clks); 225 if (ret) { 226 if (ret == -ENOENT) 227 break; 228 229 return dev_err_probe(spc->dev, ret, 230 "failed to get channel clocks\n"); 231 } 232 233 clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk; 234 chn->clk_rate = clk_get_rate(clk_pwm); 235 } 236 237 if (!i) { 238 dev_err(spc->dev, "no available PWM channels\n"); 239 return -ENODEV; 240 } 241 242 spc->num_pwms = i; 243 244 return 0; 245} 246 247static int sprd_pwm_probe(struct platform_device *pdev) 248{ 249 struct sprd_pwm_chip *spc; 250 int ret; 251 252 spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); 253 if (!spc) 254 return -ENOMEM; 255 256 spc->base = devm_platform_ioremap_resource(pdev, 0); 257 if (IS_ERR(spc->base)) 258 return PTR_ERR(spc->base); 259 260 spc->dev = &pdev->dev; 261 platform_set_drvdata(pdev, spc); 262 263 ret = sprd_pwm_clk_init(spc); 264 if (ret) 265 return ret; 266 267 spc->chip.dev = &pdev->dev; 268 spc->chip.ops = &sprd_pwm_ops; 269 spc->chip.base = -1; 270 spc->chip.npwm = spc->num_pwms; 271 272 ret = pwmchip_add(&spc->chip); 273 if (ret) 274 dev_err(&pdev->dev, "failed to add PWM chip\n"); 275 276 return ret; 277} 278 279static int sprd_pwm_remove(struct platform_device *pdev) 280{ 281 struct sprd_pwm_chip *spc = platform_get_drvdata(pdev); 282 283 return pwmchip_remove(&spc->chip); 284} 285 286static const struct of_device_id sprd_pwm_of_match[] = { 287 { .compatible = "sprd,ums512-pwm", }, 288 { }, 289}; 290MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); 291 292static struct platform_driver sprd_pwm_driver = { 293 .driver = { 294 .name = "sprd-pwm", 295 .of_match_table = sprd_pwm_of_match, 296 }, 297 .probe = sprd_pwm_probe, 298 .remove = sprd_pwm_remove, 299}; 300 301module_platform_driver(sprd_pwm_driver); 302 303MODULE_DESCRIPTION("Spreadtrum PWM Driver"); 304MODULE_LICENSE("GPL v2"); 305