18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * ST Microelectronics SPEAr Pulse Width Modulator driver 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * Copyright (C) 2012 ST Microelectronics 58c2ecf20Sopenharmony_ci * Shiraz Hashim <shiraz.linux.kernel@gmail.com> 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public 88c2ecf20Sopenharmony_ci * License version 2. This program is licensed "as is" without any 98c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied. 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/clk.h> 138c2ecf20Sopenharmony_ci#include <linux/err.h> 148c2ecf20Sopenharmony_ci#include <linux/io.h> 158c2ecf20Sopenharmony_ci#include <linux/ioport.h> 168c2ecf20Sopenharmony_ci#include <linux/kernel.h> 178c2ecf20Sopenharmony_ci#include <linux/math64.h> 188c2ecf20Sopenharmony_ci#include <linux/module.h> 198c2ecf20Sopenharmony_ci#include <linux/of.h> 208c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 218c2ecf20Sopenharmony_ci#include <linux/pwm.h> 228c2ecf20Sopenharmony_ci#include <linux/slab.h> 238c2ecf20Sopenharmony_ci#include <linux/types.h> 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#define NUM_PWM 4 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/* PWM registers and bits definitions */ 288c2ecf20Sopenharmony_ci#define PWMCR 0x00 /* Control Register */ 298c2ecf20Sopenharmony_ci#define PWMCR_PWM_ENABLE 0x1 308c2ecf20Sopenharmony_ci#define PWMCR_PRESCALE_SHIFT 2 318c2ecf20Sopenharmony_ci#define PWMCR_MIN_PRESCALE 0x00 328c2ecf20Sopenharmony_ci#define PWMCR_MAX_PRESCALE 0x3FFF 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#define PWMDCR 0x04 /* Duty Cycle Register */ 358c2ecf20Sopenharmony_ci#define PWMDCR_MIN_DUTY 0x0001 368c2ecf20Sopenharmony_ci#define PWMDCR_MAX_DUTY 0xFFFF 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci#define PWMPCR 0x08 /* Period Register */ 398c2ecf20Sopenharmony_ci#define PWMPCR_MIN_PERIOD 0x0001 408c2ecf20Sopenharmony_ci#define PWMPCR_MAX_PERIOD 0xFFFF 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci/* Following only available on 13xx SoCs */ 438c2ecf20Sopenharmony_ci#define PWMMCR 0x3C /* Master Control Register */ 448c2ecf20Sopenharmony_ci#define PWMMCR_PWM_ENABLE 0x1 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci/** 478c2ecf20Sopenharmony_ci * struct spear_pwm_chip - struct representing pwm chip 488c2ecf20Sopenharmony_ci * 498c2ecf20Sopenharmony_ci * @mmio_base: base address of pwm chip 508c2ecf20Sopenharmony_ci * @clk: pointer to clk structure of pwm chip 518c2ecf20Sopenharmony_ci * @chip: linux pwm chip representation 528c2ecf20Sopenharmony_ci */ 538c2ecf20Sopenharmony_cistruct spear_pwm_chip { 548c2ecf20Sopenharmony_ci void __iomem *mmio_base; 558c2ecf20Sopenharmony_ci struct clk *clk; 568c2ecf20Sopenharmony_ci struct pwm_chip chip; 578c2ecf20Sopenharmony_ci}; 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_cistatic inline struct spear_pwm_chip *to_spear_pwm_chip(struct pwm_chip *chip) 608c2ecf20Sopenharmony_ci{ 618c2ecf20Sopenharmony_ci return container_of(chip, struct spear_pwm_chip, chip); 628c2ecf20Sopenharmony_ci} 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_cistatic inline u32 spear_pwm_readl(struct spear_pwm_chip *chip, unsigned int num, 658c2ecf20Sopenharmony_ci unsigned long offset) 668c2ecf20Sopenharmony_ci{ 678c2ecf20Sopenharmony_ci return readl_relaxed(chip->mmio_base + (num << 4) + offset); 688c2ecf20Sopenharmony_ci} 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_cistatic inline void spear_pwm_writel(struct spear_pwm_chip *chip, 718c2ecf20Sopenharmony_ci unsigned int num, unsigned long offset, 728c2ecf20Sopenharmony_ci unsigned long val) 738c2ecf20Sopenharmony_ci{ 748c2ecf20Sopenharmony_ci writel_relaxed(val, chip->mmio_base + (num << 4) + offset); 758c2ecf20Sopenharmony_ci} 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_cistatic int spear_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 788c2ecf20Sopenharmony_ci int duty_ns, int period_ns) 798c2ecf20Sopenharmony_ci{ 808c2ecf20Sopenharmony_ci struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); 818c2ecf20Sopenharmony_ci u64 val, div, clk_rate; 828c2ecf20Sopenharmony_ci unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc; 838c2ecf20Sopenharmony_ci int ret; 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ci /* 868c2ecf20Sopenharmony_ci * Find pv, dc and prescale to suit duty_ns and period_ns. This is done 878c2ecf20Sopenharmony_ci * according to formulas described below: 888c2ecf20Sopenharmony_ci * 898c2ecf20Sopenharmony_ci * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE 908c2ecf20Sopenharmony_ci * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE 918c2ecf20Sopenharmony_ci * 928c2ecf20Sopenharmony_ci * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) 938c2ecf20Sopenharmony_ci * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) 948c2ecf20Sopenharmony_ci */ 958c2ecf20Sopenharmony_ci clk_rate = clk_get_rate(pc->clk); 968c2ecf20Sopenharmony_ci while (1) { 978c2ecf20Sopenharmony_ci div = 1000000000; 988c2ecf20Sopenharmony_ci div *= 1 + prescale; 998c2ecf20Sopenharmony_ci val = clk_rate * period_ns; 1008c2ecf20Sopenharmony_ci pv = div64_u64(val, div); 1018c2ecf20Sopenharmony_ci val = clk_rate * duty_ns; 1028c2ecf20Sopenharmony_ci dc = div64_u64(val, div); 1038c2ecf20Sopenharmony_ci 1048c2ecf20Sopenharmony_ci /* if duty_ns and period_ns are not achievable then return */ 1058c2ecf20Sopenharmony_ci if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY) 1068c2ecf20Sopenharmony_ci return -EINVAL; 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci /* 1098c2ecf20Sopenharmony_ci * if pv and dc have crossed their upper limit, then increase 1108c2ecf20Sopenharmony_ci * prescale and recalculate pv and dc. 1118c2ecf20Sopenharmony_ci */ 1128c2ecf20Sopenharmony_ci if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) { 1138c2ecf20Sopenharmony_ci if (++prescale > PWMCR_MAX_PRESCALE) 1148c2ecf20Sopenharmony_ci return -EINVAL; 1158c2ecf20Sopenharmony_ci continue; 1168c2ecf20Sopenharmony_ci } 1178c2ecf20Sopenharmony_ci break; 1188c2ecf20Sopenharmony_ci } 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci /* 1218c2ecf20Sopenharmony_ci * NOTE: the clock to PWM has to be enabled first before writing to the 1228c2ecf20Sopenharmony_ci * registers. 1238c2ecf20Sopenharmony_ci */ 1248c2ecf20Sopenharmony_ci ret = clk_enable(pc->clk); 1258c2ecf20Sopenharmony_ci if (ret) 1268c2ecf20Sopenharmony_ci return ret; 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci spear_pwm_writel(pc, pwm->hwpwm, PWMCR, 1298c2ecf20Sopenharmony_ci prescale << PWMCR_PRESCALE_SHIFT); 1308c2ecf20Sopenharmony_ci spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); 1318c2ecf20Sopenharmony_ci spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); 1328c2ecf20Sopenharmony_ci clk_disable(pc->clk); 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci return 0; 1358c2ecf20Sopenharmony_ci} 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_cistatic int spear_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 1388c2ecf20Sopenharmony_ci{ 1398c2ecf20Sopenharmony_ci struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); 1408c2ecf20Sopenharmony_ci int rc = 0; 1418c2ecf20Sopenharmony_ci u32 val; 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_ci rc = clk_enable(pc->clk); 1448c2ecf20Sopenharmony_ci if (rc) 1458c2ecf20Sopenharmony_ci return rc; 1468c2ecf20Sopenharmony_ci 1478c2ecf20Sopenharmony_ci val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 1488c2ecf20Sopenharmony_ci val |= PWMCR_PWM_ENABLE; 1498c2ecf20Sopenharmony_ci spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); 1508c2ecf20Sopenharmony_ci 1518c2ecf20Sopenharmony_ci return 0; 1528c2ecf20Sopenharmony_ci} 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_cistatic void spear_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 1558c2ecf20Sopenharmony_ci{ 1568c2ecf20Sopenharmony_ci struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); 1578c2ecf20Sopenharmony_ci u32 val; 1588c2ecf20Sopenharmony_ci 1598c2ecf20Sopenharmony_ci val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); 1608c2ecf20Sopenharmony_ci val &= ~PWMCR_PWM_ENABLE; 1618c2ecf20Sopenharmony_ci spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); 1628c2ecf20Sopenharmony_ci 1638c2ecf20Sopenharmony_ci clk_disable(pc->clk); 1648c2ecf20Sopenharmony_ci} 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_cistatic const struct pwm_ops spear_pwm_ops = { 1678c2ecf20Sopenharmony_ci .config = spear_pwm_config, 1688c2ecf20Sopenharmony_ci .enable = spear_pwm_enable, 1698c2ecf20Sopenharmony_ci .disable = spear_pwm_disable, 1708c2ecf20Sopenharmony_ci .owner = THIS_MODULE, 1718c2ecf20Sopenharmony_ci}; 1728c2ecf20Sopenharmony_ci 1738c2ecf20Sopenharmony_cistatic int spear_pwm_probe(struct platform_device *pdev) 1748c2ecf20Sopenharmony_ci{ 1758c2ecf20Sopenharmony_ci struct device_node *np = pdev->dev.of_node; 1768c2ecf20Sopenharmony_ci struct spear_pwm_chip *pc; 1778c2ecf20Sopenharmony_ci struct resource *r; 1788c2ecf20Sopenharmony_ci int ret; 1798c2ecf20Sopenharmony_ci u32 val; 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_ci pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 1828c2ecf20Sopenharmony_ci if (!pc) 1838c2ecf20Sopenharmony_ci return -ENOMEM; 1848c2ecf20Sopenharmony_ci 1858c2ecf20Sopenharmony_ci r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1868c2ecf20Sopenharmony_ci pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); 1878c2ecf20Sopenharmony_ci if (IS_ERR(pc->mmio_base)) 1888c2ecf20Sopenharmony_ci return PTR_ERR(pc->mmio_base); 1898c2ecf20Sopenharmony_ci 1908c2ecf20Sopenharmony_ci pc->clk = devm_clk_get(&pdev->dev, NULL); 1918c2ecf20Sopenharmony_ci if (IS_ERR(pc->clk)) 1928c2ecf20Sopenharmony_ci return PTR_ERR(pc->clk); 1938c2ecf20Sopenharmony_ci 1948c2ecf20Sopenharmony_ci platform_set_drvdata(pdev, pc); 1958c2ecf20Sopenharmony_ci 1968c2ecf20Sopenharmony_ci pc->chip.dev = &pdev->dev; 1978c2ecf20Sopenharmony_ci pc->chip.ops = &spear_pwm_ops; 1988c2ecf20Sopenharmony_ci pc->chip.base = -1; 1998c2ecf20Sopenharmony_ci pc->chip.npwm = NUM_PWM; 2008c2ecf20Sopenharmony_ci 2018c2ecf20Sopenharmony_ci ret = clk_prepare(pc->clk); 2028c2ecf20Sopenharmony_ci if (ret) 2038c2ecf20Sopenharmony_ci return ret; 2048c2ecf20Sopenharmony_ci 2058c2ecf20Sopenharmony_ci if (of_device_is_compatible(np, "st,spear1340-pwm")) { 2068c2ecf20Sopenharmony_ci ret = clk_enable(pc->clk); 2078c2ecf20Sopenharmony_ci if (ret) { 2088c2ecf20Sopenharmony_ci clk_unprepare(pc->clk); 2098c2ecf20Sopenharmony_ci return ret; 2108c2ecf20Sopenharmony_ci } 2118c2ecf20Sopenharmony_ci /* 2128c2ecf20Sopenharmony_ci * Following enables PWM chip, channels would still be 2138c2ecf20Sopenharmony_ci * enabled individually through their control register 2148c2ecf20Sopenharmony_ci */ 2158c2ecf20Sopenharmony_ci val = readl_relaxed(pc->mmio_base + PWMMCR); 2168c2ecf20Sopenharmony_ci val |= PWMMCR_PWM_ENABLE; 2178c2ecf20Sopenharmony_ci writel_relaxed(val, pc->mmio_base + PWMMCR); 2188c2ecf20Sopenharmony_ci 2198c2ecf20Sopenharmony_ci clk_disable(pc->clk); 2208c2ecf20Sopenharmony_ci } 2218c2ecf20Sopenharmony_ci 2228c2ecf20Sopenharmony_ci ret = pwmchip_add(&pc->chip); 2238c2ecf20Sopenharmony_ci if (ret < 0) { 2248c2ecf20Sopenharmony_ci clk_unprepare(pc->clk); 2258c2ecf20Sopenharmony_ci dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 2268c2ecf20Sopenharmony_ci } 2278c2ecf20Sopenharmony_ci 2288c2ecf20Sopenharmony_ci return ret; 2298c2ecf20Sopenharmony_ci} 2308c2ecf20Sopenharmony_ci 2318c2ecf20Sopenharmony_cistatic int spear_pwm_remove(struct platform_device *pdev) 2328c2ecf20Sopenharmony_ci{ 2338c2ecf20Sopenharmony_ci struct spear_pwm_chip *pc = platform_get_drvdata(pdev); 2348c2ecf20Sopenharmony_ci 2358c2ecf20Sopenharmony_ci /* clk was prepared in probe, hence unprepare it here */ 2368c2ecf20Sopenharmony_ci clk_unprepare(pc->clk); 2378c2ecf20Sopenharmony_ci return pwmchip_remove(&pc->chip); 2388c2ecf20Sopenharmony_ci} 2398c2ecf20Sopenharmony_ci 2408c2ecf20Sopenharmony_cistatic const struct of_device_id spear_pwm_of_match[] = { 2418c2ecf20Sopenharmony_ci { .compatible = "st,spear320-pwm" }, 2428c2ecf20Sopenharmony_ci { .compatible = "st,spear1340-pwm" }, 2438c2ecf20Sopenharmony_ci { } 2448c2ecf20Sopenharmony_ci}; 2458c2ecf20Sopenharmony_ci 2468c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, spear_pwm_of_match); 2478c2ecf20Sopenharmony_ci 2488c2ecf20Sopenharmony_cistatic struct platform_driver spear_pwm_driver = { 2498c2ecf20Sopenharmony_ci .driver = { 2508c2ecf20Sopenharmony_ci .name = "spear-pwm", 2518c2ecf20Sopenharmony_ci .of_match_table = spear_pwm_of_match, 2528c2ecf20Sopenharmony_ci }, 2538c2ecf20Sopenharmony_ci .probe = spear_pwm_probe, 2548c2ecf20Sopenharmony_ci .remove = spear_pwm_remove, 2558c2ecf20Sopenharmony_ci}; 2568c2ecf20Sopenharmony_ci 2578c2ecf20Sopenharmony_cimodule_platform_driver(spear_pwm_driver); 2588c2ecf20Sopenharmony_ci 2598c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 2608c2ecf20Sopenharmony_ciMODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>"); 2618c2ecf20Sopenharmony_ciMODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.com>"); 2628c2ecf20Sopenharmony_ciMODULE_ALIAS("platform:spear-pwm"); 263