1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PWM driver for Rockchip SoCs
4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 * Copyright (C) 2014 ROCKCHIP, Inc.
7 */
8
9#include <linux/clk.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/time.h>
17
18#define PWM_CTRL_TIMER_EN	(1 << 0)
19#define PWM_CTRL_OUTPUT_EN	(1 << 3)
20
21#define PWM_ENABLE		(1 << 0)
22#define PWM_CONTINUOUS		(1 << 1)
23#define PWM_DUTY_POSITIVE	(1 << 3)
24#define PWM_DUTY_NEGATIVE	(0 << 3)
25#define PWM_INACTIVE_NEGATIVE	(0 << 4)
26#define PWM_INACTIVE_POSITIVE	(1 << 4)
27#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
28#define PWM_OUTPUT_LEFT		(0 << 5)
29#define PWM_LOCK_EN		(1 << 6)
30#define PWM_LP_DISABLE		(0 << 8)
31
32struct rockchip_pwm_chip {
33	struct pwm_chip chip;
34	struct clk *clk;
35	struct clk *pclk;
36	const struct rockchip_pwm_data *data;
37	void __iomem *base;
38};
39
40struct rockchip_pwm_regs {
41	unsigned long duty;
42	unsigned long period;
43	unsigned long cntr;
44	unsigned long ctrl;
45};
46
47struct rockchip_pwm_data {
48	struct rockchip_pwm_regs regs;
49	unsigned int prescaler;
50	bool supports_polarity;
51	bool supports_lock;
52	u32 enable_conf;
53};
54
55static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
56{
57	return container_of(c, struct rockchip_pwm_chip, chip);
58}
59
60static void rockchip_pwm_get_state(struct pwm_chip *chip,
61				   struct pwm_device *pwm,
62				   struct pwm_state *state)
63{
64	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
65	u32 enable_conf = pc->data->enable_conf;
66	unsigned long clk_rate;
67	u64 tmp;
68	u32 val;
69	int ret;
70
71	ret = clk_enable(pc->pclk);
72	if (ret)
73		return;
74
75	clk_rate = clk_get_rate(pc->clk);
76
77	tmp = readl_relaxed(pc->base + pc->data->regs.period);
78	tmp *= pc->data->prescaler * NSEC_PER_SEC;
79	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
80
81	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
82	tmp *= pc->data->prescaler * NSEC_PER_SEC;
83	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84
85	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
86	state->enabled = (val & enable_conf) == enable_conf;
87
88	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
89		state->polarity = PWM_POLARITY_INVERSED;
90	else
91		state->polarity = PWM_POLARITY_NORMAL;
92
93	clk_disable(pc->pclk);
94}
95
96static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
97			       const struct pwm_state *state)
98{
99	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
100	unsigned long period, duty;
101	u64 clk_rate, div;
102	u32 ctrl;
103
104	clk_rate = clk_get_rate(pc->clk);
105
106	/*
107	 * Since period and duty cycle registers have a width of 32
108	 * bits, every possible input period can be obtained using the
109	 * default prescaler value for all practical clock rate values.
110	 */
111	div = clk_rate * state->period;
112	period = DIV_ROUND_CLOSEST_ULL(div,
113				       pc->data->prescaler * NSEC_PER_SEC);
114
115	div = clk_rate * state->duty_cycle;
116	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
117
118	/*
119	 * Lock the period and duty of previous configuration, then
120	 * change the duty and period, that would not be effective.
121	 */
122	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
123	if (pc->data->supports_lock) {
124		ctrl |= PWM_LOCK_EN;
125		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
126	}
127
128	writel(period, pc->base + pc->data->regs.period);
129	writel(duty, pc->base + pc->data->regs.duty);
130
131	if (pc->data->supports_polarity) {
132		ctrl &= ~PWM_POLARITY_MASK;
133		if (state->polarity == PWM_POLARITY_INVERSED)
134			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
135		else
136			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
137	}
138
139	/*
140	 * Unlock and set polarity at the same time,
141	 * the configuration of duty, period and polarity
142	 * would be effective together at next period.
143	 */
144	if (pc->data->supports_lock)
145		ctrl &= ~PWM_LOCK_EN;
146
147	writel(ctrl, pc->base + pc->data->regs.ctrl);
148}
149
150static int rockchip_pwm_enable(struct pwm_chip *chip,
151			       struct pwm_device *pwm,
152			       bool enable)
153{
154	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
155	u32 enable_conf = pc->data->enable_conf;
156	int ret;
157	u32 val;
158
159	if (enable) {
160		ret = clk_enable(pc->clk);
161		if (ret)
162			return ret;
163	}
164
165	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
166
167	if (enable)
168		val |= enable_conf;
169	else
170		val &= ~enable_conf;
171
172	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
173
174	if (!enable)
175		clk_disable(pc->clk);
176
177	return 0;
178}
179
180static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
181			      const struct pwm_state *state)
182{
183	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
184	struct pwm_state curstate;
185	bool enabled;
186	int ret = 0;
187
188	ret = clk_enable(pc->pclk);
189	if (ret)
190		return ret;
191
192	pwm_get_state(pwm, &curstate);
193	enabled = curstate.enabled;
194
195	if (state->polarity != curstate.polarity && enabled &&
196	    !pc->data->supports_lock) {
197		ret = rockchip_pwm_enable(chip, pwm, false);
198		if (ret)
199			goto out;
200		enabled = false;
201	}
202
203	rockchip_pwm_config(chip, pwm, state);
204	if (state->enabled != enabled) {
205		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
206		if (ret)
207			goto out;
208	}
209
210out:
211	clk_disable(pc->pclk);
212
213	return ret;
214}
215
216static const struct pwm_ops rockchip_pwm_ops = {
217	.get_state = rockchip_pwm_get_state,
218	.apply = rockchip_pwm_apply,
219	.owner = THIS_MODULE,
220};
221
222static const struct rockchip_pwm_data pwm_data_v1 = {
223	.regs = {
224		.duty = 0x04,
225		.period = 0x08,
226		.cntr = 0x00,
227		.ctrl = 0x0c,
228	},
229	.prescaler = 2,
230	.supports_polarity = false,
231	.supports_lock = false,
232	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
233};
234
235static const struct rockchip_pwm_data pwm_data_v2 = {
236	.regs = {
237		.duty = 0x08,
238		.period = 0x04,
239		.cntr = 0x00,
240		.ctrl = 0x0c,
241	},
242	.prescaler = 1,
243	.supports_polarity = true,
244	.supports_lock = false,
245	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
246		       PWM_CONTINUOUS,
247};
248
249static const struct rockchip_pwm_data pwm_data_vop = {
250	.regs = {
251		.duty = 0x08,
252		.period = 0x04,
253		.cntr = 0x0c,
254		.ctrl = 0x00,
255	},
256	.prescaler = 1,
257	.supports_polarity = true,
258	.supports_lock = false,
259	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
260		       PWM_CONTINUOUS,
261};
262
263static const struct rockchip_pwm_data pwm_data_v3 = {
264	.regs = {
265		.duty = 0x08,
266		.period = 0x04,
267		.cntr = 0x00,
268		.ctrl = 0x0c,
269	},
270	.prescaler = 1,
271	.supports_polarity = true,
272	.supports_lock = true,
273	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
274		       PWM_CONTINUOUS,
275};
276
277static const struct of_device_id rockchip_pwm_dt_ids[] = {
278	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
279	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
280	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
281	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
282	{ /* sentinel */ }
283};
284MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
285
286static int rockchip_pwm_probe(struct platform_device *pdev)
287{
288	const struct of_device_id *id;
289	struct rockchip_pwm_chip *pc;
290	struct resource *r;
291	u32 enable_conf, ctrl;
292	bool enabled;
293	int ret, count;
294
295	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
296	if (!id)
297		return -EINVAL;
298
299	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
300	if (!pc)
301		return -ENOMEM;
302
303	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
304	pc->base = devm_ioremap_resource(&pdev->dev, r);
305	if (IS_ERR(pc->base))
306		return PTR_ERR(pc->base);
307
308	pc->clk = devm_clk_get(&pdev->dev, "pwm");
309	if (IS_ERR(pc->clk)) {
310		pc->clk = devm_clk_get(&pdev->dev, NULL);
311		if (IS_ERR(pc->clk))
312			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
313					     "Can't get bus clk\n");
314	}
315
316	count = of_count_phandle_with_args(pdev->dev.of_node,
317					   "clocks", "#clock-cells");
318	if (count == 2)
319		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
320	else
321		pc->pclk = pc->clk;
322
323	if (IS_ERR(pc->pclk)) {
324		ret = PTR_ERR(pc->pclk);
325		if (ret != -EPROBE_DEFER)
326			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
327		return ret;
328	}
329
330	ret = clk_prepare_enable(pc->clk);
331	if (ret) {
332		dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
333		return ret;
334	}
335
336	ret = clk_prepare_enable(pc->pclk);
337	if (ret) {
338		dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
339		goto err_clk;
340	}
341
342	platform_set_drvdata(pdev, pc);
343
344	pc->data = id->data;
345	pc->chip.dev = &pdev->dev;
346	pc->chip.ops = &rockchip_pwm_ops;
347	pc->chip.base = -1;
348	pc->chip.npwm = 1;
349
350	if (pc->data->supports_polarity) {
351		pc->chip.of_xlate = of_pwm_xlate_with_flags;
352		pc->chip.of_pwm_n_cells = 3;
353	}
354
355	enable_conf = pc->data->enable_conf;
356	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
357	enabled = (ctrl & enable_conf) == enable_conf;
358
359	ret = pwmchip_add(&pc->chip);
360	if (ret < 0) {
361		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
362		goto err_pclk;
363	}
364
365	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
366	if (!enabled)
367		clk_disable(pc->clk);
368
369	clk_disable(pc->pclk);
370
371	return 0;
372
373err_pclk:
374	clk_disable_unprepare(pc->pclk);
375err_clk:
376	clk_disable_unprepare(pc->clk);
377
378	return ret;
379}
380
381static int rockchip_pwm_remove(struct platform_device *pdev)
382{
383	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
384
385	clk_unprepare(pc->pclk);
386	clk_unprepare(pc->clk);
387
388	return pwmchip_remove(&pc->chip);
389}
390
391static struct platform_driver rockchip_pwm_driver = {
392	.driver = {
393		.name = "rockchip-pwm",
394		.of_match_table = rockchip_pwm_dt_ids,
395	},
396	.probe = rockchip_pwm_probe,
397	.remove = rockchip_pwm_remove,
398};
399module_platform_driver(rockchip_pwm_driver);
400
401MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
402MODULE_DESCRIPTION("Rockchip SoC PWM driver");
403MODULE_LICENSE("GPL v2");
404