xref: /kernel/linux/linux-5.10/drivers/pwm/pwm-lpss.c (revision 8c2ecf20) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Low Power Subsystem PWM controller driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
8 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
9 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
10 * Author: Alan Cox <alan@linux.intel.com>
11 */
12
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pm_runtime.h>
19#include <linux/time.h>
20
21#include "pwm-lpss.h"
22
23#define PWM				0x00000000
24#define PWM_ENABLE			BIT(31)
25#define PWM_SW_UPDATE			BIT(30)
26#define PWM_BASE_UNIT_SHIFT		8
27#define PWM_ON_TIME_DIV_MASK		0x000000ff
28
29/* Size of each PWM register space if multiple */
30#define PWM_SIZE			0x400
31
32static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
33{
34	return container_of(chip, struct pwm_lpss_chip, chip);
35}
36
37static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
38{
39	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
40
41	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
42}
43
44static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
45{
46	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
47
48	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
49}
50
51static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
52{
53	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
54	const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
55	const unsigned int ms = 500 * USEC_PER_MSEC;
56	u32 val;
57	int err;
58
59	/*
60	 * PWM Configuration register has SW_UPDATE bit that is set when a new
61	 * configuration is written to the register. The bit is automatically
62	 * cleared at the start of the next output cycle by the IP block.
63	 *
64	 * If one writes a new configuration to the register while it still has
65	 * the bit enabled, PWM may freeze. That is, while one can still write
66	 * to the register, it won't have an effect. Thus, we try to sleep long
67	 * enough that the bit gets cleared and make sure the bit is not
68	 * enabled while we update the configuration.
69	 */
70	err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
71	if (err)
72		dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
73
74	return err;
75}
76
77static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
78{
79	return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
80}
81
82static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
83			     int duty_ns, int period_ns)
84{
85	unsigned long long on_time_div;
86	unsigned long c = lpwm->info->clk_rate, base_unit_range;
87	unsigned long long base_unit, freq = NSEC_PER_SEC;
88	u32 ctrl;
89
90	do_div(freq, period_ns);
91
92	/*
93	 * The equation is:
94	 * base_unit = round(base_unit_range * freq / c)
95	 */
96	base_unit_range = BIT(lpwm->info->base_unit_bits);
97	freq *= base_unit_range;
98
99	base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
100	/* base_unit must not be 0 and we also want to avoid overflowing it */
101	base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
102
103	on_time_div = 255ULL * duty_ns;
104	do_div(on_time_div, period_ns);
105	on_time_div = 255ULL - on_time_div;
106
107	ctrl = pwm_lpss_read(pwm);
108	ctrl &= ~PWM_ON_TIME_DIV_MASK;
109	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
110	ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
111	ctrl |= on_time_div;
112
113	pwm_lpss_write(pwm, ctrl);
114	pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
115}
116
117static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
118{
119	if (cond)
120		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
121}
122
123static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
124				   struct pwm_device *pwm,
125				   const struct pwm_state *state)
126{
127	int ret;
128
129	ret = pwm_lpss_is_updating(pwm);
130	if (ret)
131		return ret;
132
133	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
134	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
135	ret = pwm_lpss_wait_for_update(pwm);
136	if (ret)
137		return ret;
138
139	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
140	return 0;
141}
142
143static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
144			  const struct pwm_state *state)
145{
146	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
147	int ret = 0;
148
149	if (state->enabled) {
150		if (!pwm_is_enabled(pwm)) {
151			pm_runtime_get_sync(chip->dev);
152			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
153			if (ret)
154				pm_runtime_put(chip->dev);
155		} else {
156			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
157		}
158	} else if (pwm_is_enabled(pwm)) {
159		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
160		pm_runtime_put(chip->dev);
161	}
162
163	return ret;
164}
165
166static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
167			       struct pwm_state *state)
168{
169	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
170	unsigned long base_unit_range;
171	unsigned long long base_unit, freq, on_time_div;
172	u32 ctrl;
173
174	pm_runtime_get_sync(chip->dev);
175
176	base_unit_range = BIT(lpwm->info->base_unit_bits);
177
178	ctrl = pwm_lpss_read(pwm);
179	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
180	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
181
182	freq = base_unit * lpwm->info->clk_rate;
183	do_div(freq, base_unit_range);
184	if (freq == 0)
185		state->period = NSEC_PER_SEC;
186	else
187		state->period = NSEC_PER_SEC / (unsigned long)freq;
188
189	on_time_div *= state->period;
190	do_div(on_time_div, 255);
191	state->duty_cycle = on_time_div;
192
193	state->polarity = PWM_POLARITY_NORMAL;
194	state->enabled = !!(ctrl & PWM_ENABLE);
195
196	pm_runtime_put(chip->dev);
197}
198
199static const struct pwm_ops pwm_lpss_ops = {
200	.apply = pwm_lpss_apply,
201	.get_state = pwm_lpss_get_state,
202	.owner = THIS_MODULE,
203};
204
205struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
206				     const struct pwm_lpss_boardinfo *info)
207{
208	struct pwm_lpss_chip *lpwm;
209	unsigned long c;
210	int i, ret;
211	u32 ctrl;
212
213	if (WARN_ON(info->npwm > MAX_PWMS))
214		return ERR_PTR(-ENODEV);
215
216	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
217	if (!lpwm)
218		return ERR_PTR(-ENOMEM);
219
220	lpwm->regs = devm_ioremap_resource(dev, r);
221	if (IS_ERR(lpwm->regs))
222		return ERR_CAST(lpwm->regs);
223
224	lpwm->info = info;
225
226	c = lpwm->info->clk_rate;
227	if (!c)
228		return ERR_PTR(-EINVAL);
229
230	lpwm->chip.dev = dev;
231	lpwm->chip.ops = &pwm_lpss_ops;
232	lpwm->chip.base = -1;
233	lpwm->chip.npwm = info->npwm;
234
235	ret = pwmchip_add(&lpwm->chip);
236	if (ret) {
237		dev_err(dev, "failed to add PWM chip: %d\n", ret);
238		return ERR_PTR(ret);
239	}
240
241	for (i = 0; i < lpwm->info->npwm; i++) {
242		ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
243		if (ctrl & PWM_ENABLE)
244			pm_runtime_get(dev);
245	}
246
247	return lpwm;
248}
249EXPORT_SYMBOL_GPL(pwm_lpss_probe);
250
251int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
252{
253	int i;
254
255	for (i = 0; i < lpwm->info->npwm; i++) {
256		if (pwm_is_enabled(&lpwm->chip.pwms[i]))
257			pm_runtime_put(lpwm->chip.dev);
258	}
259	return pwmchip_remove(&lpwm->chip);
260}
261EXPORT_SYMBOL_GPL(pwm_lpss_remove);
262
263MODULE_DESCRIPTION("PWM driver for Intel LPSS");
264MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
265MODULE_LICENSE("GPL v2");
266