18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com> 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#include <linux/clk.h> 78c2ecf20Sopenharmony_ci#include <linux/err.h> 88c2ecf20Sopenharmony_ci#include <linux/io.h> 98c2ecf20Sopenharmony_ci#include <linux/kernel.h> 108c2ecf20Sopenharmony_ci#include <linux/module.h> 118c2ecf20Sopenharmony_ci#include <linux/of.h> 128c2ecf20Sopenharmony_ci#include <linux/of_address.h> 138c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 148c2ecf20Sopenharmony_ci#include <linux/pwm.h> 158c2ecf20Sopenharmony_ci#include <linux/slab.h> 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_cistruct lpc32xx_pwm_chip { 188c2ecf20Sopenharmony_ci struct pwm_chip chip; 198c2ecf20Sopenharmony_ci struct clk *clk; 208c2ecf20Sopenharmony_ci void __iomem *base; 218c2ecf20Sopenharmony_ci}; 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#define PWM_ENABLE BIT(31) 248c2ecf20Sopenharmony_ci#define PWM_PIN_LEVEL BIT(30) 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#define to_lpc32xx_pwm_chip(_chip) \ 278c2ecf20Sopenharmony_ci container_of(_chip, struct lpc32xx_pwm_chip, chip) 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_cistatic int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 308c2ecf20Sopenharmony_ci int duty_ns, int period_ns) 318c2ecf20Sopenharmony_ci{ 328c2ecf20Sopenharmony_ci struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); 338c2ecf20Sopenharmony_ci unsigned long long c; 348c2ecf20Sopenharmony_ci int period_cycles, duty_cycles; 358c2ecf20Sopenharmony_ci u32 val; 368c2ecf20Sopenharmony_ci c = clk_get_rate(lpc32xx->clk); 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci /* The highest acceptable divisor is 256, which is represented by 0 */ 398c2ecf20Sopenharmony_ci period_cycles = div64_u64(c * period_ns, 408c2ecf20Sopenharmony_ci (unsigned long long)NSEC_PER_SEC * 256); 418c2ecf20Sopenharmony_ci if (!period_cycles || period_cycles > 256) 428c2ecf20Sopenharmony_ci return -ERANGE; 438c2ecf20Sopenharmony_ci if (period_cycles == 256) 448c2ecf20Sopenharmony_ci period_cycles = 0; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci /* Compute 256 x #duty/period value and care for corner cases */ 478c2ecf20Sopenharmony_ci duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256, 488c2ecf20Sopenharmony_ci period_ns); 498c2ecf20Sopenharmony_ci if (!duty_cycles) 508c2ecf20Sopenharmony_ci duty_cycles = 1; 518c2ecf20Sopenharmony_ci if (duty_cycles > 255) 528c2ecf20Sopenharmony_ci duty_cycles = 255; 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci val = readl(lpc32xx->base); 558c2ecf20Sopenharmony_ci val &= ~0xFFFF; 568c2ecf20Sopenharmony_ci val |= (period_cycles << 8) | duty_cycles; 578c2ecf20Sopenharmony_ci writel(val, lpc32xx->base); 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci return 0; 608c2ecf20Sopenharmony_ci} 618c2ecf20Sopenharmony_ci 628c2ecf20Sopenharmony_cistatic int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 638c2ecf20Sopenharmony_ci{ 648c2ecf20Sopenharmony_ci struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); 658c2ecf20Sopenharmony_ci u32 val; 668c2ecf20Sopenharmony_ci int ret; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci ret = clk_prepare_enable(lpc32xx->clk); 698c2ecf20Sopenharmony_ci if (ret) 708c2ecf20Sopenharmony_ci return ret; 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci val = readl(lpc32xx->base); 738c2ecf20Sopenharmony_ci val |= PWM_ENABLE; 748c2ecf20Sopenharmony_ci writel(val, lpc32xx->base); 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci return 0; 778c2ecf20Sopenharmony_ci} 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_cistatic void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 808c2ecf20Sopenharmony_ci{ 818c2ecf20Sopenharmony_ci struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); 828c2ecf20Sopenharmony_ci u32 val; 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci val = readl(lpc32xx->base); 858c2ecf20Sopenharmony_ci val &= ~PWM_ENABLE; 868c2ecf20Sopenharmony_ci writel(val, lpc32xx->base); 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci clk_disable_unprepare(lpc32xx->clk); 898c2ecf20Sopenharmony_ci} 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_cistatic const struct pwm_ops lpc32xx_pwm_ops = { 928c2ecf20Sopenharmony_ci .config = lpc32xx_pwm_config, 938c2ecf20Sopenharmony_ci .enable = lpc32xx_pwm_enable, 948c2ecf20Sopenharmony_ci .disable = lpc32xx_pwm_disable, 958c2ecf20Sopenharmony_ci .owner = THIS_MODULE, 968c2ecf20Sopenharmony_ci}; 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_cistatic int lpc32xx_pwm_probe(struct platform_device *pdev) 998c2ecf20Sopenharmony_ci{ 1008c2ecf20Sopenharmony_ci struct lpc32xx_pwm_chip *lpc32xx; 1018c2ecf20Sopenharmony_ci struct resource *res; 1028c2ecf20Sopenharmony_ci int ret; 1038c2ecf20Sopenharmony_ci u32 val; 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL); 1068c2ecf20Sopenharmony_ci if (!lpc32xx) 1078c2ecf20Sopenharmony_ci return -ENOMEM; 1088c2ecf20Sopenharmony_ci 1098c2ecf20Sopenharmony_ci res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1108c2ecf20Sopenharmony_ci lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); 1118c2ecf20Sopenharmony_ci if (IS_ERR(lpc32xx->base)) 1128c2ecf20Sopenharmony_ci return PTR_ERR(lpc32xx->base); 1138c2ecf20Sopenharmony_ci 1148c2ecf20Sopenharmony_ci lpc32xx->clk = devm_clk_get(&pdev->dev, NULL); 1158c2ecf20Sopenharmony_ci if (IS_ERR(lpc32xx->clk)) 1168c2ecf20Sopenharmony_ci return PTR_ERR(lpc32xx->clk); 1178c2ecf20Sopenharmony_ci 1188c2ecf20Sopenharmony_ci lpc32xx->chip.dev = &pdev->dev; 1198c2ecf20Sopenharmony_ci lpc32xx->chip.ops = &lpc32xx_pwm_ops; 1208c2ecf20Sopenharmony_ci lpc32xx->chip.npwm = 1; 1218c2ecf20Sopenharmony_ci lpc32xx->chip.base = -1; 1228c2ecf20Sopenharmony_ci 1238c2ecf20Sopenharmony_ci /* If PWM is disabled, configure the output to the default value */ 1248c2ecf20Sopenharmony_ci val = readl(lpc32xx->base); 1258c2ecf20Sopenharmony_ci val &= ~PWM_PIN_LEVEL; 1268c2ecf20Sopenharmony_ci writel(val, lpc32xx->base); 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci ret = pwmchip_add(&lpc32xx->chip); 1298c2ecf20Sopenharmony_ci if (ret < 0) { 1308c2ecf20Sopenharmony_ci dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret); 1318c2ecf20Sopenharmony_ci return ret; 1328c2ecf20Sopenharmony_ci } 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci platform_set_drvdata(pdev, lpc32xx); 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ci return 0; 1378c2ecf20Sopenharmony_ci} 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_cistatic int lpc32xx_pwm_remove(struct platform_device *pdev) 1408c2ecf20Sopenharmony_ci{ 1418c2ecf20Sopenharmony_ci struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev); 1428c2ecf20Sopenharmony_ci unsigned int i; 1438c2ecf20Sopenharmony_ci 1448c2ecf20Sopenharmony_ci for (i = 0; i < lpc32xx->chip.npwm; i++) 1458c2ecf20Sopenharmony_ci pwm_disable(&lpc32xx->chip.pwms[i]); 1468c2ecf20Sopenharmony_ci 1478c2ecf20Sopenharmony_ci return pwmchip_remove(&lpc32xx->chip); 1488c2ecf20Sopenharmony_ci} 1498c2ecf20Sopenharmony_ci 1508c2ecf20Sopenharmony_cistatic const struct of_device_id lpc32xx_pwm_dt_ids[] = { 1518c2ecf20Sopenharmony_ci { .compatible = "nxp,lpc3220-pwm", }, 1528c2ecf20Sopenharmony_ci { /* sentinel */ } 1538c2ecf20Sopenharmony_ci}; 1548c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids); 1558c2ecf20Sopenharmony_ci 1568c2ecf20Sopenharmony_cistatic struct platform_driver lpc32xx_pwm_driver = { 1578c2ecf20Sopenharmony_ci .driver = { 1588c2ecf20Sopenharmony_ci .name = "lpc32xx-pwm", 1598c2ecf20Sopenharmony_ci .of_match_table = lpc32xx_pwm_dt_ids, 1608c2ecf20Sopenharmony_ci }, 1618c2ecf20Sopenharmony_ci .probe = lpc32xx_pwm_probe, 1628c2ecf20Sopenharmony_ci .remove = lpc32xx_pwm_remove, 1638c2ecf20Sopenharmony_ci}; 1648c2ecf20Sopenharmony_cimodule_platform_driver(lpc32xx_pwm_driver); 1658c2ecf20Sopenharmony_ci 1668c2ecf20Sopenharmony_ciMODULE_ALIAS("platform:lpc32xx-pwm"); 1678c2ecf20Sopenharmony_ciMODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>"); 1688c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("LPC32XX PWM Driver"); 1698c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2"); 170