1// SPDX-License-Identifier: GPL-2.0
2/*
3 * simple driver for PWM (Pulse Width Modulator) controller
4 *
5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
6 *
7 * Limitations:
8 * - When disabled the output is driven to 0 independent of the configured
9 *   polarity.
10 */
11
12#include <linux/bitfield.h>
13#include <linux/bitops.h>
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pwm.h>
23#include <linux/slab.h>
24
25#define MX3_PWMCR			0x00    /* PWM Control Register */
26#define MX3_PWMSR			0x04    /* PWM Status Register */
27#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
28#define MX3_PWMPR			0x10    /* PWM Period Register */
29
30#define MX3_PWMCR_FWM			GENMASK(27, 26)
31#define MX3_PWMCR_STOPEN		BIT(25)
32#define MX3_PWMCR_DOZEN			BIT(24)
33#define MX3_PWMCR_WAITEN		BIT(23)
34#define MX3_PWMCR_DBGEN			BIT(22)
35#define MX3_PWMCR_BCTR			BIT(21)
36#define MX3_PWMCR_HCTR			BIT(20)
37
38#define MX3_PWMCR_POUTC			GENMASK(19, 18)
39#define MX3_PWMCR_POUTC_NORMAL		0
40#define MX3_PWMCR_POUTC_INVERTED	1
41#define MX3_PWMCR_POUTC_OFF		2
42
43#define MX3_PWMCR_CLKSRC		GENMASK(17, 16)
44#define MX3_PWMCR_CLKSRC_OFF		0
45#define MX3_PWMCR_CLKSRC_IPG		1
46#define MX3_PWMCR_CLKSRC_IPG_HIGH	2
47#define MX3_PWMCR_CLKSRC_IPG_32K	3
48
49#define MX3_PWMCR_PRESCALER		GENMASK(15, 4)
50
51#define MX3_PWMCR_SWR			BIT(3)
52
53#define MX3_PWMCR_REPEAT		GENMASK(2, 1)
54#define MX3_PWMCR_REPEAT_1X		0
55#define MX3_PWMCR_REPEAT_2X		1
56#define MX3_PWMCR_REPEAT_4X		2
57#define MX3_PWMCR_REPEAT_8X		3
58
59#define MX3_PWMCR_EN			BIT(0)
60
61#define MX3_PWMSR_FWE			BIT(6)
62#define MX3_PWMSR_CMP			BIT(5)
63#define MX3_PWMSR_ROV			BIT(4)
64#define MX3_PWMSR_FE			BIT(3)
65
66#define MX3_PWMSR_FIFOAV		GENMASK(2, 0)
67#define MX3_PWMSR_FIFOAV_EMPTY		0
68#define MX3_PWMSR_FIFOAV_1WORD		1
69#define MX3_PWMSR_FIFOAV_2WORDS		2
70#define MX3_PWMSR_FIFOAV_3WORDS		3
71#define MX3_PWMSR_FIFOAV_4WORDS		4
72
73#define MX3_PWMCR_PRESCALER_SET(x)	FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
74#define MX3_PWMCR_PRESCALER_GET(x)	(FIELD_GET(MX3_PWMCR_PRESCALER, \
75						   (x)) + 1)
76
77#define MX3_PWM_SWR_LOOP		5
78
79/* PWMPR register value of 0xffff has the same effect as 0xfffe */
80#define MX3_PWMPR_MAX			0xfffe
81
82struct pwm_imx27_chip {
83	struct clk	*clk_ipg;
84	struct clk	*clk_per;
85	void __iomem	*mmio_base;
86	struct pwm_chip	chip;
87
88	/*
89	 * The driver cannot read the current duty cycle from the hardware if
90	 * the hardware is disabled. Cache the last programmed duty cycle
91	 * value to return in that case.
92	 */
93	unsigned int duty_cycle;
94};
95
96#define to_pwm_imx27_chip(chip)	container_of(chip, struct pwm_imx27_chip, chip)
97
98static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
99{
100	int ret;
101
102	ret = clk_prepare_enable(imx->clk_ipg);
103	if (ret)
104		return ret;
105
106	ret = clk_prepare_enable(imx->clk_per);
107	if (ret) {
108		clk_disable_unprepare(imx->clk_ipg);
109		return ret;
110	}
111
112	return 0;
113}
114
115static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
116{
117	clk_disable_unprepare(imx->clk_per);
118	clk_disable_unprepare(imx->clk_ipg);
119}
120
121static void pwm_imx27_get_state(struct pwm_chip *chip,
122				struct pwm_device *pwm, struct pwm_state *state)
123{
124	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
125	u32 period, prescaler, pwm_clk, val;
126	u64 tmp;
127	int ret;
128
129	ret = pwm_imx27_clk_prepare_enable(imx);
130	if (ret < 0)
131		return;
132
133	val = readl(imx->mmio_base + MX3_PWMCR);
134
135	if (val & MX3_PWMCR_EN)
136		state->enabled = true;
137	else
138		state->enabled = false;
139
140	switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
141	case MX3_PWMCR_POUTC_NORMAL:
142		state->polarity = PWM_POLARITY_NORMAL;
143		break;
144	case MX3_PWMCR_POUTC_INVERTED:
145		state->polarity = PWM_POLARITY_INVERSED;
146		break;
147	default:
148		dev_warn(chip->dev, "can't set polarity, output disconnected");
149	}
150
151	prescaler = MX3_PWMCR_PRESCALER_GET(val);
152	pwm_clk = clk_get_rate(imx->clk_per);
153	val = readl(imx->mmio_base + MX3_PWMPR);
154	period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
155
156	/* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
157	tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
158	state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
159
160	/*
161	 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
162	 * use the cached value.
163	 */
164	if (state->enabled)
165		val = readl(imx->mmio_base + MX3_PWMSAR);
166	else
167		val = imx->duty_cycle;
168
169	tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
170	state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
171
172	pwm_imx27_clk_disable_unprepare(imx);
173}
174
175static void pwm_imx27_sw_reset(struct pwm_chip *chip)
176{
177	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
178	struct device *dev = chip->dev;
179	int wait_count = 0;
180	u32 cr;
181
182	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
183	do {
184		usleep_range(200, 1000);
185		cr = readl(imx->mmio_base + MX3_PWMCR);
186	} while ((cr & MX3_PWMCR_SWR) &&
187		 (wait_count++ < MX3_PWM_SWR_LOOP));
188
189	if (cr & MX3_PWMCR_SWR)
190		dev_warn(dev, "software reset timeout\n");
191}
192
193static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
194				     struct pwm_device *pwm)
195{
196	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
197	struct device *dev = chip->dev;
198	unsigned int period_ms;
199	int fifoav;
200	u32 sr;
201
202	sr = readl(imx->mmio_base + MX3_PWMSR);
203	fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
204	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
205		period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
206					 NSEC_PER_MSEC);
207		msleep(period_ms);
208
209		sr = readl(imx->mmio_base + MX3_PWMSR);
210		if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
211			dev_warn(dev, "there is no free FIFO slot\n");
212	}
213}
214
215static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
216			   const struct pwm_state *state)
217{
218	unsigned long period_cycles, duty_cycles, prescale;
219	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
220	struct pwm_state cstate;
221	unsigned long long c;
222	unsigned long long clkrate;
223	int ret;
224	u32 cr;
225
226	pwm_get_state(pwm, &cstate);
227
228	clkrate = clk_get_rate(imx->clk_per);
229	c = clkrate * state->period;
230
231	do_div(c, NSEC_PER_SEC);
232	period_cycles = c;
233
234	prescale = period_cycles / 0x10000 + 1;
235
236	period_cycles /= prescale;
237	c = clkrate * state->duty_cycle;
238	do_div(c, NSEC_PER_SEC);
239	duty_cycles = c;
240	duty_cycles /= prescale;
241
242	/*
243	 * according to imx pwm RM, the real period value should be PERIOD
244	 * value in PWMPR plus 2.
245	 */
246	if (period_cycles > 2)
247		period_cycles -= 2;
248	else
249		period_cycles = 0;
250
251	/*
252	 * Wait for a free FIFO slot if the PWM is already enabled, and flush
253	 * the FIFO if the PWM was disabled and is about to be enabled.
254	 */
255	if (cstate.enabled) {
256		pwm_imx27_wait_fifo_slot(chip, pwm);
257	} else {
258		ret = pwm_imx27_clk_prepare_enable(imx);
259		if (ret)
260			return ret;
261
262		pwm_imx27_sw_reset(chip);
263	}
264
265	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
266	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
267
268	/*
269	 * Store the duty cycle for future reference in cases where the
270	 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
271	 */
272	imx->duty_cycle = duty_cycles;
273
274	cr = MX3_PWMCR_PRESCALER_SET(prescale) |
275	     MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
276	     FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
277	     MX3_PWMCR_DBGEN;
278
279	if (state->polarity == PWM_POLARITY_INVERSED)
280		cr |= FIELD_PREP(MX3_PWMCR_POUTC,
281				MX3_PWMCR_POUTC_INVERTED);
282
283	if (state->enabled)
284		cr |= MX3_PWMCR_EN;
285
286	writel(cr, imx->mmio_base + MX3_PWMCR);
287
288	if (!state->enabled)
289		pwm_imx27_clk_disable_unprepare(imx);
290
291	return 0;
292}
293
294static const struct pwm_ops pwm_imx27_ops = {
295	.apply = pwm_imx27_apply,
296	.get_state = pwm_imx27_get_state,
297	.owner = THIS_MODULE,
298};
299
300static const struct of_device_id pwm_imx27_dt_ids[] = {
301	{ .compatible = "fsl,imx27-pwm", },
302	{ /* sentinel */ }
303};
304MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
305
306static int pwm_imx27_probe(struct platform_device *pdev)
307{
308	struct pwm_imx27_chip *imx;
309	int ret;
310	u32 pwmcr;
311
312	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
313	if (imx == NULL)
314		return -ENOMEM;
315
316	platform_set_drvdata(pdev, imx);
317
318	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
319	if (IS_ERR(imx->clk_ipg)) {
320		int ret = PTR_ERR(imx->clk_ipg);
321
322		if (ret != -EPROBE_DEFER)
323			dev_err(&pdev->dev,
324				"getting ipg clock failed with %d\n",
325				ret);
326		return ret;
327	}
328
329	imx->clk_per = devm_clk_get(&pdev->dev, "per");
330	if (IS_ERR(imx->clk_per)) {
331		int ret = PTR_ERR(imx->clk_per);
332
333		if (ret != -EPROBE_DEFER)
334			dev_err(&pdev->dev,
335				"failed to get peripheral clock: %d\n",
336				ret);
337
338		return ret;
339	}
340
341	imx->chip.ops = &pwm_imx27_ops;
342	imx->chip.dev = &pdev->dev;
343	imx->chip.base = -1;
344	imx->chip.npwm = 1;
345
346	imx->chip.of_xlate = of_pwm_xlate_with_flags;
347	imx->chip.of_pwm_n_cells = 3;
348
349	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
350	if (IS_ERR(imx->mmio_base))
351		return PTR_ERR(imx->mmio_base);
352
353	ret = pwm_imx27_clk_prepare_enable(imx);
354	if (ret)
355		return ret;
356
357	/* keep clks on if pwm is running */
358	pwmcr = readl(imx->mmio_base + MX3_PWMCR);
359	if (!(pwmcr & MX3_PWMCR_EN))
360		pwm_imx27_clk_disable_unprepare(imx);
361
362	return pwmchip_add(&imx->chip);
363}
364
365static int pwm_imx27_remove(struct platform_device *pdev)
366{
367	struct pwm_imx27_chip *imx;
368
369	imx = platform_get_drvdata(pdev);
370
371	return pwmchip_remove(&imx->chip);
372}
373
374static struct platform_driver imx_pwm_driver = {
375	.driver = {
376		.name = "pwm-imx27",
377		.of_match_table = pwm_imx27_dt_ids,
378	},
379	.probe = pwm_imx27_probe,
380	.remove = pwm_imx27_remove,
381};
382module_platform_driver(imx_pwm_driver);
383
384MODULE_LICENSE("GPL v2");
385MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
386