1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Expose a PWM controlled by the ChromeOS EC to the host processor.
4 *
5 * Copyright (C) 2016 Google, Inc.
6 */
7
8#include <linux/module.h>
9#include <linux/platform_data/cros_ec_commands.h>
10#include <linux/platform_data/cros_ec_proto.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13#include <linux/slab.h>
14
15/**
16 * struct cros_ec_pwm_device - Driver data for EC PWM
17 *
18 * @dev: Device node
19 * @ec: Pointer to EC device
20 * @chip: PWM controller chip
21 */
22struct cros_ec_pwm_device {
23	struct device *dev;
24	struct cros_ec_device *ec;
25	struct pwm_chip chip;
26};
27
28/**
29 * struct cros_ec_pwm - per-PWM driver data
30 * @duty_cycle: cached duty cycle
31 */
32struct cros_ec_pwm {
33	u16 duty_cycle;
34};
35
36static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
37{
38	return container_of(c, struct cros_ec_pwm_device, chip);
39}
40
41static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
42{
43	struct cros_ec_pwm *channel;
44
45	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
46	if (!channel)
47		return -ENOMEM;
48
49	pwm_set_chip_data(pwm, channel);
50
51	return 0;
52}
53
54static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
55{
56	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
57
58	kfree(channel);
59}
60
61static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
62{
63	struct {
64		struct cros_ec_command msg;
65		struct ec_params_pwm_set_duty params;
66	} __packed buf;
67	struct ec_params_pwm_set_duty *params = &buf.params;
68	struct cros_ec_command *msg = &buf.msg;
69
70	memset(&buf, 0, sizeof(buf));
71
72	msg->version = 0;
73	msg->command = EC_CMD_PWM_SET_DUTY;
74	msg->insize = 0;
75	msg->outsize = sizeof(*params);
76
77	params->duty = duty;
78	params->pwm_type = EC_PWM_TYPE_GENERIC;
79	params->index = index;
80
81	return cros_ec_cmd_xfer_status(ec, msg);
82}
83
84static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
85{
86	struct {
87		struct cros_ec_command msg;
88		union {
89			struct ec_params_pwm_get_duty params;
90			struct ec_response_pwm_get_duty resp;
91		};
92	} __packed buf;
93	struct ec_params_pwm_get_duty *params = &buf.params;
94	struct ec_response_pwm_get_duty *resp = &buf.resp;
95	struct cros_ec_command *msg = &buf.msg;
96	int ret;
97
98	memset(&buf, 0, sizeof(buf));
99
100	msg->version = 0;
101	msg->command = EC_CMD_PWM_GET_DUTY;
102	msg->insize = sizeof(*resp);
103	msg->outsize = sizeof(*params);
104
105	params->pwm_type = EC_PWM_TYPE_GENERIC;
106	params->index = index;
107
108	ret = cros_ec_cmd_xfer_status(ec, msg);
109	if (ret < 0)
110		return ret;
111
112	return resp->duty;
113}
114
115static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
116			     const struct pwm_state *state)
117{
118	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
119	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
120	u16 duty_cycle;
121	int ret;
122
123	/* The EC won't let us change the period */
124	if (state->period != EC_PWM_MAX_DUTY)
125		return -EINVAL;
126
127	/*
128	 * EC doesn't separate the concept of duty cycle and enabled, but
129	 * kernel does. Translate.
130	 */
131	duty_cycle = state->enabled ? state->duty_cycle : 0;
132
133	ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
134	if (ret < 0)
135		return ret;
136
137	channel->duty_cycle = state->duty_cycle;
138
139	return 0;
140}
141
142static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
143				  struct pwm_state *state)
144{
145	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
146	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
147	int ret;
148
149	ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
150	if (ret < 0) {
151		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
152		return;
153	}
154
155	state->enabled = (ret > 0);
156	state->period = EC_PWM_MAX_DUTY;
157	state->polarity = PWM_POLARITY_NORMAL;
158
159	/*
160	 * Note that "disabled" and "duty cycle == 0" are treated the same. If
161	 * the cached duty cycle is not zero, used the cached duty cycle. This
162	 * ensures that the configured duty cycle is kept across a disable and
163	 * enable operation and avoids potentially confusing consumers.
164	 *
165	 * For the case of the initial hardware readout, channel->duty_cycle
166	 * will be 0 and the actual duty cycle read from the EC is used.
167	 */
168	if (ret == 0 && channel->duty_cycle > 0)
169		state->duty_cycle = channel->duty_cycle;
170	else
171		state->duty_cycle = ret;
172}
173
174static struct pwm_device *
175cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
176{
177	struct pwm_device *pwm;
178
179	if (args->args[0] >= pc->npwm)
180		return ERR_PTR(-EINVAL);
181
182	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
183	if (IS_ERR(pwm))
184		return pwm;
185
186	/* The EC won't let us change the period */
187	pwm->args.period = EC_PWM_MAX_DUTY;
188
189	return pwm;
190}
191
192static const struct pwm_ops cros_ec_pwm_ops = {
193	.request = cros_ec_pwm_request,
194	.free = cros_ec_pwm_free,
195	.get_state	= cros_ec_pwm_get_state,
196	.apply		= cros_ec_pwm_apply,
197	.owner		= THIS_MODULE,
198};
199
200/*
201 * Determine the number of supported PWMs. The EC does not return the number
202 * of PWMs it supports directly, so we have to read the pwm duty cycle for
203 * subsequent channels until we get an error.
204 */
205static int cros_ec_num_pwms(struct cros_ec_device *ec)
206{
207	int i, ret;
208
209	/* The index field is only 8 bits */
210	for (i = 0; i <= U8_MAX; i++) {
211		ret = cros_ec_pwm_get_duty(ec, i);
212		/*
213		 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
214		 * responses; everything else is treated as an error.
215		 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
216		 * so check for those.
217		 */
218		switch (ret) {
219		case -EOPNOTSUPP:	/* invalid command */
220			return -ENODEV;
221		case -EINVAL:		/* invalid parameter */
222			return i;
223		default:
224			if (ret < 0)
225				return ret;
226			break;
227		}
228	}
229
230	return U8_MAX;
231}
232
233static int cros_ec_pwm_probe(struct platform_device *pdev)
234{
235	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
236	struct device *dev = &pdev->dev;
237	struct cros_ec_pwm_device *ec_pwm;
238	struct pwm_chip *chip;
239	int ret;
240
241	if (!ec) {
242		dev_err(dev, "no parent EC device\n");
243		return -EINVAL;
244	}
245
246	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
247	if (!ec_pwm)
248		return -ENOMEM;
249	chip = &ec_pwm->chip;
250	ec_pwm->ec = ec;
251
252	/* PWM chip */
253	chip->dev = dev;
254	chip->ops = &cros_ec_pwm_ops;
255	chip->of_xlate = cros_ec_pwm_xlate;
256	chip->of_pwm_n_cells = 1;
257	chip->base = -1;
258	ret = cros_ec_num_pwms(ec);
259	if (ret < 0) {
260		dev_err(dev, "Couldn't find PWMs: %d\n", ret);
261		return ret;
262	}
263	chip->npwm = ret;
264	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
265
266	ret = pwmchip_add(chip);
267	if (ret < 0) {
268		dev_err(dev, "cannot register PWM: %d\n", ret);
269		return ret;
270	}
271
272	platform_set_drvdata(pdev, ec_pwm);
273
274	return ret;
275}
276
277static int cros_ec_pwm_remove(struct platform_device *dev)
278{
279	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
280	struct pwm_chip *chip = &ec_pwm->chip;
281
282	return pwmchip_remove(chip);
283}
284
285#ifdef CONFIG_OF
286static const struct of_device_id cros_ec_pwm_of_match[] = {
287	{ .compatible = "google,cros-ec-pwm" },
288	{},
289};
290MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
291#endif
292
293static struct platform_driver cros_ec_pwm_driver = {
294	.probe = cros_ec_pwm_probe,
295	.remove = cros_ec_pwm_remove,
296	.driver = {
297		.name = "cros-ec-pwm",
298		.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
299	},
300};
301module_platform_driver(cros_ec_pwm_driver);
302
303MODULE_ALIAS("platform:cros-ec-pwm");
304MODULE_DESCRIPTION("ChromeOS EC PWM driver");
305MODULE_LICENSE("GPL v2");
306