1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2/* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9#include <linux/device.h> 10#include <linux/dmi.h> 11#include <linux/i2c.h> 12#include <linux/i2c-mux.h> 13#include <linux/io.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/platform_data/i2c-mux-reg.h> 17#include <linux/platform_data/mlxreg.h> 18#include <linux/regmap.h> 19 20#define MLX_PLAT_DEVICE_NAME "mlxplat" 21 22/* LPC bus IO offsets */ 23#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 24#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 25#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 26#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 27#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 28#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 29#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 30#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 31#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 32#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 33#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 34#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 35#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 36#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 37#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 38#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 39#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 40#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 41#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 42#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 43#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 44#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 45#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 46#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 47#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 48#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 49#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 50#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 51#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 52#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 53#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 54#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 55#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 56#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 57#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 58#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 59#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 60#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 61#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 62#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 63#define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 64#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 65#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 66#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 67#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 68#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 69#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 70#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 71#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 72#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 73#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 74#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 75#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 76#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 77#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 78#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 79#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 80#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 81#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 82#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 83#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 84#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 85#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 86#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 87#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 88#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 89#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 90#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 91#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 92#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 93#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 94#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 95#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 96#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 97#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 98#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 99#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 100#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 101#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 102#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 103#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 104#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 105#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 106#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 107#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc 108 109#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 110#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 111 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ 112 MLXPLAT_CPLD_LPC_PIO_OFFSET) 113#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 114 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ 115 MLXPLAT_CPLD_LPC_PIO_OFFSET) 116#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 117 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ 118 MLXPLAT_CPLD_LPC_PIO_OFFSET) 119 120/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 121#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 122#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 123#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 124#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 125#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 126 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 127 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 128#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 129#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 130#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 131#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 132#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 133#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 134#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 135#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 136#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 137#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 138#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 139#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(5, 0) 140#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 141#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 142#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 143#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 144#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 145 146/* Masks for aggregation for comex carriers */ 147#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 148#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 149 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 150#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 151 152/* Default I2C parent bus number */ 153#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 154 155/* Maximum number of possible physical buses equipped on system */ 156#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 157#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 158 159/* Number of channels in group */ 160#define MLXPLAT_CPLD_GRP_CHNL_NUM 8 161 162/* Start channel numbers */ 163#define MLXPLAT_CPLD_CH1 2 164#define MLXPLAT_CPLD_CH2 10 165#define MLXPLAT_CPLD_CH3 18 166 167/* Number of LPC attached MUX platform devices */ 168#define MLXPLAT_CPLD_LPC_MUX_DEVS 3 169 170/* Hotplug devices adapter numbers */ 171#define MLXPLAT_CPLD_NR_NONE -1 172#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 173#define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 174#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 175#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 176#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 177#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 178 179/* Masks and default values for watchdogs */ 180#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 181#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 182 183#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 184#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 185#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 186#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 187#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 188#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 189#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 190#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 191#define MLXPLAT_CPLD_WD_MAX_DEVS 2 192 193/* mlxplat_priv - platform private data 194 * @pdev_i2c - i2c controller platform device 195 * @pdev_mux - array of mux platform devices 196 * @pdev_hotplug - hotplug platform devices 197 * @pdev_led - led platform devices 198 * @pdev_io_regs - register access platform devices 199 * @pdev_fan - FAN platform devices 200 * @pdev_wd - array of watchdog platform devices 201 * @regmap: device register map 202 */ 203struct mlxplat_priv { 204 struct platform_device *pdev_i2c; 205 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 206 struct platform_device *pdev_hotplug; 207 struct platform_device *pdev_led; 208 struct platform_device *pdev_io_regs; 209 struct platform_device *pdev_fan; 210 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 211 void *regmap; 212}; 213 214/* Regions for LPC I2C controller and LPC base register space */ 215static const struct resource mlxplat_lpc_resources[] = { 216 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 217 MLXPLAT_CPLD_LPC_IO_RANGE, 218 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 219 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 220 MLXPLAT_CPLD_LPC_IO_RANGE, 221 "mlxplat_cpld_lpc_regs", 222 IORESOURCE_IO), 223}; 224 225/* Platform i2c next generation systems data */ 226static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 227 { 228 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 229 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 230 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 231 }, 232}; 233 234static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 235 { 236 .data = mlxplat_mlxcpld_i2c_ng_items_data, 237 }, 238}; 239 240/* Platform next generation systems i2c data */ 241static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 242 .items = mlxplat_mlxcpld_i2c_ng_items, 243 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 244 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 245 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 246 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 247}; 248 249/* Platform default channels */ 250static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 251 { 252 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 253 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 254 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 255 }, 256 { 257 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 258 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 259 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 260 }, 261}; 262 263/* Platform channels for MSN21xx system family */ 264static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 265 266/* Platform mux data */ 267static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 268 { 269 .parent = 1, 270 .base_nr = MLXPLAT_CPLD_CH1, 271 .write_only = 1, 272 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 273 .reg_size = 1, 274 .idle_in_use = 1, 275 }, 276 { 277 .parent = 1, 278 .base_nr = MLXPLAT_CPLD_CH2, 279 .write_only = 1, 280 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 281 .reg_size = 1, 282 .idle_in_use = 1, 283 }, 284 285}; 286 287/* Platform mux configuration variables */ 288static int mlxplat_max_adap_num; 289static int mlxplat_mux_num; 290static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 291 292/* Platform extended mux data */ 293static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 294 { 295 .parent = 1, 296 .base_nr = MLXPLAT_CPLD_CH1, 297 .write_only = 1, 298 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 299 .reg_size = 1, 300 .idle_in_use = 1, 301 }, 302 { 303 .parent = 1, 304 .base_nr = MLXPLAT_CPLD_CH2, 305 .write_only = 1, 306 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 307 .reg_size = 1, 308 .idle_in_use = 1, 309 }, 310 { 311 .parent = 1, 312 .base_nr = MLXPLAT_CPLD_CH3, 313 .write_only = 1, 314 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 315 .reg_size = 1, 316 .idle_in_use = 1, 317 }, 318 319}; 320 321/* Platform hotplug devices */ 322static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 323 { 324 I2C_BOARD_INFO("dps460", 0x59), 325 }, 326 { 327 I2C_BOARD_INFO("dps460", 0x58), 328 }, 329}; 330 331static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 332 { 333 I2C_BOARD_INFO("dps460", 0x5b), 334 }, 335 { 336 I2C_BOARD_INFO("dps460", 0x5a), 337 }, 338}; 339 340static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 341 { 342 I2C_BOARD_INFO("24c32", 0x50), 343 }, 344 { 345 I2C_BOARD_INFO("24c32", 0x50), 346 }, 347 { 348 I2C_BOARD_INFO("24c32", 0x50), 349 }, 350 { 351 I2C_BOARD_INFO("24c32", 0x50), 352 }, 353}; 354 355/* Platform hotplug comex carrier system family data */ 356static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 357 { 358 .label = "psu1", 359 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 360 .mask = BIT(0), 361 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 362 }, 363 { 364 .label = "psu2", 365 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 366 .mask = BIT(1), 367 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 368 }, 369}; 370 371/* Platform hotplug default data */ 372static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 373 { 374 .label = "psu1", 375 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 376 .mask = BIT(0), 377 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 378 }, 379 { 380 .label = "psu2", 381 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 382 .mask = BIT(1), 383 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 384 }, 385}; 386 387static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 388 { 389 .label = "pwr1", 390 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 391 .mask = BIT(0), 392 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 393 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 394 }, 395 { 396 .label = "pwr2", 397 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 398 .mask = BIT(1), 399 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 400 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 401 }, 402}; 403 404static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 405 { 406 .label = "fan1", 407 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 408 .mask = BIT(0), 409 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 410 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 411 }, 412 { 413 .label = "fan2", 414 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 415 .mask = BIT(1), 416 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 417 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 418 }, 419 { 420 .label = "fan3", 421 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 422 .mask = BIT(2), 423 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 424 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 425 }, 426 { 427 .label = "fan4", 428 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 429 .mask = BIT(3), 430 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 431 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 432 }, 433}; 434 435static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 436 { 437 .label = "asic1", 438 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 439 .mask = MLXPLAT_CPLD_ASIC_MASK, 440 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 441 }, 442}; 443 444static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 445 { 446 .data = mlxplat_mlxcpld_default_psu_items_data, 447 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 448 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 449 .mask = MLXPLAT_CPLD_PSU_MASK, 450 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 451 .inversed = 1, 452 .health = false, 453 }, 454 { 455 .data = mlxplat_mlxcpld_default_pwr_items_data, 456 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 457 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 458 .mask = MLXPLAT_CPLD_PWR_MASK, 459 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 460 .inversed = 0, 461 .health = false, 462 }, 463 { 464 .data = mlxplat_mlxcpld_default_fan_items_data, 465 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 466 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 467 .mask = MLXPLAT_CPLD_FAN_MASK, 468 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 469 .inversed = 1, 470 .health = false, 471 }, 472 { 473 .data = mlxplat_mlxcpld_default_asic_items_data, 474 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 475 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 476 .mask = MLXPLAT_CPLD_ASIC_MASK, 477 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 478 .inversed = 0, 479 .health = true, 480 }, 481}; 482 483static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 484 { 485 .data = mlxplat_mlxcpld_comex_psu_items_data, 486 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 487 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 488 .mask = MLXPLAT_CPLD_PSU_MASK, 489 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 490 .inversed = 1, 491 .health = false, 492 }, 493 { 494 .data = mlxplat_mlxcpld_default_pwr_items_data, 495 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 496 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 497 .mask = MLXPLAT_CPLD_PWR_MASK, 498 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 499 .inversed = 0, 500 .health = false, 501 }, 502 { 503 .data = mlxplat_mlxcpld_default_fan_items_data, 504 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 505 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 506 .mask = MLXPLAT_CPLD_FAN_MASK, 507 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 508 .inversed = 1, 509 .health = false, 510 }, 511 { 512 .data = mlxplat_mlxcpld_default_asic_items_data, 513 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 514 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 515 .mask = MLXPLAT_CPLD_ASIC_MASK, 516 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 517 .inversed = 0, 518 .health = true, 519 }, 520}; 521 522static 523struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 524 .items = mlxplat_mlxcpld_default_items, 525 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 526 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 527 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 528 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 529 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 530}; 531 532static 533struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 534 .items = mlxplat_mlxcpld_comex_items, 535 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 536 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 537 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 538 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 539 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 540}; 541 542static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 543 { 544 .label = "pwr1", 545 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 546 .mask = BIT(0), 547 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 548 }, 549 { 550 .label = "pwr2", 551 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 552 .mask = BIT(1), 553 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 554 }, 555}; 556 557/* Platform hotplug MSN21xx system family data */ 558static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 559 { 560 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 561 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 562 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 563 .mask = MLXPLAT_CPLD_PWR_MASK, 564 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 565 .inversed = 0, 566 .health = false, 567 }, 568 { 569 .data = mlxplat_mlxcpld_default_asic_items_data, 570 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 571 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 572 .mask = MLXPLAT_CPLD_ASIC_MASK, 573 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 574 .inversed = 0, 575 .health = true, 576 }, 577}; 578 579static 580struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 581 .items = mlxplat_mlxcpld_msn21xx_items, 582 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 583 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 584 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 585 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 586 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 587}; 588 589/* Platform hotplug msn274x system family data */ 590static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 591 { 592 .label = "psu1", 593 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 594 .mask = BIT(0), 595 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 596 }, 597 { 598 .label = "psu2", 599 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 600 .mask = BIT(1), 601 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 602 }, 603}; 604 605static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 606 { 607 .label = "pwr1", 608 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 609 .mask = BIT(0), 610 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 611 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 612 }, 613 { 614 .label = "pwr2", 615 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 616 .mask = BIT(1), 617 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 618 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 619 }, 620}; 621 622static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 623 { 624 .label = "fan1", 625 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 626 .mask = BIT(0), 627 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 628 }, 629 { 630 .label = "fan2", 631 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 632 .mask = BIT(1), 633 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 634 }, 635 { 636 .label = "fan3", 637 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 638 .mask = BIT(2), 639 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 640 }, 641 { 642 .label = "fan4", 643 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 644 .mask = BIT(3), 645 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 646 }, 647}; 648 649static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 650 { 651 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 652 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 653 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 654 .mask = MLXPLAT_CPLD_PSU_MASK, 655 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 656 .inversed = 1, 657 .health = false, 658 }, 659 { 660 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 661 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 662 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 663 .mask = MLXPLAT_CPLD_PWR_MASK, 664 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 665 .inversed = 0, 666 .health = false, 667 }, 668 { 669 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 670 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 671 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 672 .mask = MLXPLAT_CPLD_FAN_MASK, 673 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 674 .inversed = 1, 675 .health = false, 676 }, 677 { 678 .data = mlxplat_mlxcpld_default_asic_items_data, 679 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 680 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 681 .mask = MLXPLAT_CPLD_ASIC_MASK, 682 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 683 .inversed = 0, 684 .health = true, 685 }, 686}; 687 688static 689struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 690 .items = mlxplat_mlxcpld_msn274x_items, 691 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 692 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 693 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 694 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 695 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 696}; 697 698/* Platform hotplug MSN201x system family data */ 699static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 700 { 701 .label = "pwr1", 702 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 703 .mask = BIT(0), 704 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 705 }, 706 { 707 .label = "pwr2", 708 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 709 .mask = BIT(1), 710 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 711 }, 712}; 713 714static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 715 { 716 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 717 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 718 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 719 .mask = MLXPLAT_CPLD_PWR_MASK, 720 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 721 .inversed = 0, 722 .health = false, 723 }, 724 { 725 .data = mlxplat_mlxcpld_default_asic_items_data, 726 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 727 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 728 .mask = MLXPLAT_CPLD_ASIC_MASK, 729 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 730 .inversed = 0, 731 .health = true, 732 }, 733}; 734 735static 736struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 737 .items = mlxplat_mlxcpld_msn201x_items, 738 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 739 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 740 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 741 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 742 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 743}; 744 745/* Platform hotplug next generation system family data */ 746static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 747 { 748 .label = "psu1", 749 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 750 .mask = BIT(0), 751 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 752 }, 753 { 754 .label = "psu2", 755 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 756 .mask = BIT(1), 757 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 758 }, 759}; 760 761static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 762 { 763 .label = "fan1", 764 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 765 .mask = BIT(0), 766 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 767 .bit = BIT(0), 768 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 769 }, 770 { 771 .label = "fan2", 772 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 773 .mask = BIT(1), 774 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 775 .bit = BIT(1), 776 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 777 }, 778 { 779 .label = "fan3", 780 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 781 .mask = BIT(2), 782 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 783 .bit = BIT(2), 784 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 785 }, 786 { 787 .label = "fan4", 788 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 789 .mask = BIT(3), 790 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 791 .bit = BIT(3), 792 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 793 }, 794 { 795 .label = "fan5", 796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 797 .mask = BIT(4), 798 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 799 .bit = BIT(4), 800 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 801 }, 802 { 803 .label = "fan6", 804 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 805 .mask = BIT(5), 806 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 807 .bit = BIT(5), 808 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 809 }, 810}; 811 812static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 813 { 814 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 815 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 816 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 817 .mask = MLXPLAT_CPLD_PSU_MASK, 818 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 819 .inversed = 1, 820 .health = false, 821 }, 822 { 823 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 824 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 825 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 826 .mask = MLXPLAT_CPLD_PWR_MASK, 827 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 828 .inversed = 0, 829 .health = false, 830 }, 831 { 832 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 833 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 834 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 835 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 836 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 837 .inversed = 1, 838 .health = false, 839 }, 840 { 841 .data = mlxplat_mlxcpld_default_asic_items_data, 842 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 843 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 844 .mask = MLXPLAT_CPLD_ASIC_MASK, 845 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 846 .inversed = 0, 847 .health = true, 848 }, 849}; 850 851static 852struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 853 .items = mlxplat_mlxcpld_default_ng_items, 854 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 855 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 856 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 857 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 858 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 859}; 860 861/* Platform hotplug extended system family data */ 862static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 863 { 864 .label = "psu1", 865 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 866 .mask = BIT(0), 867 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 868 }, 869 { 870 .label = "psu2", 871 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 872 .mask = BIT(1), 873 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 874 }, 875 { 876 .label = "psu3", 877 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 878 .mask = BIT(2), 879 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 880 }, 881 { 882 .label = "psu4", 883 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 884 .mask = BIT(3), 885 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 886 }, 887}; 888 889static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 890 { 891 .label = "pwr1", 892 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 893 .mask = BIT(0), 894 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 895 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 896 }, 897 { 898 .label = "pwr2", 899 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 900 .mask = BIT(1), 901 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 902 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 903 }, 904 { 905 .label = "pwr3", 906 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 907 .mask = BIT(2), 908 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 909 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 910 }, 911 { 912 .label = "pwr4", 913 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 914 .mask = BIT(3), 915 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 916 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 917 }, 918}; 919 920static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 921 { 922 .data = mlxplat_mlxcpld_ext_psu_items_data, 923 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 924 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 925 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 926 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 927 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 928 .inversed = 1, 929 .health = false, 930 }, 931 { 932 .data = mlxplat_mlxcpld_ext_pwr_items_data, 933 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 934 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 935 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 936 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 937 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 938 .inversed = 0, 939 .health = false, 940 }, 941 { 942 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 943 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 944 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 945 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 946 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 947 .inversed = 1, 948 .health = false, 949 }, 950 { 951 .data = mlxplat_mlxcpld_default_asic_items_data, 952 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 953 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 954 .mask = MLXPLAT_CPLD_ASIC_MASK, 955 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 956 .inversed = 0, 957 .health = true, 958 }, 959}; 960 961static 962struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 963 .items = mlxplat_mlxcpld_ext_items, 964 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 965 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 966 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 967 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 968 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 969}; 970 971/* Platform led default data */ 972static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 973 { 974 .label = "status:green", 975 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 976 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 977 }, 978 { 979 .label = "status:red", 980 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 981 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 982 }, 983 { 984 .label = "psu:green", 985 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 986 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 987 }, 988 { 989 .label = "psu:red", 990 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 991 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 992 }, 993 { 994 .label = "fan1:green", 995 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 996 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 997 }, 998 { 999 .label = "fan1:red", 1000 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1001 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1002 }, 1003 { 1004 .label = "fan2:green", 1005 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1006 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1007 }, 1008 { 1009 .label = "fan2:red", 1010 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1011 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1012 }, 1013 { 1014 .label = "fan3:green", 1015 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1016 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1017 }, 1018 { 1019 .label = "fan3:red", 1020 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1021 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1022 }, 1023 { 1024 .label = "fan4:green", 1025 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1026 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1027 }, 1028 { 1029 .label = "fan4:red", 1030 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1031 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1032 }, 1033}; 1034 1035static struct mlxreg_core_platform_data mlxplat_default_led_data = { 1036 .data = mlxplat_mlxcpld_default_led_data, 1037 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 1038}; 1039 1040/* Platform led MSN21xx system family data */ 1041static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 1042 { 1043 .label = "status:green", 1044 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1045 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1046 }, 1047 { 1048 .label = "status:red", 1049 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1050 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1051 }, 1052 { 1053 .label = "fan:green", 1054 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1055 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1056 }, 1057 { 1058 .label = "fan:red", 1059 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1060 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1061 }, 1062 { 1063 .label = "psu1:green", 1064 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1065 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1066 }, 1067 { 1068 .label = "psu1:red", 1069 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1070 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1071 }, 1072 { 1073 .label = "psu2:green", 1074 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1075 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1076 }, 1077 { 1078 .label = "psu2:red", 1079 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1080 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1081 }, 1082 { 1083 .label = "uid:blue", 1084 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1085 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1086 }, 1087}; 1088 1089static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 1090 .data = mlxplat_mlxcpld_msn21xx_led_data, 1091 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 1092}; 1093 1094/* Platform led for default data for 200GbE systems */ 1095static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 1096 { 1097 .label = "status:green", 1098 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1099 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1100 }, 1101 { 1102 .label = "status:orange", 1103 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1104 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1105 }, 1106 { 1107 .label = "psu:green", 1108 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1109 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1110 }, 1111 { 1112 .label = "psu:orange", 1113 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1114 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1115 }, 1116 { 1117 .label = "fan1:green", 1118 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1119 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1120 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1121 .bit = BIT(0), 1122 }, 1123 { 1124 .label = "fan1:orange", 1125 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1126 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1127 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1128 .bit = BIT(0), 1129 }, 1130 { 1131 .label = "fan2:green", 1132 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1133 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1134 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1135 .bit = BIT(1), 1136 }, 1137 { 1138 .label = "fan2:orange", 1139 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1140 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1141 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1142 .bit = BIT(1), 1143 }, 1144 { 1145 .label = "fan3:green", 1146 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1147 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1148 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1149 .bit = BIT(2), 1150 }, 1151 { 1152 .label = "fan3:orange", 1153 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1154 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1155 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1156 .bit = BIT(2), 1157 }, 1158 { 1159 .label = "fan4:green", 1160 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1161 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1162 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1163 .bit = BIT(3), 1164 }, 1165 { 1166 .label = "fan4:orange", 1167 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1168 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1169 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1170 .bit = BIT(3), 1171 }, 1172 { 1173 .label = "fan5:green", 1174 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1175 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1176 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1177 .bit = BIT(4), 1178 }, 1179 { 1180 .label = "fan5:orange", 1181 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1182 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1183 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1184 .bit = BIT(4), 1185 }, 1186 { 1187 .label = "fan6:green", 1188 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1189 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1190 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1191 .bit = BIT(5), 1192 }, 1193 { 1194 .label = "fan6:orange", 1195 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 1196 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1197 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1198 .bit = BIT(5), 1199 }, 1200 { 1201 .label = "uid:blue", 1202 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1203 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1204 }, 1205}; 1206 1207static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 1208 .data = mlxplat_mlxcpld_default_ng_led_data, 1209 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 1210}; 1211 1212/* Platform led for Comex based 100GbE systems */ 1213static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 1214 { 1215 .label = "status:green", 1216 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1217 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1218 }, 1219 { 1220 .label = "status:red", 1221 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1222 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 1223 }, 1224 { 1225 .label = "psu:green", 1226 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1227 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1228 }, 1229 { 1230 .label = "psu:red", 1231 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 1232 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1233 }, 1234 { 1235 .label = "fan1:green", 1236 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1237 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1238 }, 1239 { 1240 .label = "fan1:red", 1241 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1242 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1243 }, 1244 { 1245 .label = "fan2:green", 1246 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1247 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1248 }, 1249 { 1250 .label = "fan2:red", 1251 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 1252 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1253 }, 1254 { 1255 .label = "fan3:green", 1256 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1257 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1258 }, 1259 { 1260 .label = "fan3:red", 1261 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1262 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1263 }, 1264 { 1265 .label = "fan4:green", 1266 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1267 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1268 }, 1269 { 1270 .label = "fan4:red", 1271 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 1272 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 1273 }, 1274 { 1275 .label = "uid:blue", 1276 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 1277 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 1278 }, 1279}; 1280 1281static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 1282 .data = mlxplat_mlxcpld_comex_100G_led_data, 1283 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 1284}; 1285 1286/* Platform register access default */ 1287static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 1288 { 1289 .label = "cpld1_version", 1290 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1291 .bit = GENMASK(7, 0), 1292 .mode = 0444, 1293 }, 1294 { 1295 .label = "cpld2_version", 1296 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1297 .bit = GENMASK(7, 0), 1298 .mode = 0444, 1299 }, 1300 { 1301 .label = "cpld1_pn", 1302 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1303 .bit = GENMASK(15, 0), 1304 .mode = 0444, 1305 .regnum = 2, 1306 }, 1307 { 1308 .label = "cpld2_pn", 1309 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1310 .bit = GENMASK(15, 0), 1311 .mode = 0444, 1312 .regnum = 2, 1313 }, 1314 { 1315 .label = "cpld1_version_min", 1316 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1317 .bit = GENMASK(7, 0), 1318 .mode = 0444, 1319 }, 1320 { 1321 .label = "cpld2_version_min", 1322 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1323 .bit = GENMASK(7, 0), 1324 .mode = 0444, 1325 }, 1326 { 1327 .label = "reset_long_pb", 1328 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1329 .mask = GENMASK(7, 0) & ~BIT(0), 1330 .mode = 0444, 1331 }, 1332 { 1333 .label = "reset_short_pb", 1334 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1335 .mask = GENMASK(7, 0) & ~BIT(1), 1336 .mode = 0444, 1337 }, 1338 { 1339 .label = "reset_aux_pwr_or_ref", 1340 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1341 .mask = GENMASK(7, 0) & ~BIT(2), 1342 .mode = 0444, 1343 }, 1344 { 1345 .label = "reset_main_pwr_fail", 1346 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1347 .mask = GENMASK(7, 0) & ~BIT(3), 1348 .mode = 0444, 1349 }, 1350 { 1351 .label = "reset_sw_reset", 1352 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1353 .mask = GENMASK(7, 0) & ~BIT(4), 1354 .mode = 0444, 1355 }, 1356 { 1357 .label = "reset_fw_reset", 1358 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1359 .mask = GENMASK(7, 0) & ~BIT(5), 1360 .mode = 0444, 1361 }, 1362 { 1363 .label = "reset_hotswap_or_wd", 1364 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1365 .mask = GENMASK(7, 0) & ~BIT(6), 1366 .mode = 0444, 1367 }, 1368 { 1369 .label = "reset_asic_thermal", 1370 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1371 .mask = GENMASK(7, 0) & ~BIT(7), 1372 .mode = 0444, 1373 }, 1374 { 1375 .label = "psu1_on", 1376 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1377 .mask = GENMASK(7, 0) & ~BIT(0), 1378 .mode = 0200, 1379 }, 1380 { 1381 .label = "psu2_on", 1382 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1383 .mask = GENMASK(7, 0) & ~BIT(1), 1384 .mode = 0200, 1385 }, 1386 { 1387 .label = "pwr_cycle", 1388 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1389 .mask = GENMASK(7, 0) & ~BIT(2), 1390 .mode = 0200, 1391 }, 1392 { 1393 .label = "pwr_down", 1394 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1395 .mask = GENMASK(7, 0) & ~BIT(3), 1396 .mode = 0200, 1397 }, 1398 { 1399 .label = "select_iio", 1400 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1401 .mask = GENMASK(7, 0) & ~BIT(6), 1402 .mode = 0644, 1403 }, 1404 { 1405 .label = "asic_health", 1406 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1407 .mask = MLXPLAT_CPLD_ASIC_MASK, 1408 .bit = 1, 1409 .mode = 0444, 1410 }, 1411}; 1412 1413static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 1414 .data = mlxplat_mlxcpld_default_regs_io_data, 1415 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 1416}; 1417 1418/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 1419static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 1420 { 1421 .label = "cpld1_version", 1422 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1423 .bit = GENMASK(7, 0), 1424 .mode = 0444, 1425 }, 1426 { 1427 .label = "cpld2_version", 1428 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1429 .bit = GENMASK(7, 0), 1430 .mode = 0444, 1431 }, 1432 { 1433 .label = "cpld1_pn", 1434 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1435 .bit = GENMASK(15, 0), 1436 .mode = 0444, 1437 .regnum = 2, 1438 }, 1439 { 1440 .label = "cpld2_pn", 1441 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1442 .bit = GENMASK(15, 0), 1443 .mode = 0444, 1444 .regnum = 2, 1445 }, 1446 { 1447 .label = "cpld1_version_min", 1448 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1449 .bit = GENMASK(7, 0), 1450 .mode = 0444, 1451 }, 1452 { 1453 .label = "cpld2_version_min", 1454 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1455 .bit = GENMASK(7, 0), 1456 .mode = 0444, 1457 }, 1458 { 1459 .label = "reset_long_pb", 1460 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1461 .mask = GENMASK(7, 0) & ~BIT(0), 1462 .mode = 0444, 1463 }, 1464 { 1465 .label = "reset_short_pb", 1466 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1467 .mask = GENMASK(7, 0) & ~BIT(1), 1468 .mode = 0444, 1469 }, 1470 { 1471 .label = "reset_aux_pwr_or_ref", 1472 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1473 .mask = GENMASK(7, 0) & ~BIT(2), 1474 .mode = 0444, 1475 }, 1476 { 1477 .label = "reset_sw_reset", 1478 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1479 .mask = GENMASK(7, 0) & ~BIT(3), 1480 .mode = 0444, 1481 }, 1482 { 1483 .label = "reset_main_pwr_fail", 1484 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1485 .mask = GENMASK(7, 0) & ~BIT(4), 1486 .mode = 0444, 1487 }, 1488 { 1489 .label = "reset_asic_thermal", 1490 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1491 .mask = GENMASK(7, 0) & ~BIT(5), 1492 .mode = 0444, 1493 }, 1494 { 1495 .label = "reset_hotswap_or_halt", 1496 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1497 .mask = GENMASK(7, 0) & ~BIT(6), 1498 .mode = 0444, 1499 }, 1500 { 1501 .label = "reset_sff_wd", 1502 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1503 .mask = GENMASK(7, 0) & ~BIT(6), 1504 .mode = 0444, 1505 }, 1506 { 1507 .label = "psu1_on", 1508 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1509 .mask = GENMASK(7, 0) & ~BIT(0), 1510 .mode = 0200, 1511 }, 1512 { 1513 .label = "psu2_on", 1514 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1515 .mask = GENMASK(7, 0) & ~BIT(1), 1516 .mode = 0200, 1517 }, 1518 { 1519 .label = "pwr_cycle", 1520 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1521 .mask = GENMASK(7, 0) & ~BIT(2), 1522 .mode = 0200, 1523 }, 1524 { 1525 .label = "pwr_down", 1526 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1527 .mask = GENMASK(7, 0) & ~BIT(3), 1528 .mode = 0200, 1529 }, 1530 { 1531 .label = "select_iio", 1532 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1533 .mask = GENMASK(7, 0) & ~BIT(6), 1534 .mode = 0644, 1535 }, 1536 { 1537 .label = "asic_health", 1538 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1539 .mask = MLXPLAT_CPLD_ASIC_MASK, 1540 .bit = 1, 1541 .mode = 0444, 1542 }, 1543}; 1544 1545static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 1546 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 1547 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 1548}; 1549 1550/* Platform register access for next generation systems families data */ 1551static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 1552 { 1553 .label = "cpld1_version", 1554 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 1555 .bit = GENMASK(7, 0), 1556 .mode = 0444, 1557 }, 1558 { 1559 .label = "cpld2_version", 1560 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 1561 .bit = GENMASK(7, 0), 1562 .mode = 0444, 1563 }, 1564 { 1565 .label = "cpld3_version", 1566 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 1567 .bit = GENMASK(7, 0), 1568 .mode = 0444, 1569 }, 1570 { 1571 .label = "cpld4_version", 1572 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 1573 .bit = GENMASK(7, 0), 1574 .mode = 0444, 1575 }, 1576 { 1577 .label = "cpld1_pn", 1578 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 1579 .bit = GENMASK(15, 0), 1580 .mode = 0444, 1581 .regnum = 2, 1582 }, 1583 { 1584 .label = "cpld2_pn", 1585 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 1586 .bit = GENMASK(15, 0), 1587 .mode = 0444, 1588 .regnum = 2, 1589 }, 1590 { 1591 .label = "cpld3_pn", 1592 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 1593 .bit = GENMASK(15, 0), 1594 .mode = 0444, 1595 .regnum = 2, 1596 }, 1597 { 1598 .label = "cpld4_pn", 1599 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 1600 .bit = GENMASK(15, 0), 1601 .mode = 0444, 1602 .regnum = 2, 1603 }, 1604 { 1605 .label = "cpld1_version_min", 1606 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 1607 .bit = GENMASK(7, 0), 1608 .mode = 0444, 1609 }, 1610 { 1611 .label = "cpld2_version_min", 1612 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 1613 .bit = GENMASK(7, 0), 1614 .mode = 0444, 1615 }, 1616 { 1617 .label = "cpld3_version_min", 1618 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 1619 .bit = GENMASK(7, 0), 1620 .mode = 0444, 1621 }, 1622 { 1623 .label = "cpld4_version_min", 1624 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 1625 .bit = GENMASK(7, 0), 1626 .mode = 0444, 1627 }, 1628 { 1629 .label = "reset_long_pb", 1630 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1631 .mask = GENMASK(7, 0) & ~BIT(0), 1632 .mode = 0444, 1633 }, 1634 { 1635 .label = "reset_short_pb", 1636 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1637 .mask = GENMASK(7, 0) & ~BIT(1), 1638 .mode = 0444, 1639 }, 1640 { 1641 .label = "reset_aux_pwr_or_ref", 1642 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1643 .mask = GENMASK(7, 0) & ~BIT(2), 1644 .mode = 0444, 1645 }, 1646 { 1647 .label = "reset_from_comex", 1648 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1649 .mask = GENMASK(7, 0) & ~BIT(4), 1650 .mode = 0444, 1651 }, 1652 { 1653 .label = "reset_from_asic", 1654 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1655 .mask = GENMASK(7, 0) & ~BIT(5), 1656 .mode = 0444, 1657 }, 1658 { 1659 .label = "reset_swb_wd", 1660 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1661 .mask = GENMASK(7, 0) & ~BIT(6), 1662 .mode = 0444, 1663 }, 1664 { 1665 .label = "reset_asic_thermal", 1666 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1667 .mask = GENMASK(7, 0) & ~BIT(7), 1668 .mode = 0444, 1669 }, 1670 { 1671 .label = "reset_comex_pwr_fail", 1672 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1673 .mask = GENMASK(7, 0) & ~BIT(3), 1674 .mode = 0444, 1675 }, 1676 { 1677 .label = "reset_platform", 1678 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1679 .mask = GENMASK(7, 0) & ~BIT(4), 1680 .mode = 0444, 1681 }, 1682 { 1683 .label = "reset_soc", 1684 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1685 .mask = GENMASK(7, 0) & ~BIT(5), 1686 .mode = 0444, 1687 }, 1688 { 1689 .label = "reset_comex_wd", 1690 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 1691 .mask = GENMASK(7, 0) & ~BIT(6), 1692 .mode = 0444, 1693 }, 1694 { 1695 .label = "reset_voltmon_upgrade_fail", 1696 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1697 .mask = GENMASK(7, 0) & ~BIT(0), 1698 .mode = 0444, 1699 }, 1700 { 1701 .label = "reset_system", 1702 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1703 .mask = GENMASK(7, 0) & ~BIT(1), 1704 .mode = 0444, 1705 }, 1706 { 1707 .label = "reset_sw_pwr_off", 1708 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1709 .mask = GENMASK(7, 0) & ~BIT(2), 1710 .mode = 0444, 1711 }, 1712 { 1713 .label = "reset_comex_thermal", 1714 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1715 .mask = GENMASK(7, 0) & ~BIT(3), 1716 .mode = 0444, 1717 }, 1718 { 1719 .label = "reset_reload_bios", 1720 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1721 .mask = GENMASK(7, 0) & ~BIT(5), 1722 .mode = 0444, 1723 }, 1724 { 1725 .label = "reset_ac_pwr_fail", 1726 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 1727 .mask = GENMASK(7, 0) & ~BIT(6), 1728 .mode = 0444, 1729 }, 1730 { 1731 .label = "psu1_on", 1732 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1733 .mask = GENMASK(7, 0) & ~BIT(0), 1734 .mode = 0200, 1735 }, 1736 { 1737 .label = "psu2_on", 1738 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1739 .mask = GENMASK(7, 0) & ~BIT(1), 1740 .mode = 0200, 1741 }, 1742 { 1743 .label = "pwr_cycle", 1744 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1745 .mask = GENMASK(7, 0) & ~BIT(2), 1746 .mode = 0200, 1747 }, 1748 { 1749 .label = "pwr_down", 1750 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 1751 .mask = GENMASK(7, 0) & ~BIT(3), 1752 .mode = 0200, 1753 }, 1754 { 1755 .label = "jtag_enable", 1756 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 1757 .mask = GENMASK(7, 0) & ~BIT(4), 1758 .mode = 0644, 1759 }, 1760 { 1761 .label = "asic_health", 1762 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1763 .mask = MLXPLAT_CPLD_ASIC_MASK, 1764 .bit = 1, 1765 .mode = 0444, 1766 }, 1767 { 1768 .label = "fan_dir", 1769 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 1770 .bit = GENMASK(7, 0), 1771 .mode = 0444, 1772 }, 1773 { 1774 .label = "voltreg_update_status", 1775 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 1776 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 1777 .bit = 5, 1778 .mode = 0444, 1779 }, 1780 { 1781 .label = "vpd_wp", 1782 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1783 .mask = GENMASK(7, 0) & ~BIT(3), 1784 .mode = 0644, 1785 }, 1786 { 1787 .label = "pcie_asic_reset_dis", 1788 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 1789 .mask = GENMASK(7, 0) & ~BIT(4), 1790 .mode = 0644, 1791 }, 1792 { 1793 .label = "config1", 1794 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 1795 .bit = GENMASK(7, 0), 1796 .mode = 0444, 1797 }, 1798 { 1799 .label = "config2", 1800 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 1801 .bit = GENMASK(7, 0), 1802 .mode = 0444, 1803 }, 1804 { 1805 .label = "ufm_version", 1806 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 1807 .bit = GENMASK(7, 0), 1808 .mode = 0444, 1809 }, 1810}; 1811 1812static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 1813 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 1814 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 1815}; 1816 1817/* Platform FAN default */ 1818static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 1819 { 1820 .label = "pwm1", 1821 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 1822 }, 1823 { 1824 .label = "tacho1", 1825 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 1826 .mask = GENMASK(7, 0), 1827 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1828 .bit = BIT(0), 1829 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1830 1831 }, 1832 { 1833 .label = "tacho2", 1834 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 1835 .mask = GENMASK(7, 0), 1836 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1837 .bit = BIT(1), 1838 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1839 }, 1840 { 1841 .label = "tacho3", 1842 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 1843 .mask = GENMASK(7, 0), 1844 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1845 .bit = BIT(2), 1846 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1847 }, 1848 { 1849 .label = "tacho4", 1850 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 1851 .mask = GENMASK(7, 0), 1852 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1853 .bit = BIT(3), 1854 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1855 }, 1856 { 1857 .label = "tacho5", 1858 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 1859 .mask = GENMASK(7, 0), 1860 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1861 .bit = BIT(4), 1862 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1863 }, 1864 { 1865 .label = "tacho6", 1866 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 1867 .mask = GENMASK(7, 0), 1868 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1869 .bit = BIT(5), 1870 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1871 }, 1872 { 1873 .label = "tacho7", 1874 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 1875 .mask = GENMASK(7, 0), 1876 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1877 .bit = BIT(6), 1878 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1879 }, 1880 { 1881 .label = "tacho8", 1882 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 1883 .mask = GENMASK(7, 0), 1884 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 1885 .bit = BIT(7), 1886 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1887 }, 1888 { 1889 .label = "tacho9", 1890 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 1891 .mask = GENMASK(7, 0), 1892 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1893 .bit = BIT(0), 1894 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1895 }, 1896 { 1897 .label = "tacho10", 1898 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 1899 .mask = GENMASK(7, 0), 1900 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1901 .bit = BIT(1), 1902 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1903 }, 1904 { 1905 .label = "tacho11", 1906 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 1907 .mask = GENMASK(7, 0), 1908 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1909 .bit = BIT(2), 1910 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1911 }, 1912 { 1913 .label = "tacho12", 1914 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 1915 .mask = GENMASK(7, 0), 1916 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 1917 .bit = BIT(3), 1918 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1919 }, 1920 { 1921 .label = "conf", 1922 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 1923 }, 1924}; 1925 1926static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 1927 .data = mlxplat_mlxcpld_default_fan_data, 1928 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 1929 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1930}; 1931 1932/* Watchdog type1: hardware implementation version1 1933 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 1934 */ 1935static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 1936 { 1937 .label = "action", 1938 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 1939 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 1940 .bit = 0, 1941 }, 1942 { 1943 .label = "timeout", 1944 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 1945 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1946 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1947 }, 1948 { 1949 .label = "ping", 1950 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1951 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1952 .bit = 0, 1953 }, 1954 { 1955 .label = "reset", 1956 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1957 .mask = GENMASK(7, 0) & ~BIT(6), 1958 .bit = 6, 1959 }, 1960}; 1961 1962static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 1963 { 1964 .label = "action", 1965 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 1966 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 1967 .bit = 4, 1968 }, 1969 { 1970 .label = "timeout", 1971 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 1972 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 1973 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 1974 }, 1975 { 1976 .label = "ping", 1977 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 1978 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 1979 .bit = 1, 1980 }, 1981}; 1982 1983static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 1984 { 1985 .data = mlxplat_mlxcpld_wd_main_regs_type1, 1986 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 1987 .version = MLX_WDT_TYPE1, 1988 .identity = "mlx-wdt-main", 1989 }, 1990 { 1991 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 1992 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 1993 .version = MLX_WDT_TYPE1, 1994 .identity = "mlx-wdt-aux", 1995 }, 1996}; 1997 1998/* Watchdog type2: hardware implementation version 2 1999 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 2000 */ 2001static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 2002 { 2003 .label = "action", 2004 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2005 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2006 .bit = 0, 2007 }, 2008 { 2009 .label = "timeout", 2010 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2011 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2012 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2013 }, 2014 { 2015 .label = "timeleft", 2016 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 2017 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2018 }, 2019 { 2020 .label = "ping", 2021 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2022 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2023 .bit = 0, 2024 }, 2025 { 2026 .label = "reset", 2027 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2028 .mask = GENMASK(7, 0) & ~BIT(6), 2029 .bit = 6, 2030 }, 2031}; 2032 2033static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 2034 { 2035 .label = "action", 2036 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2037 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2038 .bit = 4, 2039 }, 2040 { 2041 .label = "timeout", 2042 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2043 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2044 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 2045 }, 2046 { 2047 .label = "timeleft", 2048 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 2049 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2050 }, 2051 { 2052 .label = "ping", 2053 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2054 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2055 .bit = 4, 2056 }, 2057}; 2058 2059static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 2060 { 2061 .data = mlxplat_mlxcpld_wd_main_regs_type2, 2062 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 2063 .version = MLX_WDT_TYPE2, 2064 .identity = "mlx-wdt-main", 2065 }, 2066 { 2067 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 2068 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 2069 .version = MLX_WDT_TYPE2, 2070 .identity = "mlx-wdt-aux", 2071 }, 2072}; 2073 2074/* Watchdog type3: hardware implementation version 3 2075 * Can be on all systems. It's differentiated by WD capability bit. 2076 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 2077 * still have only one main watchdog. 2078 */ 2079static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 2080 { 2081 .label = "action", 2082 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2083 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2084 .bit = 0, 2085 }, 2086 { 2087 .label = "timeout", 2088 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2089 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2090 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 2091 }, 2092 { 2093 .label = "timeleft", 2094 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 2095 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2096 }, 2097 { 2098 .label = "ping", 2099 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 2100 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 2101 .bit = 0, 2102 }, 2103 { 2104 .label = "reset", 2105 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2106 .mask = GENMASK(7, 0) & ~BIT(6), 2107 .bit = 6, 2108 }, 2109}; 2110 2111static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 2112 { 2113 .label = "action", 2114 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2115 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2116 .bit = 4, 2117 }, 2118 { 2119 .label = "timeout", 2120 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2121 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2122 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 2123 }, 2124 { 2125 .label = "timeleft", 2126 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 2127 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 2128 }, 2129 { 2130 .label = "ping", 2131 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 2132 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 2133 .bit = 4, 2134 }, 2135}; 2136 2137static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 2138 { 2139 .data = mlxplat_mlxcpld_wd_main_regs_type3, 2140 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 2141 .version = MLX_WDT_TYPE3, 2142 .identity = "mlx-wdt-main", 2143 }, 2144 { 2145 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 2146 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 2147 .version = MLX_WDT_TYPE3, 2148 .identity = "mlx-wdt-aux", 2149 }, 2150}; 2151 2152static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 2153{ 2154 switch (reg) { 2155 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2156 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2157 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2158 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2159 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2160 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2161 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2162 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2163 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2164 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2165 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2166 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2167 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2168 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2169 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2170 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2171 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2172 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2173 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2174 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2175 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2176 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2177 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2178 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2179 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2180 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2181 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2182 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2183 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2184 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2185 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2186 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2187 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2188 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2189 return true; 2190 } 2191 return false; 2192} 2193 2194static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 2195{ 2196 switch (reg) { 2197 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2198 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2199 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2200 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2201 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2202 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2203 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2204 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2205 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2206 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2207 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2208 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2209 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2210 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2211 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2212 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2213 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2214 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2215 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2216 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2217 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 2218 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2219 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 2220 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2221 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2222 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2223 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2224 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2225 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2226 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2227 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2228 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2229 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2230 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2231 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2232 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2233 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2234 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2235 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2236 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2237 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2238 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2239 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2240 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 2241 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 2242 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 2243 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 2244 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2245 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2246 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 2247 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2248 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2249 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 2250 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2251 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2252 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2253 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2254 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2255 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2256 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2257 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2258 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2259 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2260 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2261 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2262 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2263 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2264 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2265 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2266 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2267 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2268 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2269 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2270 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2271 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2272 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2273 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2274 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2275 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2276 return true; 2277 } 2278 return false; 2279} 2280 2281static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 2282{ 2283 switch (reg) { 2284 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 2285 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 2286 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 2287 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 2288 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 2289 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 2290 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 2291 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 2292 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 2293 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 2294 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 2295 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 2296 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 2297 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 2298 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 2299 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 2300 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 2301 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 2302 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 2303 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 2304 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 2305 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 2306 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 2307 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 2308 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 2309 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 2310 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 2311 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 2312 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 2313 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 2314 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 2315 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 2316 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 2317 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 2318 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 2319 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 2320 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 2321 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 2322 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 2323 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 2324 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 2325 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 2326 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 2327 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 2328 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 2329 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 2330 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 2331 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 2332 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 2333 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 2334 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 2335 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 2336 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 2337 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 2338 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 2339 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 2340 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 2341 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 2342 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 2343 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 2344 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 2345 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 2346 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 2347 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 2348 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 2349 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 2350 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 2351 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 2352 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 2353 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 2354 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 2355 return true; 2356 } 2357 return false; 2358} 2359 2360static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 2361 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 2362 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 2363 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2364 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2365}; 2366 2367static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 2368 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2369 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 2370}; 2371 2372static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 2373 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 2374 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 2375 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2376}; 2377 2378static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 2379 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 2380 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 2381 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 2382 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 2383}; 2384 2385struct mlxplat_mlxcpld_regmap_context { 2386 void __iomem *base; 2387}; 2388 2389static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 2390 2391static int 2392mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 2393{ 2394 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2395 2396 *val = ioread8(ctx->base + reg); 2397 return 0; 2398} 2399 2400static int 2401mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 2402{ 2403 struct mlxplat_mlxcpld_regmap_context *ctx = context; 2404 2405 iowrite8(val, ctx->base + reg); 2406 return 0; 2407} 2408 2409static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 2410 .reg_bits = 8, 2411 .val_bits = 8, 2412 .max_register = 255, 2413 .cache_type = REGCACHE_FLAT, 2414 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2415 .readable_reg = mlxplat_mlxcpld_readable_reg, 2416 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2417 .reg_defaults = mlxplat_mlxcpld_regmap_default, 2418 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 2419 .reg_read = mlxplat_mlxcpld_reg_read, 2420 .reg_write = mlxplat_mlxcpld_reg_write, 2421}; 2422 2423static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 2424 .reg_bits = 8, 2425 .val_bits = 8, 2426 .max_register = 255, 2427 .cache_type = REGCACHE_FLAT, 2428 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2429 .readable_reg = mlxplat_mlxcpld_readable_reg, 2430 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2431 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 2432 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 2433 .reg_read = mlxplat_mlxcpld_reg_read, 2434 .reg_write = mlxplat_mlxcpld_reg_write, 2435}; 2436 2437static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 2438 .reg_bits = 8, 2439 .val_bits = 8, 2440 .max_register = 255, 2441 .cache_type = REGCACHE_FLAT, 2442 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2443 .readable_reg = mlxplat_mlxcpld_readable_reg, 2444 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2445 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 2446 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 2447 .reg_read = mlxplat_mlxcpld_reg_read, 2448 .reg_write = mlxplat_mlxcpld_reg_write, 2449}; 2450 2451static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 2452 .reg_bits = 8, 2453 .val_bits = 8, 2454 .max_register = 255, 2455 .cache_type = REGCACHE_FLAT, 2456 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 2457 .readable_reg = mlxplat_mlxcpld_readable_reg, 2458 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 2459 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 2460 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 2461 .reg_read = mlxplat_mlxcpld_reg_read, 2462 .reg_write = mlxplat_mlxcpld_reg_write, 2463}; 2464 2465static struct resource mlxplat_mlxcpld_resources[] = { 2466 [0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"), 2467}; 2468 2469static struct platform_device *mlxplat_dev; 2470static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 2471static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 2472static struct mlxreg_core_platform_data *mlxplat_led; 2473static struct mlxreg_core_platform_data *mlxplat_regs_io; 2474static struct mlxreg_core_platform_data *mlxplat_fan; 2475static struct mlxreg_core_platform_data 2476 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 2477static const struct regmap_config *mlxplat_regmap_config; 2478 2479static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 2480{ 2481 int i; 2482 2483 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2484 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2485 mlxplat_mux_data = mlxplat_default_mux_data; 2486 for (i = 0; i < mlxplat_mux_num; i++) { 2487 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 2488 mlxplat_mux_data[i].n_values = 2489 ARRAY_SIZE(mlxplat_default_channels[i]); 2490 } 2491 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 2492 mlxplat_hotplug->deferred_nr = 2493 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2494 mlxplat_led = &mlxplat_default_led_data; 2495 mlxplat_regs_io = &mlxplat_default_regs_io_data; 2496 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2497 2498 return 1; 2499} 2500 2501static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 2502{ 2503 int i; 2504 2505 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2506 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2507 mlxplat_mux_data = mlxplat_default_mux_data; 2508 for (i = 0; i < mlxplat_mux_num; i++) { 2509 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2510 mlxplat_mux_data[i].n_values = 2511 ARRAY_SIZE(mlxplat_msn21xx_channels); 2512 } 2513 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 2514 mlxplat_hotplug->deferred_nr = 2515 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2516 mlxplat_led = &mlxplat_msn21xx_led_data; 2517 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2518 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2519 2520 return 1; 2521} 2522 2523static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 2524{ 2525 int i; 2526 2527 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2528 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2529 mlxplat_mux_data = mlxplat_default_mux_data; 2530 for (i = 0; i < mlxplat_mux_num; i++) { 2531 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2532 mlxplat_mux_data[i].n_values = 2533 ARRAY_SIZE(mlxplat_msn21xx_channels); 2534 } 2535 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 2536 mlxplat_hotplug->deferred_nr = 2537 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2538 mlxplat_led = &mlxplat_default_led_data; 2539 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2540 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2541 2542 return 1; 2543} 2544 2545static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 2546{ 2547 int i; 2548 2549 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2550 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2551 mlxplat_mux_data = mlxplat_default_mux_data; 2552 for (i = 0; i < mlxplat_mux_num; i++) { 2553 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2554 mlxplat_mux_data[i].n_values = 2555 ARRAY_SIZE(mlxplat_msn21xx_channels); 2556 } 2557 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 2558 mlxplat_hotplug->deferred_nr = 2559 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2560 mlxplat_led = &mlxplat_msn21xx_led_data; 2561 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 2562 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 2563 2564 return 1; 2565} 2566 2567static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 2568{ 2569 int i; 2570 2571 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2572 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2573 mlxplat_mux_data = mlxplat_default_mux_data; 2574 for (i = 0; i < mlxplat_mux_num; i++) { 2575 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2576 mlxplat_mux_data[i].n_values = 2577 ARRAY_SIZE(mlxplat_msn21xx_channels); 2578 } 2579 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 2580 mlxplat_hotplug->deferred_nr = 2581 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2582 mlxplat_led = &mlxplat_default_ng_led_data; 2583 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2584 mlxplat_fan = &mlxplat_default_fan_data; 2585 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2586 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2587 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2588 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 2589 2590 return 1; 2591} 2592 2593static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 2594{ 2595 int i; 2596 2597 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2598 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 2599 mlxplat_mux_data = mlxplat_extended_mux_data; 2600 for (i = 0; i < mlxplat_mux_num; i++) { 2601 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2602 mlxplat_mux_data[i].n_values = 2603 ARRAY_SIZE(mlxplat_msn21xx_channels); 2604 } 2605 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 2606 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 2607 mlxplat_led = &mlxplat_comex_100G_led_data; 2608 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2609 mlxplat_fan = &mlxplat_default_fan_data; 2610 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2611 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2612 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 2613 2614 return 1; 2615} 2616 2617static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 2618{ 2619 int i; 2620 2621 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 2622 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 2623 mlxplat_mux_data = mlxplat_default_mux_data; 2624 for (i = 0; i < mlxplat_mux_num; i++) { 2625 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 2626 mlxplat_mux_data[i].n_values = 2627 ARRAY_SIZE(mlxplat_msn21xx_channels); 2628 } 2629 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 2630 mlxplat_hotplug->deferred_nr = 2631 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 2632 mlxplat_led = &mlxplat_default_ng_led_data; 2633 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 2634 mlxplat_fan = &mlxplat_default_fan_data; 2635 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 2636 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 2637 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 2638 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 2639 2640 return 1; 2641} 2642 2643static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 2644 { 2645 .callback = mlxplat_dmi_default_matched, 2646 .matches = { 2647 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 2648 }, 2649 }, 2650 { 2651 .callback = mlxplat_dmi_msn21xx_matched, 2652 .matches = { 2653 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 2654 }, 2655 }, 2656 { 2657 .callback = mlxplat_dmi_msn274x_matched, 2658 .matches = { 2659 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 2660 }, 2661 }, 2662 { 2663 .callback = mlxplat_dmi_msn201x_matched, 2664 .matches = { 2665 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 2666 }, 2667 }, 2668 { 2669 .callback = mlxplat_dmi_qmb7xx_matched, 2670 .matches = { 2671 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 2672 }, 2673 }, 2674 { 2675 .callback = mlxplat_dmi_qmb7xx_matched, 2676 .matches = { 2677 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 2678 }, 2679 }, 2680 { 2681 .callback = mlxplat_dmi_comex_matched, 2682 .matches = { 2683 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 2684 }, 2685 }, 2686 { 2687 .callback = mlxplat_dmi_ng400_matched, 2688 .matches = { 2689 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 2690 }, 2691 }, 2692 { 2693 .callback = mlxplat_dmi_msn274x_matched, 2694 .matches = { 2695 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2696 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 2697 }, 2698 }, 2699 { 2700 .callback = mlxplat_dmi_default_matched, 2701 .matches = { 2702 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2703 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 2704 }, 2705 }, 2706 { 2707 .callback = mlxplat_dmi_default_matched, 2708 .matches = { 2709 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2710 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 2711 }, 2712 }, 2713 { 2714 .callback = mlxplat_dmi_default_matched, 2715 .matches = { 2716 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2717 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 2718 }, 2719 }, 2720 { 2721 .callback = mlxplat_dmi_default_matched, 2722 .matches = { 2723 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2724 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 2725 }, 2726 }, 2727 { 2728 .callback = mlxplat_dmi_msn21xx_matched, 2729 .matches = { 2730 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2731 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 2732 }, 2733 }, 2734 { 2735 .callback = mlxplat_dmi_msn201x_matched, 2736 .matches = { 2737 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2738 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 2739 }, 2740 }, 2741 { 2742 .callback = mlxplat_dmi_qmb7xx_matched, 2743 .matches = { 2744 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2745 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 2746 }, 2747 }, 2748 { 2749 .callback = mlxplat_dmi_qmb7xx_matched, 2750 .matches = { 2751 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2752 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 2753 }, 2754 }, 2755 { 2756 .callback = mlxplat_dmi_qmb7xx_matched, 2757 .matches = { 2758 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2759 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 2760 }, 2761 }, 2762 { 2763 .callback = mlxplat_dmi_qmb7xx_matched, 2764 .matches = { 2765 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 2766 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 2767 }, 2768 }, 2769 { } 2770}; 2771 2772MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 2773 2774static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 2775{ 2776 struct i2c_adapter *search_adap; 2777 int shift, i; 2778 2779 /* Scan adapters from expected id to verify it is free. */ 2780 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 2781 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 2782 mlxplat_max_adap_num; i++) { 2783 search_adap = i2c_get_adapter(i); 2784 if (search_adap) { 2785 i2c_put_adapter(search_adap); 2786 continue; 2787 } 2788 2789 /* Return if expected parent adapter is free. */ 2790 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 2791 return 0; 2792 break; 2793 } 2794 2795 /* Return with error if free id for adapter is not found. */ 2796 if (i == mlxplat_max_adap_num) 2797 return -ENODEV; 2798 2799 /* Shift adapter ids, since expected parent adapter is not free. */ 2800 *nr = i; 2801 for (i = 0; i < mlxplat_mux_num; i++) { 2802 shift = *nr - mlxplat_mux_data[i].parent; 2803 mlxplat_mux_data[i].parent = *nr; 2804 mlxplat_mux_data[i].base_nr += shift; 2805 if (shift > 0) 2806 mlxplat_hotplug->shift_nr = shift; 2807 } 2808 2809 return 0; 2810} 2811 2812static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 2813{ 2814 u32 regval; 2815 int i, rc; 2816 2817 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2818 ®val); 2819 if (rc) 2820 return rc; 2821 2822 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 2823 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 2824 if (mlxplat_wd_data[i]) 2825 mlxplat_wd_data[i] = 2826 &mlxplat_mlxcpld_wd_set_type3[i]; 2827 } 2828 } 2829 2830 return 0; 2831} 2832 2833static int __init mlxplat_init(void) 2834{ 2835 struct mlxplat_priv *priv; 2836 int i, j, nr, err; 2837 2838 if (!dmi_check_system(mlxplat_dmi_table)) 2839 return -ENODEV; 2840 2841 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 2842 mlxplat_lpc_resources, 2843 ARRAY_SIZE(mlxplat_lpc_resources)); 2844 2845 if (IS_ERR(mlxplat_dev)) 2846 return PTR_ERR(mlxplat_dev); 2847 2848 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 2849 GFP_KERNEL); 2850 if (!priv) { 2851 err = -ENOMEM; 2852 goto fail_alloc; 2853 } 2854 platform_set_drvdata(mlxplat_dev, priv); 2855 2856 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 2857 mlxplat_lpc_resources[1].start, 1); 2858 if (!mlxplat_mlxcpld_regmap_ctx.base) { 2859 err = -ENOMEM; 2860 goto fail_alloc; 2861 } 2862 2863 if (!mlxplat_regmap_config) 2864 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 2865 2866 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 2867 &mlxplat_mlxcpld_regmap_ctx, 2868 mlxplat_regmap_config); 2869 if (IS_ERR(priv->regmap)) { 2870 err = PTR_ERR(priv->regmap); 2871 goto fail_alloc; 2872 } 2873 2874 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 2875 if (nr < 0) 2876 goto fail_alloc; 2877 2878 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 2879 if (mlxplat_i2c) 2880 mlxplat_i2c->regmap = priv->regmap; 2881 priv->pdev_i2c = platform_device_register_resndata( 2882 &mlxplat_dev->dev, "i2c_mlxcpld", 2883 nr, mlxplat_mlxcpld_resources, 2884 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2885 mlxplat_i2c, sizeof(*mlxplat_i2c)); 2886 if (IS_ERR(priv->pdev_i2c)) { 2887 err = PTR_ERR(priv->pdev_i2c); 2888 goto fail_alloc; 2889 } 2890 2891 for (i = 0; i < mlxplat_mux_num; i++) { 2892 priv->pdev_mux[i] = platform_device_register_resndata( 2893 &priv->pdev_i2c->dev, 2894 "i2c-mux-reg", i, NULL, 2895 0, &mlxplat_mux_data[i], 2896 sizeof(mlxplat_mux_data[i])); 2897 if (IS_ERR(priv->pdev_mux[i])) { 2898 err = PTR_ERR(priv->pdev_mux[i]); 2899 goto fail_platform_mux_register; 2900 } 2901 } 2902 2903 /* Add hotplug driver */ 2904 mlxplat_hotplug->regmap = priv->regmap; 2905 priv->pdev_hotplug = platform_device_register_resndata( 2906 &mlxplat_dev->dev, "mlxreg-hotplug", 2907 PLATFORM_DEVID_NONE, 2908 mlxplat_mlxcpld_resources, 2909 ARRAY_SIZE(mlxplat_mlxcpld_resources), 2910 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 2911 if (IS_ERR(priv->pdev_hotplug)) { 2912 err = PTR_ERR(priv->pdev_hotplug); 2913 goto fail_platform_mux_register; 2914 } 2915 2916 /* Set default registers. */ 2917 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { 2918 err = regmap_write(priv->regmap, 2919 mlxplat_regmap_config->reg_defaults[j].reg, 2920 mlxplat_regmap_config->reg_defaults[j].def); 2921 if (err) 2922 goto fail_platform_mux_register; 2923 } 2924 2925 /* Add LED driver. */ 2926 mlxplat_led->regmap = priv->regmap; 2927 priv->pdev_led = platform_device_register_resndata( 2928 &mlxplat_dev->dev, "leds-mlxreg", 2929 PLATFORM_DEVID_NONE, NULL, 0, 2930 mlxplat_led, sizeof(*mlxplat_led)); 2931 if (IS_ERR(priv->pdev_led)) { 2932 err = PTR_ERR(priv->pdev_led); 2933 goto fail_platform_hotplug_register; 2934 } 2935 2936 /* Add registers io access driver. */ 2937 if (mlxplat_regs_io) { 2938 mlxplat_regs_io->regmap = priv->regmap; 2939 priv->pdev_io_regs = platform_device_register_resndata( 2940 &mlxplat_dev->dev, "mlxreg-io", 2941 PLATFORM_DEVID_NONE, NULL, 0, 2942 mlxplat_regs_io, 2943 sizeof(*mlxplat_regs_io)); 2944 if (IS_ERR(priv->pdev_io_regs)) { 2945 err = PTR_ERR(priv->pdev_io_regs); 2946 goto fail_platform_led_register; 2947 } 2948 } 2949 2950 /* Add FAN driver. */ 2951 if (mlxplat_fan) { 2952 mlxplat_fan->regmap = priv->regmap; 2953 priv->pdev_fan = platform_device_register_resndata( 2954 &mlxplat_dev->dev, "mlxreg-fan", 2955 PLATFORM_DEVID_NONE, NULL, 0, 2956 mlxplat_fan, 2957 sizeof(*mlxplat_fan)); 2958 if (IS_ERR(priv->pdev_fan)) { 2959 err = PTR_ERR(priv->pdev_fan); 2960 goto fail_platform_io_regs_register; 2961 } 2962 } 2963 2964 /* Add WD drivers. */ 2965 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 2966 if (err) 2967 goto fail_platform_wd_register; 2968 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { 2969 if (mlxplat_wd_data[j]) { 2970 mlxplat_wd_data[j]->regmap = priv->regmap; 2971 priv->pdev_wd[j] = platform_device_register_resndata( 2972 &mlxplat_dev->dev, "mlx-wdt", 2973 j, NULL, 0, 2974 mlxplat_wd_data[j], 2975 sizeof(*mlxplat_wd_data[j])); 2976 if (IS_ERR(priv->pdev_wd[j])) { 2977 err = PTR_ERR(priv->pdev_wd[j]); 2978 goto fail_platform_wd_register; 2979 } 2980 } 2981 } 2982 2983 /* Sync registers with hardware. */ 2984 regcache_mark_dirty(priv->regmap); 2985 err = regcache_sync(priv->regmap); 2986 if (err) 2987 goto fail_platform_wd_register; 2988 2989 return 0; 2990 2991fail_platform_wd_register: 2992 while (--j >= 0) 2993 platform_device_unregister(priv->pdev_wd[j]); 2994 if (mlxplat_fan) 2995 platform_device_unregister(priv->pdev_fan); 2996fail_platform_io_regs_register: 2997 if (mlxplat_regs_io) 2998 platform_device_unregister(priv->pdev_io_regs); 2999fail_platform_led_register: 3000 platform_device_unregister(priv->pdev_led); 3001fail_platform_hotplug_register: 3002 platform_device_unregister(priv->pdev_hotplug); 3003fail_platform_mux_register: 3004 while (--i >= 0) 3005 platform_device_unregister(priv->pdev_mux[i]); 3006 platform_device_unregister(priv->pdev_i2c); 3007fail_alloc: 3008 platform_device_unregister(mlxplat_dev); 3009 3010 return err; 3011} 3012module_init(mlxplat_init); 3013 3014static void __exit mlxplat_exit(void) 3015{ 3016 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 3017 int i; 3018 3019 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 3020 platform_device_unregister(priv->pdev_wd[i]); 3021 if (priv->pdev_fan) 3022 platform_device_unregister(priv->pdev_fan); 3023 if (priv->pdev_io_regs) 3024 platform_device_unregister(priv->pdev_io_regs); 3025 platform_device_unregister(priv->pdev_led); 3026 platform_device_unregister(priv->pdev_hotplug); 3027 3028 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) 3029 platform_device_unregister(priv->pdev_mux[i]); 3030 3031 platform_device_unregister(priv->pdev_i2c); 3032 platform_device_unregister(mlxplat_dev); 3033} 3034module_exit(mlxplat_exit); 3035 3036MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 3037MODULE_DESCRIPTION("Mellanox platform driver"); 3038MODULE_LICENSE("Dual BSD/GPL"); 3039