1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 Sanechips Technology Co., Ltd. 4 * Copyright 2017 Linaro Ltd. 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/of_address.h> 10#include <linux/of_device.h> 11#include <linux/pinctrl/pinctrl.h> 12#include <linux/platform_device.h> 13 14#include "pinctrl-zx.h" 15 16#define TOP_REG0 0x00 17#define TOP_REG1 0x04 18#define TOP_REG2 0x08 19#define TOP_REG3 0x0c 20#define TOP_REG4 0x10 21#define TOP_REG5 0x14 22#define TOP_REG6 0x18 23#define TOP_REG7 0x1c 24#define TOP_REG8 0x20 25 26/* 27 * The pin numbering starts from AON pins with reserved ones included, 28 * so that register data like offset and bit position for AON pins can 29 * be calculated from pin number. 30 */ 31enum zx296718_pin { 32 /* aon_pmm_reg_0 */ 33 I2C3_SCL = 0, 34 I2C3_SDA = 1, 35 AON_RESERVED0 = 2, 36 AON_RESERVED1 = 3, 37 SEC_EN = 4, 38 UART0_RXD = 5, 39 UART0_TXD = 6, 40 IR_IN = 7, 41 SPI0_CLK = 8, 42 SPI0_CS = 9, 43 SPI0_TXD = 10, 44 SPI0_RXD = 11, 45 KEY_COL0 = 12, 46 KEY_COL1 = 13, 47 KEY_COL2 = 14, 48 KEY_ROW0 = 15, 49 50 /* aon_pmm_reg_1 */ 51 KEY_ROW1 = 16, 52 KEY_ROW2 = 17, 53 HDMI_SCL = 18, 54 HDMI_SDA = 19, 55 JTAG_TCK = 20, 56 JTAG_TRSTN = 21, 57 JTAG_TMS = 22, 58 JTAG_TDI = 23, 59 JTAG_TDO = 24, 60 I2C0_SCL = 25, 61 I2C0_SDA = 26, 62 I2C1_SCL = 27, 63 I2C1_SDA = 28, 64 AON_RESERVED2 = 29, 65 AON_RESERVED3 = 30, 66 AON_RESERVED4 = 31, 67 68 /* aon_pmm_reg_2 */ 69 SPI1_CLK = 32, 70 SPI1_CS = 33, 71 SPI1_TXD = 34, 72 SPI1_RXD = 35, 73 AON_RESERVED5 = 36, 74 AON_RESERVED6 = 37, 75 AUDIO_DET = 38, 76 SPDIF_OUT = 39, 77 HDMI_CEC = 40, 78 HDMI_HPD = 41, 79 GMAC_25M_OUT = 42, 80 BOOT_SEL0 = 43, 81 BOOT_SEL1 = 44, 82 BOOT_SEL2 = 45, 83 DEEP_SLEEP_OUT_N = 46, 84 AON_RESERVED7 = 47, 85 86 /* top_pmm_reg_0 */ 87 GMII_GTX_CLK = 48, 88 GMII_TX_CLK = 49, 89 GMII_TXD0 = 50, 90 GMII_TXD1 = 51, 91 GMII_TXD2 = 52, 92 GMII_TXD3 = 53, 93 GMII_TXD4 = 54, 94 GMII_TXD5 = 55, 95 GMII_TXD6 = 56, 96 GMII_TXD7 = 57, 97 GMII_TX_ER = 58, 98 GMII_TX_EN = 59, 99 GMII_RX_CLK = 60, 100 GMII_RXD0 = 61, 101 GMII_RXD1 = 62, 102 GMII_RXD2 = 63, 103 104 /* top_pmm_reg_1 */ 105 GMII_RXD3 = 64, 106 GMII_RXD4 = 65, 107 GMII_RXD5 = 66, 108 GMII_RXD6 = 67, 109 GMII_RXD7 = 68, 110 GMII_RX_ER = 69, 111 GMII_RX_DV = 70, 112 GMII_COL = 71, 113 GMII_CRS = 72, 114 GMII_MDC = 73, 115 GMII_MDIO = 74, 116 SDIO1_CLK = 75, 117 SDIO1_CMD = 76, 118 SDIO1_DATA0 = 77, 119 SDIO1_DATA1 = 78, 120 SDIO1_DATA2 = 79, 121 122 /* top_pmm_reg_2 */ 123 SDIO1_DATA3 = 80, 124 SDIO1_CD = 81, 125 SDIO1_WP = 82, 126 USIM1_CD = 83, 127 USIM1_CLK = 84, 128 USIM1_RST = 85, 129 130 /* top_pmm_reg_3 */ 131 USIM1_DATA = 86, 132 SDIO0_CLK = 87, 133 SDIO0_CMD = 88, 134 SDIO0_DATA0 = 89, 135 SDIO0_DATA1 = 90, 136 SDIO0_DATA2 = 91, 137 SDIO0_DATA3 = 92, 138 SDIO0_CD = 93, 139 SDIO0_WP = 94, 140 141 /* top_pmm_reg_4 */ 142 TSI0_DATA0 = 95, 143 SPINOR_CLK = 96, 144 TSI2_DATA = 97, 145 TSI2_CLK = 98, 146 TSI2_SYNC = 99, 147 TSI2_VALID = 100, 148 SPINOR_CS = 101, 149 SPINOR_DQ0 = 102, 150 SPINOR_DQ1 = 103, 151 SPINOR_DQ2 = 104, 152 SPINOR_DQ3 = 105, 153 VGA_HS = 106, 154 VGA_VS = 107, 155 TSI3_DATA = 108, 156 157 /* top_pmm_reg_5 */ 158 TSI3_CLK = 109, 159 TSI3_SYNC = 110, 160 TSI3_VALID = 111, 161 I2S1_WS = 112, 162 I2S1_BCLK = 113, 163 I2S1_MCLK = 114, 164 I2S1_DIN0 = 115, 165 I2S1_DOUT0 = 116, 166 SPI3_CLK = 117, 167 SPI3_CS = 118, 168 SPI3_TXD = 119, 169 NAND_LDO_MS18_SEL = 120, 170 171 /* top_pmm_reg_6 */ 172 SPI3_RXD = 121, 173 I2S0_MCLK = 122, 174 I2S0_BCLK = 123, 175 I2S0_WS = 124, 176 I2S0_DIN0 = 125, 177 I2S0_DOUT0 = 126, 178 I2C5_SCL = 127, 179 I2C5_SDA = 128, 180 SPI2_CLK = 129, 181 SPI2_CS = 130, 182 SPI2_TXD = 131, 183 184 /* top_pmm_reg_7 */ 185 SPI2_RXD = 132, 186 NAND_WP_N = 133, 187 NAND_PAGE_SIZE0 = 134, 188 NAND_PAGE_SIZE1 = 135, 189 NAND_ADDR_CYCLE = 136, 190 NAND_RB0 = 137, 191 NAND_RB1 = 138, 192 NAND_RB2 = 139, 193 NAND_RB3 = 140, 194 195 /* top_pmm_reg_8 */ 196 GMAC_125M_IN = 141, 197 GMAC_50M_OUT = 142, 198 SPINOR_SSCLK_LOOPBACK = 143, 199 SPINOR_SDIO1CLK_LOOPBACK = 144, 200}; 201 202static const struct pinctrl_pin_desc zx296718_pins[] = { 203 /* aon_pmm_reg_0 */ 204 AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0, 205 AON_MUX(0x0, "ANMI"), /* anmi */ 206 AON_MUX(0x1, "AGPIO"), /* agpio29 */ 207 AON_MUX(0x2, "nonAON"), /* pin0 */ 208 AON_MUX(0x3, "EXT_INT"), /* int4 */ 209 TOP_MUX(0x0, "I2C3"), /* scl */ 210 TOP_MUX(0x1, "SPI2"), /* txd */ 211 TOP_MUX(0x2, "I2S1")), /* din0 */ 212 AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9, 213 AON_MUX(0x0, "WD"), /* rst_b */ 214 AON_MUX(0x1, "AGPIO"), /* agpio30 */ 215 AON_MUX(0x2, "nonAON"), /* pin1 */ 216 AON_MUX(0x3, "EXT_INT"), /* int5 */ 217 TOP_MUX(0x0, "I2C3"), /* sda */ 218 TOP_MUX(0x1, "SPI2"), /* rxd */ 219 TOP_MUX(0x2, "I2S0")), /* mclk */ 220 ZX_RESERVED(AON_RESERVED0), 221 ZX_RESERVED(AON_RESERVED1), 222 AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0, 223 AON_MUX(0x0, "SEC"), /* en */ 224 AON_MUX(0x1, "AGPIO"), /* agpio28 */ 225 AON_MUX(0x2, "nonAON"), /* pin3 */ 226 AON_MUX(0x3, "EXT_INT"), /* int7 */ 227 TOP_MUX(0x0, "I2C2"), /* sda */ 228 TOP_MUX(0x1, "SPI2")), /* cs */ 229 AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9, 230 AON_MUX(0x0, "UART0"), /* rxd */ 231 AON_MUX(0x1, "AGPIO"), /* agpio20 */ 232 AON_MUX(0x2, "nonAON")), /* pin34 */ 233 AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18, 234 AON_MUX(0x0, "UART0"), /* txd */ 235 AON_MUX(0x1, "AGPIO"), /* agpio21 */ 236 AON_MUX(0x2, "nonAON")), /* pin32 */ 237 AON_PIN(IR_IN, 0, 0, 0, 0x64, 0, 238 AON_MUX(0x0, "IR"), /* in */ 239 AON_MUX(0x1, "AGPIO"), /* agpio0 */ 240 AON_MUX(0x2, "nonAON")), /* pin27 */ 241 AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9, 242 AON_MUX(0x0, "EXT_INT"), /* int0 */ 243 AON_MUX(0x1, "AGPIO"), /* agpio23 */ 244 AON_MUX(0x2, "nonAON"), /* pin5 */ 245 AON_MUX(0x3, "PCU"), /* test6 */ 246 TOP_MUX(0x0, "SPI0"), /* clk */ 247 TOP_MUX(0x1, "ISP")), /* flash_trig */ 248 AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18, 249 AON_MUX(0x0, "EXT_INT"), /* int1 */ 250 AON_MUX(0x1, "AGPIO"), /* agpio24 */ 251 AON_MUX(0x2, "nonAON"), /* pin6 */ 252 AON_MUX(0x3, "PCU"), /* test0 */ 253 TOP_MUX(0x0, "SPI0"), /* cs */ 254 TOP_MUX(0x1, "ISP")), /* prelight_trig */ 255 AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0, 256 AON_MUX(0x0, "EXT_INT"), /* int2 */ 257 AON_MUX(0x1, "AGPIO"), /* agpio25 */ 258 AON_MUX(0x2, "nonAON"), /* pin7 */ 259 AON_MUX(0x3, "PCU"), /* test1 */ 260 TOP_MUX(0x0, "SPI0"), /* txd */ 261 TOP_MUX(0x1, "ISP")), /* shutter_trig */ 262 AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9, 263 AON_MUX(0x0, "EXT_INT"), /* int3 */ 264 AON_MUX(0x1, "AGPIO"), /* agpio26 */ 265 AON_MUX(0x2, "nonAON"), /* pin8 */ 266 AON_MUX(0x3, "PCU"), /* test2 */ 267 TOP_MUX(0x0, "SPI0"), /* rxd */ 268 TOP_MUX(0x1, "ISP")), /* shutter_open */ 269 AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18, 270 AON_MUX(0x0, "KEY"), /* col0 */ 271 AON_MUX(0x1, "AGPIO"), /* agpio5 */ 272 AON_MUX(0x2, "nonAON"), /* pin9 */ 273 AON_MUX(0x3, "PCU"), /* test3 */ 274 TOP_MUX(0x0, "UART3"), /* rxd */ 275 TOP_MUX(0x1, "I2S0")), /* din1 */ 276 AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0, 277 AON_MUX(0x0, "KEY"), /* col1 */ 278 AON_MUX(0x1, "AGPIO"), /* agpio6 */ 279 AON_MUX(0x2, "nonAON"), /* pin10 */ 280 TOP_MUX(0x0, "UART3"), /* txd */ 281 TOP_MUX(0x1, "I2S0"), /* din2 */ 282 TOP_MUX(0x2, "VGA")), /* scl */ 283 AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9, 284 AON_MUX(0x0, "KEY"), /* col2 */ 285 AON_MUX(0x1, "AGPIO"), /* agpio7 */ 286 AON_MUX(0x2, "nonAON"), /* pin11 */ 287 TOP_MUX(0x0, "PWM"), /* out1 */ 288 TOP_MUX(0x1, "I2S0"), /* din3 */ 289 TOP_MUX(0x2, "VGA")), /* sda */ 290 AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18, 291 AON_MUX(0x0, "KEY"), /* row0 */ 292 AON_MUX(0x1, "AGPIO"), /* agpio8 */ 293 AON_MUX(0x2, "nonAON"), /* pin33 */ 294 AON_MUX(0x3, "WD")), /* rst_b */ 295 296 /* aon_pmm_reg_1 */ 297 AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0, 298 AON_MUX(0x0, "KEY"), /* row1 */ 299 AON_MUX(0x1, "AGPIO"), /* agpio9 */ 300 AON_MUX(0x2, "nonAON"), /* pin12 */ 301 TOP_MUX(0x0, "LCD"), /* port0 lcd_te */ 302 TOP_MUX(0x1, "I2S0"), /* dout2 */ 303 TOP_MUX(0x2, "PWM"), /* out2 */ 304 TOP_MUX(0x3, "VGA")), /* hs1 */ 305 AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9, 306 AON_MUX(0x0, "KEY"), /* row2 */ 307 AON_MUX(0x1, "AGPIO"), /* agpio10 */ 308 AON_MUX(0x2, "nonAON"), /* pin13 */ 309 TOP_MUX(0x0, "LCD"), /* port1 lcd_te */ 310 TOP_MUX(0x1, "I2S0"), /* dout3 */ 311 TOP_MUX(0x2, "PWM"), /* out3 */ 312 TOP_MUX(0x3, "VGA")), /* vs1 */ 313 AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18, 314 AON_MUX(0x0, "PCU"), /* test7 */ 315 AON_MUX(0x1, "AGPIO"), /* agpio3 */ 316 AON_MUX(0x2, "nonAON"), /* pin14 */ 317 TOP_MUX(0x0, "HDMI"), /* scl */ 318 TOP_MUX(0x1, "UART3")), /* rxd */ 319 AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0, 320 AON_MUX(0x0, "PCU"), /* test8 */ 321 AON_MUX(0x1, "AGPIO"), /* agpio4 */ 322 AON_MUX(0x2, "nonAON"), /* pin15 */ 323 TOP_MUX(0x0, "HDMI"), /* sda */ 324 TOP_MUX(0x1, "UART3")), /* txd */ 325 AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18, 326 AON_MUX(0x0, "JTAG"), /* tck */ 327 AON_MUX(0x1, "AGPIO"), /* agpio11 */ 328 AON_MUX(0x2, "nonAON"), /* pin22 */ 329 AON_MUX(0x3, "EXT_INT"), /* int4 */ 330 TOP_MUX(0x0, "SPI4"), /* clk */ 331 TOP_MUX(0x1, "UART1")), /* rxd */ 332 AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0, 333 AON_MUX(0x0, "JTAG"), /* trstn */ 334 AON_MUX(0x1, "AGPIO"), /* agpio12 */ 335 AON_MUX(0x2, "nonAON"), /* pin23 */ 336 AON_MUX(0x3, "EXT_INT"), /* int5 */ 337 TOP_MUX(0x0, "SPI4"), /* cs */ 338 TOP_MUX(0x1, "UART1")), /* txd */ 339 AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9, 340 AON_MUX(0x0, "JTAG"), /* tms */ 341 AON_MUX(0x1, "AGPIO"), /* agpio13 */ 342 AON_MUX(0x2, "nonAON"), /* pin24 */ 343 AON_MUX(0x3, "EXT_INT"), /* int6 */ 344 TOP_MUX(0x0, "SPI4"), /* txd */ 345 TOP_MUX(0x1, "UART2")), /* rxd */ 346 AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18, 347 AON_MUX(0x0, "JTAG"), /* tdi */ 348 AON_MUX(0x1, "AGPIO"), /* agpio14 */ 349 AON_MUX(0x2, "nonAON"), /* pin25 */ 350 AON_MUX(0x3, "EXT_INT"), /* int7 */ 351 TOP_MUX(0x0, "SPI4"), /* rxd */ 352 TOP_MUX(0x1, "UART2")), /* txd */ 353 AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0, 354 AON_MUX(0x0, "JTAG"), /* tdo */ 355 AON_MUX(0x1, "AGPIO"), /* agpio15 */ 356 AON_MUX(0x2, "nonAON")), /* pin26 */ 357 AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9, 358 AON_MUX(0x0, "I2C0"), /* scl */ 359 AON_MUX(0x1, "AGPIO"), /* agpio16 */ 360 AON_MUX(0x2, "nonAON")), /* pin28 */ 361 AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18, 362 AON_MUX(0x0, "I2C0"), /* sda */ 363 AON_MUX(0x1, "AGPIO"), /* agpio17 */ 364 AON_MUX(0x2, "nonAON")), /* pin29 */ 365 AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0, 366 AON_MUX(0x0, "I2C1"), /* scl */ 367 AON_MUX(0x1, "AGPIO"), /* agpio18 */ 368 AON_MUX(0x2, "nonAON"), /* pin30 */ 369 TOP_MUX(0x0, "LCD")), /* port0 lcd_te */ 370 AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9, 371 AON_MUX(0x0, "I2C1"), /* sda */ 372 AON_MUX(0x1, "AGPIO"), /* agpio19 */ 373 AON_MUX(0x2, "nonAON"), /* pin31 */ 374 TOP_MUX(0x0, "LCD")), /* port1 lcd_te */ 375 ZX_RESERVED(AON_RESERVED2), 376 ZX_RESERVED(AON_RESERVED3), 377 ZX_RESERVED(AON_RESERVED4), 378 379 /* aon_pmm_reg_2 */ 380 AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9, 381 AON_MUX(0x0, "EXT_INT"), /* int0 */ 382 AON_MUX(0x1, "PCU"), /* test12 */ 383 AON_MUX(0x2, "nonAON"), /* pin39 */ 384 TOP_MUX(0x0, "SPI1"), /* clk */ 385 TOP_MUX(0x1, "PCM"), /* clk */ 386 TOP_MUX(0x2, "BGPIO"), /* gpio35 */ 387 TOP_MUX(0x3, "I2C4"), /* scl */ 388 TOP_MUX(0x4, "I2S1"), /* mclk */ 389 TOP_MUX(0x5, "ISP")), /* flash_trig */ 390 AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18, 391 AON_MUX(0x0, "EXT_INT"), /* int1 */ 392 AON_MUX(0x1, "PCU"), /* test13 */ 393 AON_MUX(0x2, "nonAON"), /* pin40 */ 394 TOP_MUX(0x0, "SPI1"), /* cs */ 395 TOP_MUX(0x1, "PCM"), /* fs */ 396 TOP_MUX(0x2, "BGPIO"), /* gpio36 */ 397 TOP_MUX(0x3, "I2C4"), /* sda */ 398 TOP_MUX(0x4, "I2S1"), /* bclk */ 399 TOP_MUX(0x5, "ISP")), /* prelight_trig */ 400 AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0, 401 AON_MUX(0x0, "EXT_INT"), /* int2 */ 402 AON_MUX(0x1, "PCU"), /* test14 */ 403 AON_MUX(0x2, "nonAON"), /* pin41 */ 404 TOP_MUX(0x0, "SPI1"), /* txd */ 405 TOP_MUX(0x1, "PCM"), /* txd */ 406 TOP_MUX(0x2, "BGPIO"), /* gpio37 */ 407 TOP_MUX(0x3, "UART5"), /* rxd */ 408 TOP_MUX(0x4, "I2S1"), /* ws */ 409 TOP_MUX(0x5, "ISP")), /* shutter_trig */ 410 AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9, 411 AON_MUX(0x0, "EXT_INT"), /* int3 */ 412 AON_MUX(0x1, "PCU"), /* test15 */ 413 AON_MUX(0x2, "nonAON"), /* pin42 */ 414 TOP_MUX(0x0, "SPI1"), /* rxd */ 415 TOP_MUX(0x1, "PCM"), /* rxd */ 416 TOP_MUX(0x2, "BGPIO"), /* gpio38 */ 417 TOP_MUX(0x3, "UART5"), /* txd */ 418 TOP_MUX(0x4, "I2S1"), /* dout0 */ 419 TOP_MUX(0x5, "ISP")), /* shutter_open */ 420 ZX_RESERVED(AON_RESERVED5), 421 ZX_RESERVED(AON_RESERVED6), 422 AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18, 423 AON_MUX(0x0, "PCU"), /* test4 */ 424 AON_MUX(0x1, "AGPIO"), /* agpio27 */ 425 AON_MUX(0x2, "nonAON"), /* pin2 */ 426 AON_MUX(0x3, "EXT_INT"), /* int16 */ 427 TOP_MUX(0x0, "AUDIO"), /* detect */ 428 TOP_MUX(0x1, "I2C2"), /* scl */ 429 TOP_MUX(0x2, "SPI2")), /* clk */ 430 AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9, 431 AON_MUX(0x0, "PCU"), /* test5 */ 432 AON_MUX(0x1, "AGPIO"), /* agpio22 */ 433 AON_MUX(0x2, "nonAON"), /* pin4 */ 434 TOP_MUX(0x0, "SPDIF"), /* out */ 435 TOP_MUX(0x1, "PWM"), /* out0 */ 436 TOP_MUX(0x2, "ISP")), /* fl_trig */ 437 AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9, 438 AON_MUX(0x0, "PCU"), /* test9 */ 439 AON_MUX(0x1, "AGPIO"), /* agpio1 */ 440 AON_MUX(0x2, "nonAON")), /* pin16 */ 441 AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18, 442 AON_MUX(0x0, "PCU"), /* test10 */ 443 AON_MUX(0x1, "AGPIO"), /* agpio2 */ 444 AON_MUX(0x2, "nonAON")), /* pin17 */ 445 AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0, 446 AON_MUX(0x0, "PCU"), /* test11 */ 447 AON_MUX(0x1, "AGPIO"), /* agpio31 */ 448 AON_MUX(0x2, "nonAON")), /* pin43 */ 449 AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9, 450 AON_MUX(0x0, "BOOT"), /* sel0 */ 451 AON_MUX(0x1, "AGPIO"), /* agpio18 */ 452 AON_MUX(0x2, "nonAON")), /* pin18 */ 453 AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18, 454 AON_MUX(0x0, "BOOT"), /* sel1 */ 455 AON_MUX(0x1, "AGPIO"), /* agpio19 */ 456 AON_MUX(0x2, "nonAON")), /* pin19 */ 457 AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0, 458 AON_MUX(0x0, "BOOT"), /* sel2 */ 459 AON_MUX(0x1, "AGPIO"), /* agpio20 */ 460 AON_MUX(0x2, "nonAON")), /* pin20 */ 461 AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9, 462 AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */ 463 AON_MUX(0x1, "AGPIO"), /* agpio21 */ 464 AON_MUX(0x2, "nonAON")), /* pin21 */ 465 ZX_RESERVED(AON_RESERVED7), 466 467 /* top_pmm_reg_0 */ 468 TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0, 469 TOP_MUX(0x0, "GMII"), /* gtx_clk */ 470 TOP_MUX(0x1, "DVI0"), /* clk */ 471 TOP_MUX(0x2, "BGPIO")), /* gpio0 */ 472 TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9, 473 TOP_MUX(0x0, "GMII"), /* tx_clk */ 474 TOP_MUX(0x1, "DVI0"), /* vs */ 475 TOP_MUX(0x2, "BGPIO")), /* gpio1 */ 476 TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18, 477 TOP_MUX(0x0, "GMII"), /* txd0 */ 478 TOP_MUX(0x1, "DVI0"), /* hs */ 479 TOP_MUX(0x2, "BGPIO")), /* gpio2 */ 480 TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0, 481 TOP_MUX(0x0, "GMII"), /* txd1 */ 482 TOP_MUX(0x1, "DVI0"), /* d0 */ 483 TOP_MUX(0x2, "BGPIO")), /* gpio3 */ 484 TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9, 485 TOP_MUX(0x0, "GMII"), /* txd2 */ 486 TOP_MUX(0x1, "DVI0"), /* d1 */ 487 TOP_MUX(0x2, "BGPIO")), /* gpio4 */ 488 TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18, 489 TOP_MUX(0x0, "GMII"), /* txd3 */ 490 TOP_MUX(0x1, "DVI0"), /* d2 */ 491 TOP_MUX(0x2, "BGPIO")), /* gpio5 */ 492 TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0, 493 TOP_MUX(0x0, "GMII"), /* txd4 */ 494 TOP_MUX(0x1, "DVI0"), /* d3 */ 495 TOP_MUX(0x2, "BGPIO")), /* gpio6 */ 496 TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9, 497 TOP_MUX(0x0, "GMII"), /* txd5 */ 498 TOP_MUX(0x1, "DVI0"), /* d4 */ 499 TOP_MUX(0x2, "BGPIO")), /* gpio7 */ 500 TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18, 501 TOP_MUX(0x0, "GMII"), /* txd6 */ 502 TOP_MUX(0x1, "DVI0"), /* d5 */ 503 TOP_MUX(0x2, "BGPIO")), /* gpio8 */ 504 TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0, 505 TOP_MUX(0x0, "GMII"), /* txd7 */ 506 TOP_MUX(0x1, "DVI0"), /* d6 */ 507 TOP_MUX(0x2, "BGPIO")), /* gpio9 */ 508 TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9, 509 TOP_MUX(0x0, "GMII"), /* tx_er */ 510 TOP_MUX(0x1, "DVI0"), /* d7 */ 511 TOP_MUX(0x2, "BGPIO")), /* gpio10 */ 512 TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18, 513 TOP_MUX(0x0, "GMII"), /* tx_en */ 514 TOP_MUX(0x1, "DVI0"), /* d8 */ 515 TOP_MUX(0x3, "BGPIO")), /* gpio11 */ 516 TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0, 517 TOP_MUX(0x0, "GMII"), /* rx_clk */ 518 TOP_MUX(0x1, "DVI0"), /* d9 */ 519 TOP_MUX(0x3, "BGPIO")), /* gpio12 */ 520 TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9, 521 TOP_MUX(0x0, "GMII"), /* rxd0 */ 522 TOP_MUX(0x1, "DVI0"), /* d10 */ 523 TOP_MUX(0x3, "BGPIO")), /* gpio13 */ 524 TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18, 525 TOP_MUX(0x0, "GMII"), /* rxd1 */ 526 TOP_MUX(0x1, "DVI0"), /* d11 */ 527 TOP_MUX(0x2, "BGPIO")), /* gpio14 */ 528 TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0, 529 TOP_MUX(0x0, "GMII"), /* rxd2 */ 530 TOP_MUX(0x1, "DVI1"), /* clk */ 531 TOP_MUX(0x2, "BGPIO")), /* gpio15 */ 532 533 /* top_pmm_reg_1 */ 534 TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9, 535 TOP_MUX(0x0, "GMII"), /* rxd3 */ 536 TOP_MUX(0x1, "DVI1"), /* hs */ 537 TOP_MUX(0x2, "BGPIO")), /* gpio16 */ 538 TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18, 539 TOP_MUX(0x0, "GMII"), /* rxd4 */ 540 TOP_MUX(0x1, "DVI1"), /* vs */ 541 TOP_MUX(0x2, "BGPIO")), /* gpio17 */ 542 TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0, 543 TOP_MUX(0x0, "GMII"), /* rxd5 */ 544 TOP_MUX(0x1, "DVI1"), /* d0 */ 545 TOP_MUX(0x2, "BGPIO"), /* gpio18 */ 546 TOP_MUX(0x3, "TSI0")), /* dat0 */ 547 TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9, 548 TOP_MUX(0x0, "GMII"), /* rxd6 */ 549 TOP_MUX(0x1, "DVI1"), /* d1 */ 550 TOP_MUX(0x2, "BGPIO"), /* gpio19 */ 551 TOP_MUX(0x3, "TSI0")), /* clk */ 552 TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18, 553 TOP_MUX(0x0, "GMII"), /* rxd7 */ 554 TOP_MUX(0x1, "DVI1"), /* d2 */ 555 TOP_MUX(0x2, "BGPIO"), /* gpio20 */ 556 TOP_MUX(0x3, "TSI0")), /* sync */ 557 TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0, 558 TOP_MUX(0x0, "GMII"), /* rx_er */ 559 TOP_MUX(0x1, "DVI1"), /* d3 */ 560 TOP_MUX(0x2, "BGPIO"), /* gpio21 */ 561 TOP_MUX(0x3, "TSI0")), /* valid */ 562 TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9, 563 TOP_MUX(0x0, "GMII"), /* rx_dv */ 564 TOP_MUX(0x1, "DVI1"), /* d4 */ 565 TOP_MUX(0x2, "BGPIO"), /* gpio22 */ 566 TOP_MUX(0x3, "TSI1")), /* dat0 */ 567 TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18, 568 TOP_MUX(0x0, "GMII"), /* col */ 569 TOP_MUX(0x1, "DVI1"), /* d5 */ 570 TOP_MUX(0x2, "BGPIO"), /* gpio23 */ 571 TOP_MUX(0x3, "TSI1")), /* clk */ 572 TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0, 573 TOP_MUX(0x0, "GMII"), /* crs */ 574 TOP_MUX(0x1, "DVI1"), /* d6 */ 575 TOP_MUX(0x2, "BGPIO"), /* gpio24 */ 576 TOP_MUX(0x3, "TSI1")), /* sync */ 577 TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9, 578 TOP_MUX(0x0, "GMII"), /* mdc */ 579 TOP_MUX(0x1, "DVI1"), /* d7 */ 580 TOP_MUX(0x2, "BGPIO"), /* gpio25 */ 581 TOP_MUX(0x3, "TSI1")), /* valid */ 582 TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18, 583 TOP_MUX(0x0, "GMII"), /* mdio */ 584 TOP_MUX(0x2, "BGPIO")), /* gpio26 */ 585 TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18, 586 TOP_MUX(0x0, "SDIO1"), /* clk */ 587 TOP_MUX(0x1, "USIM0"), /* clk */ 588 TOP_MUX(0x2, "BGPIO"), /* gpio27 */ 589 TOP_MUX(0x3, "SPINOR")), /* clk */ 590 TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0, 591 TOP_MUX(0x0, "SDIO1"), /* cmd */ 592 TOP_MUX(0x1, "USIM0"), /* cd */ 593 TOP_MUX(0x2, "BGPIO"), /* gpio28 */ 594 TOP_MUX(0x3, "SPINOR")), /* cs */ 595 TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9, 596 TOP_MUX(0x0, "SDIO1"), /* dat0 */ 597 TOP_MUX(0x1, "USIM0"), /* rst */ 598 TOP_MUX(0x2, "BGPIO"), /* gpio29 */ 599 TOP_MUX(0x3, "SPINOR")), /* dq0 */ 600 TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18, 601 TOP_MUX(0x0, "SDIO1"), /* dat1 */ 602 TOP_MUX(0x1, "USIM0"), /* data */ 603 TOP_MUX(0x2, "BGPIO"), /* gpio30 */ 604 TOP_MUX(0x3, "SPINOR")), /* dq1 */ 605 TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0, 606 TOP_MUX(0x0, "SDIO1"), /* dat2 */ 607 TOP_MUX(0x1, "BGPIO"), /* gpio31 */ 608 TOP_MUX(0x2, "SPINOR")), /* dq2 */ 609 610 /* top_pmm_reg_2 */ 611 TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9, 612 TOP_MUX(0x0, "SDIO1"), /* dat3 */ 613 TOP_MUX(0x1, "BGPIO"), /* gpio32 */ 614 TOP_MUX(0x2, "SPINOR")), /* dq3 */ 615 TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18, 616 TOP_MUX(0x0, "SDIO1"), /* cd */ 617 TOP_MUX(0x1, "BGPIO"), /* gpio33 */ 618 TOP_MUX(0x2, "ISP")), /* fl_trig */ 619 TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0, 620 TOP_MUX(0x0, "SDIO1"), /* wp */ 621 TOP_MUX(0x1, "BGPIO"), /* gpio34 */ 622 TOP_MUX(0x2, "ISP")), /* ref_clk */ 623 TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18, 624 TOP_MUX(0x0, "USIM1"), /* cd */ 625 TOP_MUX(0x1, "UART4"), /* rxd */ 626 TOP_MUX(0x2, "BGPIO"), /* gpio39 */ 627 TOP_MUX(0x3, "SPI3"), /* clk */ 628 TOP_MUX(0x4, "I2S0"), /* bclk */ 629 TOP_MUX(0x5, "B_DVI0")), /* d8 */ 630 TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18, 631 TOP_MUX(0x0, "USIM1"), /* clk */ 632 TOP_MUX(0x1, "UART4"), /* txd */ 633 TOP_MUX(0x2, "BGPIO"), /* gpio40 */ 634 TOP_MUX(0x3, "SPI3"), /* cs */ 635 TOP_MUX(0x4, "I2S0"), /* ws */ 636 TOP_MUX(0x5, "B_DVI0")), /* d9 */ 637 TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0, 638 TOP_MUX(0x0, "USIM1"), /* rst */ 639 TOP_MUX(0x1, "UART4"), /* cts */ 640 TOP_MUX(0x2, "BGPIO"), /* gpio41 */ 641 TOP_MUX(0x3, "SPI3"), /* txd */ 642 TOP_MUX(0x4, "I2S0"), /* dout0 */ 643 TOP_MUX(0x5, "B_DVI0")), /* d10 */ 644 645 /* top_pmm_reg_3 */ 646 TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9, 647 TOP_MUX(0x0, "USIM1"), /* dat */ 648 TOP_MUX(0x1, "UART4"), /* rst */ 649 TOP_MUX(0x2, "BGPIO"), /* gpio42 */ 650 TOP_MUX(0x3, "SPI3"), /* rxd */ 651 TOP_MUX(0x4, "I2S0"), /* din0 */ 652 TOP_MUX(0x5, "B_DVI0")), /* d11 */ 653 TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0, 654 TOP_MUX(0x0, "SDIO0"), /* clk */ 655 TOP_MUX(0x1, "GPIO")), /* gpio43 */ 656 TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9, 657 TOP_MUX(0x0, "SDIO0"), /* cmd */ 658 TOP_MUX(0x1, "GPIO")), /* gpio44 */ 659 TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18, 660 TOP_MUX(0x0, "SDIO0"), /* dat0 */ 661 TOP_MUX(0x1, "GPIO")), /* gpio45 */ 662 TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0, 663 TOP_MUX(0x0, "SDIO0"), /* dat1 */ 664 TOP_MUX(0x1, "GPIO")), /* gpio46 */ 665 TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9, 666 TOP_MUX(0x0, "SDIO0"), /* dat2 */ 667 TOP_MUX(0x1, "GPIO")), /* gpio47 */ 668 TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18, 669 TOP_MUX(0x0, "SDIO0"), /* dat3 */ 670 TOP_MUX(0x1, "GPIO")), /* gpio48 */ 671 TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0, 672 TOP_MUX(0x0, "SDIO0"), /* cd */ 673 TOP_MUX(0x1, "GPIO")), /* gpio49 */ 674 TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9, 675 TOP_MUX(0x0, "SDIO0"), /* wp */ 676 TOP_MUX(0x1, "GPIO")), /* gpio50 */ 677 678 /* top_pmm_reg_4 */ 679 TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18, 680 TOP_MUX(0x0, "TSI0"), /* dat0 */ 681 TOP_MUX(0x1, "LCD"), /* clk */ 682 TOP_MUX(0x2, "BGPIO")), /* gpio51 */ 683 TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18, 684 TOP_MUX(0x0, "SPINOR"), /* clk */ 685 TOP_MUX(0x1, "TSI0"), /* dat1 */ 686 TOP_MUX(0x2, "LCD"), /* dat0 */ 687 TOP_MUX(0x3, "BGPIO")), /* gpio52 */ 688 TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0, 689 TOP_MUX(0x0, "TSI2"), /* dat */ 690 TOP_MUX(0x1, "TSI0"), /* dat2 */ 691 TOP_MUX(0x2, "LCD"), /* dat1 */ 692 TOP_MUX(0x3, "BGPIO")), /* gpio53 */ 693 TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9, 694 TOP_MUX(0x0, "TSI2"), /* clk */ 695 TOP_MUX(0x1, "TSI0"), /* dat3 */ 696 TOP_MUX(0x2, "LCD"), /* dat2 */ 697 TOP_MUX(0x3, "BGPIO")), /* gpio54 */ 698 TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18, 699 TOP_MUX(0x0, "TSI2"), /* sync */ 700 TOP_MUX(0x1, "TSI0"), /* dat4 */ 701 TOP_MUX(0x2, "LCD"), /* dat3 */ 702 TOP_MUX(0x3, "BGPIO")), /* gpio55 */ 703 TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0, 704 TOP_MUX(0x0, "TSI2"), /* valid */ 705 TOP_MUX(0x1, "TSI0"), /* dat5 */ 706 TOP_MUX(0x2, "LCD"), /* dat4 */ 707 TOP_MUX(0x3, "BGPIO")), /* gpio56 */ 708 TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9, 709 TOP_MUX(0x0, "SPINOR"), /* cs */ 710 TOP_MUX(0x1, "TSI0"), /* dat6 */ 711 TOP_MUX(0x2, "LCD"), /* dat5 */ 712 TOP_MUX(0x3, "BGPIO")), /* gpio57 */ 713 TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18, 714 TOP_MUX(0x0, "SPINOR"), /* dq0 */ 715 TOP_MUX(0x1, "TSI0"), /* dat7 */ 716 TOP_MUX(0x2, "LCD"), /* dat6 */ 717 TOP_MUX(0x3, "BGPIO")), /* gpio58 */ 718 TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0, 719 TOP_MUX(0x0, "SPINOR"), /* dq1 */ 720 TOP_MUX(0x1, "TSI0"), /* clk */ 721 TOP_MUX(0x2, "LCD"), /* dat7 */ 722 TOP_MUX(0x3, "BGPIO")), /* gpio59 */ 723 TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9, 724 TOP_MUX(0x0, "SPINOR"), /* dq2 */ 725 TOP_MUX(0x1, "TSI0"), /* sync */ 726 TOP_MUX(0x2, "LCD"), /* dat8 */ 727 TOP_MUX(0x3, "BGPIO")), /* gpio60 */ 728 TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18, 729 TOP_MUX(0x0, "SPINOR"), /* dq3 */ 730 TOP_MUX(0x1, "TSI0"), /* valid */ 731 TOP_MUX(0x2, "LCD"), /* dat9 */ 732 TOP_MUX(0x3, "BGPIO")), /* gpio61 */ 733 TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0, 734 TOP_MUX(0x0, "VGA"), /* hs */ 735 TOP_MUX(0x1, "TSI1"), /* dat0 */ 736 TOP_MUX(0x2, "LCD"), /* dat10 */ 737 TOP_MUX(0x3, "BGPIO"), /* gpio62 */ 738 TOP_MUX(0x4, "I2S1"), /* din1 */ 739 TOP_MUX(0x5, "B_DVI0")), /* clk */ 740 TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9, 741 TOP_MUX(0x0, "VGA"), /* vs0 */ 742 TOP_MUX(0x1, "TSI1"), /* dat1 */ 743 TOP_MUX(0x2, "LCD"), /* dat11 */ 744 TOP_MUX(0x3, "BGPIO"), /* gpio63 */ 745 TOP_MUX(0x4, "I2S1"), /* din2 */ 746 TOP_MUX(0x5, "B_DVI0")), /* vs */ 747 TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18, 748 TOP_MUX(0x0, "TSI3"), /* dat */ 749 TOP_MUX(0x1, "TSI1"), /* dat2 */ 750 TOP_MUX(0x2, "LCD"), /* dat12 */ 751 TOP_MUX(0x3, "BGPIO"), /* gpio64 */ 752 TOP_MUX(0x4, "I2S1"), /* din3 */ 753 TOP_MUX(0x5, "B_DVI0")), /* hs */ 754 755 /* top_pmm_reg_5 */ 756 TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0, 757 TOP_MUX(0x0, "TSI3"), /* clk */ 758 TOP_MUX(0x1, "TSI1"), /* dat3 */ 759 TOP_MUX(0x2, "LCD"), /* dat13 */ 760 TOP_MUX(0x3, "BGPIO"), /* gpio65 */ 761 TOP_MUX(0x4, "I2S1"), /* dout1 */ 762 TOP_MUX(0x5, "B_DVI0")), /* d0 */ 763 TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9, 764 TOP_MUX(0x0, "TSI3"), /* sync */ 765 TOP_MUX(0x1, "TSI1"), /* dat4 */ 766 TOP_MUX(0x2, "LCD"), /* dat14 */ 767 TOP_MUX(0x3, "BGPIO"), /* gpio66 */ 768 TOP_MUX(0x4, "I2S1"), /* dout2 */ 769 TOP_MUX(0x5, "B_DVI0")), /* d1 */ 770 TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18, 771 TOP_MUX(0x0, "TSI3"), /* valid */ 772 TOP_MUX(0x1, "TSI1"), /* dat5 */ 773 TOP_MUX(0x2, "LCD"), /* dat15 */ 774 TOP_MUX(0x3, "BGPIO"), /* gpio67 */ 775 TOP_MUX(0x4, "I2S1"), /* dout3 */ 776 TOP_MUX(0x5, "B_DVI0")), /* d2 */ 777 TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0, 778 TOP_MUX(0x0, "I2S1"), /* ws */ 779 TOP_MUX(0x1, "TSI1"), /* dat6 */ 780 TOP_MUX(0x2, "LCD"), /* dat16 */ 781 TOP_MUX(0x3, "BGPIO"), /* gpio68 */ 782 TOP_MUX(0x4, "VGA"), /* scl */ 783 TOP_MUX(0x5, "B_DVI0")), /* d3 */ 784 TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9, 785 TOP_MUX(0x0, "I2S1"), /* bclk */ 786 TOP_MUX(0x1, "TSI1"), /* dat7 */ 787 TOP_MUX(0x2, "LCD"), /* dat17 */ 788 TOP_MUX(0x3, "BGPIO"), /* gpio69 */ 789 TOP_MUX(0x4, "VGA"), /* sda */ 790 TOP_MUX(0x5, "B_DVI0")), /* d4 */ 791 TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18, 792 TOP_MUX(0x0, "I2S1"), /* mclk */ 793 TOP_MUX(0x1, "TSI1"), /* clk */ 794 TOP_MUX(0x2, "LCD"), /* dat18 */ 795 TOP_MUX(0x3, "BGPIO")), /* gpio70 */ 796 TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0, 797 TOP_MUX(0x0, "I2S1"), /* din0 */ 798 TOP_MUX(0x1, "TSI1"), /* sync */ 799 TOP_MUX(0x2, "LCD"), /* dat19 */ 800 TOP_MUX(0x3, "BGPIO")), /* gpio71 */ 801 TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9, 802 TOP_MUX(0x0, "I2S1"), /* dout0 */ 803 TOP_MUX(0x1, "TSI1"), /* valid */ 804 TOP_MUX(0x2, "LCD"), /* dat20 */ 805 TOP_MUX(0x3, "BGPIO")), /* gpio72 */ 806 TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18, 807 TOP_MUX(0x0, "SPI3"), /* clk */ 808 TOP_MUX(0x1, "TSO1"), /* clk */ 809 TOP_MUX(0x2, "LCD"), /* dat21 */ 810 TOP_MUX(0x3, "BGPIO"), /* gpio73 */ 811 TOP_MUX(0x4, "UART5"), /* rxd */ 812 TOP_MUX(0x5, "PCM"), /* fs */ 813 TOP_MUX(0x6, "I2S0"), /* din1 */ 814 TOP_MUX(0x7, "B_DVI0")), /* d5 */ 815 TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0, 816 TOP_MUX(0x0, "SPI3"), /* cs */ 817 TOP_MUX(0x1, "TSO1"), /* dat0 */ 818 TOP_MUX(0x2, "LCD"), /* dat22 */ 819 TOP_MUX(0x3, "BGPIO"), /* gpio74 */ 820 TOP_MUX(0x4, "UART5"), /* txd */ 821 TOP_MUX(0x5, "PCM"), /* clk */ 822 TOP_MUX(0x6, "I2S0"), /* din2 */ 823 TOP_MUX(0x7, "B_DVI0")), /* d6 */ 824 TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9, 825 TOP_MUX(0x0, "SPI3"), /* txd */ 826 TOP_MUX(0x1, "TSO1"), /* dat1 */ 827 TOP_MUX(0x2, "LCD"), /* dat23 */ 828 TOP_MUX(0x3, "BGPIO"), /* gpio75 */ 829 TOP_MUX(0x4, "UART5"), /* cts */ 830 TOP_MUX(0x5, "PCM"), /* txd */ 831 TOP_MUX(0x6, "I2S0"), /* din3 */ 832 TOP_MUX(0x7, "B_DVI0")), /* d7 */ 833 TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0, 834 TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */ 835 TOP_MUX(0x1, "BGPIO")), /* gpio99 */ 836 837 /* top_pmm_reg_6 */ 838 TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18, 839 TOP_MUX(0x0, "SPI3"), /* rxd */ 840 TOP_MUX(0x1, "TSO1"), /* dat2 */ 841 TOP_MUX(0x2, "LCD"), /* stvu_vsync */ 842 TOP_MUX(0x3, "BGPIO"), /* gpio76 */ 843 TOP_MUX(0x4, "UART5"), /* rts */ 844 TOP_MUX(0x5, "PCM"), /* rxd */ 845 TOP_MUX(0x6, "I2S0"), /* dout1 */ 846 TOP_MUX(0x7, "B_DVI1")), /* clk */ 847 TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0, 848 TOP_MUX(0x0, "I2S0"), /* mclk */ 849 TOP_MUX(0x1, "TSO1"), /* dat3 */ 850 TOP_MUX(0x2, "LCD"), /* stvd */ 851 TOP_MUX(0x3, "BGPIO"), /* gpio77 */ 852 TOP_MUX(0x4, "USIM0"), /* cd */ 853 TOP_MUX(0x5, "B_DVI1")), /* vs */ 854 TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9, 855 TOP_MUX(0x0, "I2S0"), /* bclk */ 856 TOP_MUX(0x1, "TSO1"), /* dat4 */ 857 TOP_MUX(0x2, "LCD"), /* sthl_hsync */ 858 TOP_MUX(0x3, "BGPIO"), /* gpio78 */ 859 TOP_MUX(0x4, "USIM0"), /* clk */ 860 TOP_MUX(0x5, "B_DVI1")), /* hs */ 861 TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18, 862 TOP_MUX(0x0, "I2S0"), /* ws */ 863 TOP_MUX(0x1, "TSO1"), /* dat5 */ 864 TOP_MUX(0x2, "LCD"), /* sthr */ 865 TOP_MUX(0x3, "BGPIO"), /* gpio79 */ 866 TOP_MUX(0x4, "USIM0"), /* rst */ 867 TOP_MUX(0x5, "B_DVI1")), /* d0 */ 868 TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0, 869 TOP_MUX(0x0, "I2S0"), /* din0 */ 870 TOP_MUX(0x1, "TSO1"), /* dat6 */ 871 TOP_MUX(0x2, "LCD"), /* oev_dataen */ 872 TOP_MUX(0x3, "BGPIO"), /* gpio80 */ 873 TOP_MUX(0x4, "USIM0"), /* dat */ 874 TOP_MUX(0x5, "B_DVI1")), /* d1 */ 875 TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9, 876 TOP_MUX(0x0, "I2S0"), /* dout0 */ 877 TOP_MUX(0x1, "TSO1"), /* dat7 */ 878 TOP_MUX(0x2, "LCD"), /* ckv */ 879 TOP_MUX(0x3, "BGPIO")), /* gpio81 */ 880 TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18, 881 TOP_MUX(0x0, "I2C5"), /* scl */ 882 TOP_MUX(0x1, "TSO1"), /* sync */ 883 TOP_MUX(0x2, "LCD"), /* ld */ 884 TOP_MUX(0x3, "BGPIO"), /* gpio82 */ 885 TOP_MUX(0x4, "PWM"), /* out2 */ 886 TOP_MUX(0x5, "I2S0"), /* dout2 */ 887 TOP_MUX(0x6, "B_DVI1")), /* d2 */ 888 TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0, 889 TOP_MUX(0x0, "I2C5"), /* sda */ 890 TOP_MUX(0x1, "TSO1"), /* vld */ 891 TOP_MUX(0x2, "LCD"), /* pol */ 892 TOP_MUX(0x3, "BGPIO"), /* gpio83 */ 893 TOP_MUX(0x4, "PWM"), /* out3 */ 894 TOP_MUX(0x5, "I2S0"), /* dout3 */ 895 TOP_MUX(0x6, "B_DVI1")), /* d3 */ 896 TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9, 897 TOP_MUX(0x0, "SPI2"), /* clk */ 898 TOP_MUX(0x1, "TSO0"), /* clk */ 899 TOP_MUX(0x2, "LCD"), /* degsl */ 900 TOP_MUX(0x3, "BGPIO"), /* gpio84 */ 901 TOP_MUX(0x4, "I2C4"), /* scl */ 902 TOP_MUX(0x5, "B_DVI1")), /* d4 */ 903 TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18, 904 TOP_MUX(0x0, "SPI2"), /* cs */ 905 TOP_MUX(0x1, "TSO0"), /* data */ 906 TOP_MUX(0x2, "LCD"), /* rev */ 907 TOP_MUX(0x3, "BGPIO"), /* gpio85 */ 908 TOP_MUX(0x4, "I2C4"), /* sda */ 909 TOP_MUX(0x5, "B_DVI1")), /* d5 */ 910 TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0, 911 TOP_MUX(0x0, "SPI2"), /* txd */ 912 TOP_MUX(0x1, "TSO0"), /* sync */ 913 TOP_MUX(0x2, "LCD"), /* u_d */ 914 TOP_MUX(0x3, "BGPIO"), /* gpio86 */ 915 TOP_MUX(0x4, "I2C4"), /* scl */ 916 TOP_MUX(0x5, "B_DVI1")), /* d6 */ 917 918 /* top_pmm_reg_7 */ 919 TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9, 920 TOP_MUX(0x0, "SPI2"), /* rxd */ 921 TOP_MUX(0x1, "TSO0"), /* vld */ 922 TOP_MUX(0x2, "LCD"), /* r_l */ 923 TOP_MUX(0x3, "BGPIO"), /* gpio87 */ 924 TOP_MUX(0x4, "I2C3"), /* sda */ 925 TOP_MUX(0x5, "B_DVI1")), /* d7 */ 926 TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9, 927 TOP_MUX(0x0, "NAND"), /* wp */ 928 TOP_MUX(0x1, "PWM"), /* out2 */ 929 TOP_MUX(0x2, "SPI2"), /* clk */ 930 TOP_MUX(0x3, "BGPIO"), /* gpio88 */ 931 TOP_MUX(0x4, "TSI0"), /* dat0 */ 932 TOP_MUX(0x5, "I2S1")), /* din1 */ 933 TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0, 934 TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */ 935 TOP_MUX(0x1, "PWM"), /* out3 */ 936 TOP_MUX(0x2, "SPI2"), /* cs */ 937 TOP_MUX(0x3, "BGPIO"), /* gpio89 */ 938 TOP_MUX(0x4, "TSI0"), /* clk */ 939 TOP_MUX(0x5, "I2S1")), /* din2 */ 940 TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9, 941 TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */ 942 TOP_MUX(0x1, "I2C4"), /* scl */ 943 TOP_MUX(0x2, "SPI2"), /* txd */ 944 TOP_MUX(0x3, "BGPIO"), /* gpio90 */ 945 TOP_MUX(0x4, "TSI0"), /* sync */ 946 TOP_MUX(0x5, "I2S1")), /* din3 */ 947 TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18, 948 TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */ 949 TOP_MUX(0x1, "I2C4"), /* sda */ 950 TOP_MUX(0x2, "SPI2"), /* rxd */ 951 TOP_MUX(0x3, "BGPIO"), /* gpio91 */ 952 TOP_MUX(0x4, "TSI0"), /* valid */ 953 TOP_MUX(0x5, "I2S1")), /* dout1 */ 954 TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0, 955 TOP_MUX(0x0, "NAND"), /* rdy_busy0 */ 956 TOP_MUX(0x1, "I2C2"), /* scl */ 957 TOP_MUX(0x2, "USIM0"), /* cd */ 958 TOP_MUX(0x3, "BGPIO"), /* gpio92 */ 959 TOP_MUX(0x4, "TSI1")), /* data0 */ 960 TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9, 961 TOP_MUX(0x0, "NAND"), /* rdy_busy1 */ 962 TOP_MUX(0x1, "I2C2"), /* sda */ 963 TOP_MUX(0x2, "USIM0"), /* clk */ 964 TOP_MUX(0x3, "BGPIO"), /* gpio93 */ 965 TOP_MUX(0x4, "TSI1")), /* clk */ 966 TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18, 967 TOP_MUX(0x0, "NAND"), /* rdy_busy2 */ 968 TOP_MUX(0x1, "UART5"), /* rxd */ 969 TOP_MUX(0x2, "USIM0"), /* rst */ 970 TOP_MUX(0x3, "BGPIO"), /* gpio94 */ 971 TOP_MUX(0x4, "TSI1"), /* sync */ 972 TOP_MUX(0x4, "I2S1")), /* dout2 */ 973 TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18, 974 TOP_MUX(0x0, "NAND"), /* rdy_busy3 */ 975 TOP_MUX(0x1, "UART5"), /* txd */ 976 TOP_MUX(0x2, "USIM0"), /* dat */ 977 TOP_MUX(0x3, "BGPIO"), /* gpio95 */ 978 TOP_MUX(0x4, "TSI1"), /* valid */ 979 TOP_MUX(0x4, "I2S1")), /* dout3 */ 980 981 /* top_pmm_reg_8 */ 982 TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0, 983 TOP_MUX(0x0, "GMII"), /* 125m_in */ 984 TOP_MUX(0x1, "USB2"), /* 0_drvvbus */ 985 TOP_MUX(0x2, "ISP"), /* ref_clk */ 986 TOP_MUX(0x3, "BGPIO")), /* gpio96 */ 987 TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9, 988 TOP_MUX(0x0, "GMII"), /* 50m_out */ 989 TOP_MUX(0x1, "USB2"), /* 1_drvvbus */ 990 TOP_MUX(0x2, "BGPIO"), /* gpio97 */ 991 TOP_MUX(0x3, "USB2")), /* 0_drvvbus */ 992 TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9, 993 TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */ 994 TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18, 995 TOP_MUX(0x0, "SPINOR")), /* ssclk_i */ 996}; 997 998static struct zx_pinctrl_soc_info zx296718_pinctrl_info = { 999 .pins = zx296718_pins, 1000 .npins = ARRAY_SIZE(zx296718_pins), 1001}; 1002 1003static int zx296718_pinctrl_probe(struct platform_device *pdev) 1004{ 1005 return zx_pinctrl_init(pdev, &zx296718_pinctrl_info); 1006} 1007 1008static const struct of_device_id zx296718_pinctrl_match[] = { 1009 { .compatible = "zte,zx296718-pmm", }, 1010 {} 1011}; 1012MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match); 1013 1014static struct platform_driver zx296718_pinctrl_driver = { 1015 .probe = zx296718_pinctrl_probe, 1016 .driver = { 1017 .name = "zx296718-pinctrl", 1018 .of_match_table = zx296718_pinctrl_match, 1019 }, 1020}; 1021builtin_platform_driver(zx296718_pinctrl_driver); 1022 1023MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver"); 1024MODULE_LICENSE("GPL"); 1025