1/* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/io.h> 14#include <linux/clk.h> 15#include <linux/gpio/driver.h> 16#include <linux/interrupt.h> 17#include <linux/irqdomain.h> 18#include <linux/irqchip/chained_irq.h> 19#include <linux/export.h> 20#include <linux/of.h> 21#include <linux/of_clk.h> 22#include <linux/of_address.h> 23#include <linux/of_device.h> 24#include <linux/of_irq.h> 25#include <linux/pinctrl/consumer.h> 26#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinconf-generic.h> 29#include <linux/pinctrl/pinmux.h> 30#include <linux/regulator/consumer.h> 31#include <linux/platform_device.h> 32#include <linux/slab.h> 33 34#include <dt-bindings/pinctrl/sun4i-a10.h> 35 36#include "../core.h" 37#include "pinctrl-sunxi.h" 38 39/* 40 * These lock classes tell lockdep that GPIO IRQs are in a different 41 * category than their parents, so it won't report false recursion. 42 */ 43static struct lock_class_key sunxi_pinctrl_irq_lock_class; 44static struct lock_class_key sunxi_pinctrl_irq_request_class; 45 46static struct irq_chip sunxi_pinctrl_edge_irq_chip; 47static struct irq_chip sunxi_pinctrl_level_irq_chip; 48 49static struct sunxi_pinctrl_group * 50sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 51{ 52 int i; 53 54 for (i = 0; i < pctl->ngroups; i++) { 55 struct sunxi_pinctrl_group *grp = pctl->groups + i; 56 57 if (!strcmp(grp->name, group)) 58 return grp; 59 } 60 61 return NULL; 62} 63 64static struct sunxi_pinctrl_function * 65sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 66 const char *name) 67{ 68 struct sunxi_pinctrl_function *func = pctl->functions; 69 int i; 70 71 for (i = 0; i < pctl->nfunctions; i++) { 72 if (!func[i].name) 73 break; 74 75 if (!strcmp(func[i].name, name)) 76 return func + i; 77 } 78 79 return NULL; 80} 81 82static struct sunxi_desc_function * 83sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 84 const char *pin_name, 85 const char *func_name) 86{ 87 int i; 88 89 for (i = 0; i < pctl->desc->npins; i++) { 90 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 91 92 if (!strcmp(pin->pin.name, pin_name)) { 93 struct sunxi_desc_function *func = pin->functions; 94 95 while (func->name) { 96 if (!strcmp(func->name, func_name) && 97 (!func->variant || 98 func->variant & pctl->variant)) 99 return func; 100 101 func++; 102 } 103 } 104 } 105 106 return NULL; 107} 108 109static struct sunxi_desc_function * 110sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 111 const u16 pin_num, 112 const char *func_name) 113{ 114 int i; 115 116 for (i = 0; i < pctl->desc->npins; i++) { 117 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 118 119 if (pin->pin.number == pin_num) { 120 struct sunxi_desc_function *func = pin->functions; 121 122 while (func->name) { 123 if (!strcmp(func->name, func_name)) 124 return func; 125 126 func++; 127 } 128 } 129 } 130 131 return NULL; 132} 133 134static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 135{ 136 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 137 138 return pctl->ngroups; 139} 140 141static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 142 unsigned group) 143{ 144 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 145 146 return pctl->groups[group].name; 147} 148 149static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 150 unsigned group, 151 const unsigned **pins, 152 unsigned *num_pins) 153{ 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 156 *pins = (unsigned *)&pctl->groups[group].pin; 157 *num_pins = 1; 158 159 return 0; 160} 161 162static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 163{ 164 return of_find_property(node, "bias-pull-up", NULL) || 165 of_find_property(node, "bias-pull-down", NULL) || 166 of_find_property(node, "bias-disable", NULL) || 167 of_find_property(node, "allwinner,pull", NULL); 168} 169 170static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 171{ 172 return of_find_property(node, "drive-strength", NULL) || 173 of_find_property(node, "allwinner,drive", NULL); 174} 175 176static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 177{ 178 u32 val; 179 180 /* Try the new style binding */ 181 if (of_find_property(node, "bias-pull-up", NULL)) 182 return PIN_CONFIG_BIAS_PULL_UP; 183 184 if (of_find_property(node, "bias-pull-down", NULL)) 185 return PIN_CONFIG_BIAS_PULL_DOWN; 186 187 if (of_find_property(node, "bias-disable", NULL)) 188 return PIN_CONFIG_BIAS_DISABLE; 189 190 /* And fall back to the old binding */ 191 if (of_property_read_u32(node, "allwinner,pull", &val)) 192 return -EINVAL; 193 194 switch (val) { 195 case SUN4I_PINCTRL_NO_PULL: 196 return PIN_CONFIG_BIAS_DISABLE; 197 case SUN4I_PINCTRL_PULL_UP: 198 return PIN_CONFIG_BIAS_PULL_UP; 199 case SUN4I_PINCTRL_PULL_DOWN: 200 return PIN_CONFIG_BIAS_PULL_DOWN; 201 } 202 203 return -EINVAL; 204} 205 206static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 207{ 208 u32 val; 209 210 /* Try the new style binding */ 211 if (!of_property_read_u32(node, "drive-strength", &val)) { 212 /* We can't go below 10mA ... */ 213 if (val < 10) 214 return -EINVAL; 215 216 /* ... and only up to 40 mA ... */ 217 if (val > 40) 218 val = 40; 219 220 /* by steps of 10 mA */ 221 return rounddown(val, 10); 222 } 223 224 /* And then fall back to the old binding */ 225 if (of_property_read_u32(node, "allwinner,drive", &val)) 226 return -EINVAL; 227 228 return (val + 1) * 10; 229} 230 231static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 232{ 233 const char *function; 234 int ret; 235 236 /* Try the generic binding */ 237 ret = of_property_read_string(node, "function", &function); 238 if (!ret) 239 return function; 240 241 /* And fall back to our legacy one */ 242 ret = of_property_read_string(node, "allwinner,function", &function); 243 if (!ret) 244 return function; 245 246 return NULL; 247} 248 249static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 250 int *npins) 251{ 252 int count; 253 254 /* Try the generic binding */ 255 count = of_property_count_strings(node, "pins"); 256 if (count > 0) { 257 *npins = count; 258 return "pins"; 259 } 260 261 /* And fall back to our legacy one */ 262 count = of_property_count_strings(node, "allwinner,pins"); 263 if (count > 0) { 264 *npins = count; 265 return "allwinner,pins"; 266 } 267 268 return NULL; 269} 270 271static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 272 unsigned int *len) 273{ 274 unsigned long *pinconfig; 275 unsigned int configlen = 0, idx = 0; 276 int ret; 277 278 if (sunxi_pctrl_has_drive_prop(node)) 279 configlen++; 280 if (sunxi_pctrl_has_bias_prop(node)) 281 configlen++; 282 283 /* 284 * If we don't have any configuration, bail out 285 */ 286 if (!configlen) 287 return NULL; 288 289 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); 290 if (!pinconfig) 291 return ERR_PTR(-ENOMEM); 292 293 if (sunxi_pctrl_has_drive_prop(node)) { 294 int drive = sunxi_pctrl_parse_drive_prop(node); 295 if (drive < 0) { 296 ret = drive; 297 goto err_free; 298 } 299 300 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 301 drive); 302 } 303 304 if (sunxi_pctrl_has_bias_prop(node)) { 305 int pull = sunxi_pctrl_parse_bias_prop(node); 306 int arg = 0; 307 if (pull < 0) { 308 ret = pull; 309 goto err_free; 310 } 311 312 if (pull != PIN_CONFIG_BIAS_DISABLE) 313 arg = 1; /* hardware uses weak pull resistors */ 314 315 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 316 } 317 318 319 *len = configlen; 320 return pinconfig; 321 322err_free: 323 kfree(pinconfig); 324 return ERR_PTR(ret); 325} 326 327static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 328 struct device_node *node, 329 struct pinctrl_map **map, 330 unsigned *num_maps) 331{ 332 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 333 unsigned long *pinconfig; 334 struct property *prop; 335 const char *function, *pin_prop; 336 const char *group; 337 int ret, npins, nmaps, configlen = 0, i = 0; 338 339 *map = NULL; 340 *num_maps = 0; 341 342 function = sunxi_pctrl_parse_function_prop(node); 343 if (!function) { 344 dev_err(pctl->dev, "missing function property in node %pOFn\n", 345 node); 346 return -EINVAL; 347 } 348 349 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 350 if (!pin_prop) { 351 dev_err(pctl->dev, "missing pins property in node %pOFn\n", 352 node); 353 return -EINVAL; 354 } 355 356 /* 357 * We have two maps for each pin: one for the function, one 358 * for the configuration (bias, strength, etc). 359 * 360 * We might be slightly overshooting, since we might not have 361 * any configuration. 362 */ 363 nmaps = npins * 2; 364 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL); 365 if (!*map) 366 return -ENOMEM; 367 368 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 369 if (IS_ERR(pinconfig)) { 370 ret = PTR_ERR(pinconfig); 371 goto err_free_map; 372 } 373 374 of_property_for_each_string(node, pin_prop, prop, group) { 375 struct sunxi_pinctrl_group *grp = 376 sunxi_pinctrl_find_group_by_name(pctl, group); 377 378 if (!grp) { 379 dev_err(pctl->dev, "unknown pin %s", group); 380 continue; 381 } 382 383 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 384 grp->name, 385 function)) { 386 dev_err(pctl->dev, "unsupported function %s on pin %s", 387 function, group); 388 continue; 389 } 390 391 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 392 (*map)[i].data.mux.group = group; 393 (*map)[i].data.mux.function = function; 394 395 i++; 396 397 if (pinconfig) { 398 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 399 (*map)[i].data.configs.group_or_pin = group; 400 (*map)[i].data.configs.configs = pinconfig; 401 (*map)[i].data.configs.num_configs = configlen; 402 i++; 403 } 404 } 405 406 *num_maps = i; 407 408 /* 409 * We know have the number of maps we need, we can resize our 410 * map array 411 */ 412 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 413 if (!*map) 414 return -ENOMEM; 415 416 return 0; 417 418err_free_map: 419 kfree(*map); 420 *map = NULL; 421 return ret; 422} 423 424static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 425 struct pinctrl_map *map, 426 unsigned num_maps) 427{ 428 int i; 429 430 /* pin config is never in the first map */ 431 for (i = 1; i < num_maps; i++) { 432 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 433 continue; 434 435 /* 436 * All the maps share the same pin config, 437 * free only the first one we find. 438 */ 439 kfree(map[i].data.configs.configs); 440 break; 441 } 442 443 kfree(map); 444} 445 446static const struct pinctrl_ops sunxi_pctrl_ops = { 447 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 448 .dt_free_map = sunxi_pctrl_dt_free_map, 449 .get_groups_count = sunxi_pctrl_get_groups_count, 450 .get_group_name = sunxi_pctrl_get_group_name, 451 .get_group_pins = sunxi_pctrl_get_group_pins, 452}; 453 454static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param, 455 u32 *offset, u32 *shift, u32 *mask) 456{ 457 switch (param) { 458 case PIN_CONFIG_DRIVE_STRENGTH: 459 *offset = sunxi_dlevel_reg(pin); 460 *shift = sunxi_dlevel_offset(pin); 461 *mask = DLEVEL_PINS_MASK; 462 break; 463 464 case PIN_CONFIG_BIAS_PULL_UP: 465 case PIN_CONFIG_BIAS_PULL_DOWN: 466 case PIN_CONFIG_BIAS_DISABLE: 467 *offset = sunxi_pull_reg(pin); 468 *shift = sunxi_pull_offset(pin); 469 *mask = PULL_PINS_MASK; 470 break; 471 472 default: 473 return -ENOTSUPP; 474 } 475 476 return 0; 477} 478 479static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 480 unsigned long *config) 481{ 482 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 483 enum pin_config_param param = pinconf_to_config_param(*config); 484 u32 offset, shift, mask, val; 485 u16 arg; 486 int ret; 487 488 pin -= pctl->desc->pin_base; 489 490 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 491 if (ret < 0) 492 return ret; 493 494 val = (readl(pctl->membase + offset) >> shift) & mask; 495 496 switch (pinconf_to_config_param(*config)) { 497 case PIN_CONFIG_DRIVE_STRENGTH: 498 arg = (val + 1) * 10; 499 break; 500 501 case PIN_CONFIG_BIAS_PULL_UP: 502 if (val != SUN4I_PINCTRL_PULL_UP) 503 return -EINVAL; 504 arg = 1; /* hardware is weak pull-up */ 505 break; 506 507 case PIN_CONFIG_BIAS_PULL_DOWN: 508 if (val != SUN4I_PINCTRL_PULL_DOWN) 509 return -EINVAL; 510 arg = 1; /* hardware is weak pull-down */ 511 break; 512 513 case PIN_CONFIG_BIAS_DISABLE: 514 if (val != SUN4I_PINCTRL_NO_PULL) 515 return -EINVAL; 516 arg = 0; 517 break; 518 519 default: 520 /* sunxi_pconf_reg should catch anything unsupported */ 521 WARN_ON(1); 522 return -ENOTSUPP; 523 } 524 525 *config = pinconf_to_config_packed(param, arg); 526 527 return 0; 528} 529 530static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 531 unsigned group, 532 unsigned long *config) 533{ 534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 535 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 536 537 /* We only support 1 pin per group. Chain it to the pin callback */ 538 return sunxi_pconf_get(pctldev, g->pin, config); 539} 540 541static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, 542 unsigned long *configs, unsigned num_configs) 543{ 544 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 545 int i; 546 547 pin -= pctl->desc->pin_base; 548 549 for (i = 0; i < num_configs; i++) { 550 enum pin_config_param param; 551 unsigned long flags; 552 u32 offset, shift, mask, reg; 553 u32 arg, val; 554 int ret; 555 556 param = pinconf_to_config_param(configs[i]); 557 arg = pinconf_to_config_argument(configs[i]); 558 559 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); 560 if (ret < 0) 561 return ret; 562 563 switch (param) { 564 case PIN_CONFIG_DRIVE_STRENGTH: 565 if (arg < 10 || arg > 40) 566 return -EINVAL; 567 /* 568 * We convert from mA to what the register expects: 569 * 0: 10mA 570 * 1: 20mA 571 * 2: 30mA 572 * 3: 40mA 573 */ 574 val = arg / 10 - 1; 575 break; 576 case PIN_CONFIG_BIAS_DISABLE: 577 val = 0; 578 break; 579 case PIN_CONFIG_BIAS_PULL_UP: 580 if (arg == 0) 581 return -EINVAL; 582 val = 1; 583 break; 584 case PIN_CONFIG_BIAS_PULL_DOWN: 585 if (arg == 0) 586 return -EINVAL; 587 val = 2; 588 break; 589 default: 590 /* sunxi_pconf_reg should catch anything unsupported */ 591 WARN_ON(1); 592 return -ENOTSUPP; 593 } 594 595 raw_spin_lock_irqsave(&pctl->lock, flags); 596 reg = readl(pctl->membase + offset); 597 reg &= ~(mask << shift); 598 writel(reg | val << shift, pctl->membase + offset); 599 raw_spin_unlock_irqrestore(&pctl->lock, flags); 600 } /* for each config */ 601 602 return 0; 603} 604 605static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 606 unsigned long *configs, unsigned num_configs) 607{ 608 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 609 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 610 611 /* We only support 1 pin per group. Chain it to the pin callback */ 612 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); 613} 614 615static const struct pinconf_ops sunxi_pconf_ops = { 616 .is_generic = true, 617 .pin_config_get = sunxi_pconf_get, 618 .pin_config_set = sunxi_pconf_set, 619 .pin_config_group_get = sunxi_pconf_group_get, 620 .pin_config_group_set = sunxi_pconf_group_set, 621}; 622 623static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 624 unsigned pin, 625 struct regulator *supply) 626{ 627 unsigned short bank; 628 unsigned long flags; 629 u32 val, reg; 630 int uV; 631 632 if (!pctl->desc->io_bias_cfg_variant) 633 return 0; 634 635 uV = regulator_get_voltage(supply); 636 if (uV < 0) 637 return uV; 638 639 /* Might be dummy regulator with no voltage set */ 640 if (uV == 0) 641 return 0; 642 643 pin -= pctl->desc->pin_base; 644 bank = pin / PINS_PER_BANK; 645 646 switch (pctl->desc->io_bias_cfg_variant) { 647 case BIAS_VOLTAGE_GRP_CONFIG: 648 /* 649 * Configured value must be equal or greater to actual 650 * voltage. 651 */ 652 if (uV <= 1800000) 653 val = 0x0; /* 1.8V */ 654 else if (uV <= 2500000) 655 val = 0x6; /* 2.5V */ 656 else if (uV <= 2800000) 657 val = 0x9; /* 2.8V */ 658 else if (uV <= 3000000) 659 val = 0xA; /* 3.0V */ 660 else 661 val = 0xD; /* 3.3V */ 662 663 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 664 reg &= ~IO_BIAS_MASK; 665 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 666 return 0; 667 case BIAS_VOLTAGE_PIO_POW_MODE_SEL: 668 val = uV <= 1800000 ? 1 : 0; 669 670 raw_spin_lock_irqsave(&pctl->lock, flags); 671 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); 672 reg &= ~(1 << bank); 673 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); 674 raw_spin_unlock_irqrestore(&pctl->lock, flags); 675 return 0; 676 default: 677 return -EINVAL; 678 } 679} 680 681static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 682{ 683 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 684 685 return pctl->nfunctions; 686} 687 688static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 689 unsigned function) 690{ 691 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 692 693 return pctl->functions[function].name; 694} 695 696static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 697 unsigned function, 698 const char * const **groups, 699 unsigned * const num_groups) 700{ 701 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 702 703 *groups = pctl->functions[function].groups; 704 *num_groups = pctl->functions[function].ngroups; 705 706 return 0; 707} 708 709static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 710 unsigned pin, 711 u8 config) 712{ 713 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 714 unsigned long flags; 715 u32 val, mask; 716 717 raw_spin_lock_irqsave(&pctl->lock, flags); 718 719 pin -= pctl->desc->pin_base; 720 val = readl(pctl->membase + sunxi_mux_reg(pin)); 721 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 722 writel((val & ~mask) | config << sunxi_mux_offset(pin), 723 pctl->membase + sunxi_mux_reg(pin)); 724 725 raw_spin_unlock_irqrestore(&pctl->lock, flags); 726} 727 728static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 729 unsigned function, 730 unsigned group) 731{ 732 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 733 struct sunxi_pinctrl_group *g = pctl->groups + group; 734 struct sunxi_pinctrl_function *func = pctl->functions + function; 735 struct sunxi_desc_function *desc = 736 sunxi_pinctrl_desc_find_function_by_name(pctl, 737 g->name, 738 func->name); 739 740 if (!desc) 741 return -EINVAL; 742 743 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 744 745 return 0; 746} 747 748static int 749sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 750 struct pinctrl_gpio_range *range, 751 unsigned offset, 752 bool input) 753{ 754 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 755 struct sunxi_desc_function *desc; 756 const char *func; 757 758 if (input) 759 func = "gpio_in"; 760 else 761 func = "gpio_out"; 762 763 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 764 if (!desc) 765 return -EINVAL; 766 767 sunxi_pmx_set(pctldev, offset, desc->muxval); 768 769 return 0; 770} 771 772static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) 773{ 774 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 775 unsigned short bank = offset / PINS_PER_BANK; 776 unsigned short bank_offset = bank - pctl->desc->pin_base / 777 PINS_PER_BANK; 778 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 779 struct regulator *reg = s_reg->regulator; 780 char supply[16]; 781 int ret; 782 783 if (reg) { 784 refcount_inc(&s_reg->refcount); 785 return 0; 786 } 787 788 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); 789 reg = regulator_get(pctl->dev, supply); 790 if (IS_ERR(reg)) { 791 dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", 792 'A' + bank); 793 return PTR_ERR(reg); 794 } 795 796 ret = regulator_enable(reg); 797 if (ret) { 798 dev_err(pctl->dev, 799 "Couldn't enable bank P%c regulator\n", 'A' + bank); 800 goto out; 801 } 802 803 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); 804 805 s_reg->regulator = reg; 806 refcount_set(&s_reg->refcount, 1); 807 808 return 0; 809 810out: 811 regulator_put(s_reg->regulator); 812 813 return ret; 814} 815 816static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) 817{ 818 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 819 unsigned short bank = offset / PINS_PER_BANK; 820 unsigned short bank_offset = bank - pctl->desc->pin_base / 821 PINS_PER_BANK; 822 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 823 824 if (!refcount_dec_and_test(&s_reg->refcount)) 825 return 0; 826 827 regulator_disable(s_reg->regulator); 828 regulator_put(s_reg->regulator); 829 s_reg->regulator = NULL; 830 831 return 0; 832} 833 834static const struct pinmux_ops sunxi_pmx_ops = { 835 .get_functions_count = sunxi_pmx_get_funcs_cnt, 836 .get_function_name = sunxi_pmx_get_func_name, 837 .get_function_groups = sunxi_pmx_get_func_groups, 838 .set_mux = sunxi_pmx_set_mux, 839 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 840 .request = sunxi_pmx_request, 841 .free = sunxi_pmx_free, 842 .strict = true, 843}; 844 845static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 846 unsigned offset) 847{ 848 return pinctrl_gpio_direction_input(chip->base + offset); 849} 850 851static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 852{ 853 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 854 u32 reg = sunxi_data_reg(offset); 855 u8 index = sunxi_data_offset(offset); 856 bool set_mux = pctl->desc->irq_read_needs_mux && 857 gpiochip_line_is_irq(chip, offset); 858 u32 pin = offset + chip->base; 859 u32 val; 860 861 if (set_mux) 862 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 863 864 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 865 866 if (set_mux) 867 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 868 869 return !!val; 870} 871 872static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 873 unsigned offset, int value) 874{ 875 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 876 u32 reg = sunxi_data_reg(offset); 877 u8 index = sunxi_data_offset(offset); 878 unsigned long flags; 879 u32 regval; 880 881 raw_spin_lock_irqsave(&pctl->lock, flags); 882 883 regval = readl(pctl->membase + reg); 884 885 if (value) 886 regval |= BIT(index); 887 else 888 regval &= ~(BIT(index)); 889 890 writel(regval, pctl->membase + reg); 891 892 raw_spin_unlock_irqrestore(&pctl->lock, flags); 893} 894 895static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 896 unsigned offset, int value) 897{ 898 sunxi_pinctrl_gpio_set(chip, offset, value); 899 return pinctrl_gpio_direction_output(chip->base + offset); 900} 901 902static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 903 const struct of_phandle_args *gpiospec, 904 u32 *flags) 905{ 906 int pin, base; 907 908 base = PINS_PER_BANK * gpiospec->args[0]; 909 pin = base + gpiospec->args[1]; 910 911 if (pin > gc->ngpio) 912 return -EINVAL; 913 914 if (flags) 915 *flags = gpiospec->args[2]; 916 917 return pin; 918} 919 920static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 921{ 922 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 923 struct sunxi_desc_function *desc; 924 unsigned pinnum = pctl->desc->pin_base + offset; 925 unsigned irqnum; 926 927 if (offset >= chip->ngpio) 928 return -ENXIO; 929 930 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 931 if (!desc) 932 return -EINVAL; 933 934 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 935 936 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 937 chip->label, offset + chip->base, irqnum); 938 939 return irq_find_mapping(pctl->domain, irqnum); 940} 941 942static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 943{ 944 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 945 struct sunxi_desc_function *func; 946 int ret; 947 948 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 949 pctl->irq_array[d->hwirq], "irq"); 950 if (!func) 951 return -EINVAL; 952 953 ret = gpiochip_lock_as_irq(pctl->chip, 954 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 955 if (ret) { 956 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 957 irqd_to_hwirq(d)); 958 return ret; 959 } 960 961 /* Change muxing to INT mode */ 962 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 963 964 return 0; 965} 966 967static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 968{ 969 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 970 971 gpiochip_unlock_as_irq(pctl->chip, 972 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 973} 974 975static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 976{ 977 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 978 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 979 u8 index = sunxi_irq_cfg_offset(d->hwirq); 980 unsigned long flags; 981 u32 regval; 982 u8 mode; 983 984 switch (type) { 985 case IRQ_TYPE_EDGE_RISING: 986 mode = IRQ_EDGE_RISING; 987 break; 988 case IRQ_TYPE_EDGE_FALLING: 989 mode = IRQ_EDGE_FALLING; 990 break; 991 case IRQ_TYPE_EDGE_BOTH: 992 mode = IRQ_EDGE_BOTH; 993 break; 994 case IRQ_TYPE_LEVEL_HIGH: 995 mode = IRQ_LEVEL_HIGH; 996 break; 997 case IRQ_TYPE_LEVEL_LOW: 998 mode = IRQ_LEVEL_LOW; 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 1004 raw_spin_lock_irqsave(&pctl->lock, flags); 1005 1006 if (type & IRQ_TYPE_LEVEL_MASK) 1007 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 1008 handle_fasteoi_irq, NULL); 1009 else 1010 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 1011 handle_edge_irq, NULL); 1012 1013 regval = readl(pctl->membase + reg); 1014 regval &= ~(IRQ_CFG_IRQ_MASK << index); 1015 writel(regval | (mode << index), pctl->membase + reg); 1016 1017 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1018 1019 return 0; 1020} 1021 1022static void sunxi_pinctrl_irq_ack(struct irq_data *d) 1023{ 1024 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1025 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 1026 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 1027 1028 /* Clear the IRQ */ 1029 writel(1 << status_idx, pctl->membase + status_reg); 1030} 1031 1032static void sunxi_pinctrl_irq_mask(struct irq_data *d) 1033{ 1034 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1035 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1036 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1037 unsigned long flags; 1038 u32 val; 1039 1040 raw_spin_lock_irqsave(&pctl->lock, flags); 1041 1042 /* Mask the IRQ */ 1043 val = readl(pctl->membase + reg); 1044 writel(val & ~(1 << idx), pctl->membase + reg); 1045 1046 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1047} 1048 1049static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 1050{ 1051 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1052 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1053 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1054 unsigned long flags; 1055 u32 val; 1056 1057 raw_spin_lock_irqsave(&pctl->lock, flags); 1058 1059 /* Unmask the IRQ */ 1060 val = readl(pctl->membase + reg); 1061 writel(val | (1 << idx), pctl->membase + reg); 1062 1063 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1064} 1065 1066static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 1067{ 1068 sunxi_pinctrl_irq_ack(d); 1069 sunxi_pinctrl_irq_unmask(d); 1070} 1071 1072static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on) 1073{ 1074 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1075 u8 bank = d->hwirq / IRQ_PER_BANK; 1076 1077 return irq_set_irq_wake(pctl->irq[bank], on); 1078} 1079 1080static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 1081 .name = "sunxi_pio_edge", 1082 .irq_ack = sunxi_pinctrl_irq_ack, 1083 .irq_mask = sunxi_pinctrl_irq_mask, 1084 .irq_unmask = sunxi_pinctrl_irq_unmask, 1085 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1086 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1087 .irq_set_type = sunxi_pinctrl_irq_set_type, 1088 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1089 .flags = IRQCHIP_MASK_ON_SUSPEND, 1090}; 1091 1092static struct irq_chip sunxi_pinctrl_level_irq_chip = { 1093 .name = "sunxi_pio_level", 1094 .irq_eoi = sunxi_pinctrl_irq_ack, 1095 .irq_mask = sunxi_pinctrl_irq_mask, 1096 .irq_unmask = sunxi_pinctrl_irq_unmask, 1097 /* Define irq_enable / disable to avoid spurious irqs for drivers 1098 * using these to suppress irqs while they clear the irq source */ 1099 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 1100 .irq_disable = sunxi_pinctrl_irq_mask, 1101 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1102 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1103 .irq_set_type = sunxi_pinctrl_irq_set_type, 1104 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1105 .flags = IRQCHIP_EOI_THREADED | 1106 IRQCHIP_MASK_ON_SUSPEND | 1107 IRQCHIP_EOI_IF_HANDLED, 1108}; 1109 1110static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 1111 struct device_node *node, 1112 const u32 *intspec, 1113 unsigned int intsize, 1114 unsigned long *out_hwirq, 1115 unsigned int *out_type) 1116{ 1117 struct sunxi_pinctrl *pctl = d->host_data; 1118 struct sunxi_desc_function *desc; 1119 int pin, base; 1120 1121 if (intsize < 3) 1122 return -EINVAL; 1123 1124 base = PINS_PER_BANK * intspec[0]; 1125 pin = pctl->desc->pin_base + base + intspec[1]; 1126 1127 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 1128 if (!desc) 1129 return -EINVAL; 1130 1131 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 1132 *out_type = intspec[2]; 1133 1134 return 0; 1135} 1136 1137static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 1138 .xlate = sunxi_pinctrl_irq_of_xlate, 1139}; 1140 1141static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 1142{ 1143 unsigned int irq = irq_desc_get_irq(desc); 1144 struct irq_chip *chip = irq_desc_get_chip(desc); 1145 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 1146 unsigned long bank, reg, val; 1147 1148 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 1149 if (irq == pctl->irq[bank]) 1150 break; 1151 1152 if (bank == pctl->desc->irq_banks) 1153 return; 1154 1155 chained_irq_enter(chip, desc); 1156 1157 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1158 val = readl(pctl->membase + reg); 1159 1160 if (val) { 1161 int irqoffset; 1162 1163 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 1164 int pin_irq = irq_find_mapping(pctl->domain, 1165 bank * IRQ_PER_BANK + irqoffset); 1166 generic_handle_irq(pin_irq); 1167 } 1168 } 1169 1170 chained_irq_exit(chip, desc); 1171} 1172 1173static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1174 const char *name) 1175{ 1176 struct sunxi_pinctrl_function *func = pctl->functions; 1177 1178 while (func->name) { 1179 /* function already there */ 1180 if (strcmp(func->name, name) == 0) { 1181 func->ngroups++; 1182 return -EEXIST; 1183 } 1184 func++; 1185 } 1186 1187 func->name = name; 1188 func->ngroups = 1; 1189 1190 pctl->nfunctions++; 1191 1192 return 0; 1193} 1194 1195static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1196{ 1197 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1198 void *ptr; 1199 int i; 1200 1201 /* 1202 * Allocate groups 1203 * 1204 * We assume that the number of groups is the number of pins 1205 * given in the data array. 1206 1207 * This will not always be true, since some pins might not be 1208 * available in the current variant, but fortunately for us, 1209 * this means that the number of pins is the maximum group 1210 * number we will ever see. 1211 */ 1212 pctl->groups = devm_kcalloc(&pdev->dev, 1213 pctl->desc->npins, sizeof(*pctl->groups), 1214 GFP_KERNEL); 1215 if (!pctl->groups) 1216 return -ENOMEM; 1217 1218 for (i = 0; i < pctl->desc->npins; i++) { 1219 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1220 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1221 1222 if (pin->variant && !(pctl->variant & pin->variant)) 1223 continue; 1224 1225 group->name = pin->pin.name; 1226 group->pin = pin->pin.number; 1227 1228 /* And now we count the actual number of pins / groups */ 1229 pctl->ngroups++; 1230 } 1231 1232 /* 1233 * We suppose that we won't have any more functions than pins, 1234 * we'll reallocate that later anyway 1235 */ 1236 pctl->functions = kcalloc(pctl->ngroups, 1237 sizeof(*pctl->functions), 1238 GFP_KERNEL); 1239 if (!pctl->functions) 1240 return -ENOMEM; 1241 1242 /* Count functions and their associated groups */ 1243 for (i = 0; i < pctl->desc->npins; i++) { 1244 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1245 struct sunxi_desc_function *func; 1246 1247 if (pin->variant && !(pctl->variant & pin->variant)) 1248 continue; 1249 1250 for (func = pin->functions; func->name; func++) { 1251 if (func->variant && !(pctl->variant & func->variant)) 1252 continue; 1253 1254 /* Create interrupt mapping while we're at it */ 1255 if (!strcmp(func->name, "irq")) { 1256 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1257 pctl->irq_array[irqnum] = pin->pin.number; 1258 } 1259 1260 sunxi_pinctrl_add_function(pctl, func->name); 1261 } 1262 } 1263 1264 /* And now allocated and fill the array for real */ 1265 ptr = krealloc(pctl->functions, 1266 pctl->nfunctions * sizeof(*pctl->functions), 1267 GFP_KERNEL); 1268 if (!ptr) { 1269 kfree(pctl->functions); 1270 pctl->functions = NULL; 1271 return -ENOMEM; 1272 } 1273 pctl->functions = ptr; 1274 1275 for (i = 0; i < pctl->desc->npins; i++) { 1276 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1277 struct sunxi_desc_function *func; 1278 1279 if (pin->variant && !(pctl->variant & pin->variant)) 1280 continue; 1281 1282 for (func = pin->functions; func->name; func++) { 1283 struct sunxi_pinctrl_function *func_item; 1284 const char **func_grp; 1285 1286 if (func->variant && !(pctl->variant & func->variant)) 1287 continue; 1288 1289 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1290 func->name); 1291 if (!func_item) { 1292 kfree(pctl->functions); 1293 return -EINVAL; 1294 } 1295 1296 if (!func_item->groups) { 1297 func_item->groups = 1298 devm_kcalloc(&pdev->dev, 1299 func_item->ngroups, 1300 sizeof(*func_item->groups), 1301 GFP_KERNEL); 1302 if (!func_item->groups) { 1303 kfree(pctl->functions); 1304 return -ENOMEM; 1305 } 1306 } 1307 1308 func_grp = func_item->groups; 1309 while (*func_grp) 1310 func_grp++; 1311 1312 *func_grp = pin->pin.name; 1313 } 1314 } 1315 1316 return 0; 1317} 1318 1319static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1320{ 1321 unsigned long clock = clk_get_rate(clk); 1322 unsigned int best_diff, best_div; 1323 int i; 1324 1325 best_diff = abs(freq - clock); 1326 best_div = 0; 1327 1328 for (i = 1; i < 8; i++) { 1329 int cur_diff = abs(freq - (clock >> i)); 1330 1331 if (cur_diff < best_diff) { 1332 best_diff = cur_diff; 1333 best_div = i; 1334 } 1335 } 1336 1337 *diff = best_diff; 1338 return best_div; 1339} 1340 1341static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1342 struct device_node *node) 1343{ 1344 unsigned int hosc_diff, losc_diff; 1345 unsigned int hosc_div, losc_div; 1346 struct clk *hosc, *losc; 1347 u8 div, src; 1348 int i, ret; 1349 1350 /* Deal with old DTs that didn't have the oscillators */ 1351 if (of_clk_get_parent_count(node) != 3) 1352 return 0; 1353 1354 /* If we don't have any setup, bail out */ 1355 if (!of_find_property(node, "input-debounce", NULL)) 1356 return 0; 1357 1358 losc = devm_clk_get(pctl->dev, "losc"); 1359 if (IS_ERR(losc)) 1360 return PTR_ERR(losc); 1361 1362 hosc = devm_clk_get(pctl->dev, "hosc"); 1363 if (IS_ERR(hosc)) 1364 return PTR_ERR(hosc); 1365 1366 for (i = 0; i < pctl->desc->irq_banks; i++) { 1367 unsigned long debounce_freq; 1368 u32 debounce; 1369 1370 ret = of_property_read_u32_index(node, "input-debounce", 1371 i, &debounce); 1372 if (ret) 1373 return ret; 1374 1375 if (!debounce) 1376 continue; 1377 1378 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1379 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1380 debounce_freq, 1381 &losc_diff); 1382 1383 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1384 debounce_freq, 1385 &hosc_diff); 1386 1387 if (hosc_diff < losc_diff) { 1388 div = hosc_div; 1389 src = 1; 1390 } else { 1391 div = losc_div; 1392 src = 0; 1393 } 1394 1395 writel(src | div << 4, 1396 pctl->membase + 1397 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1398 } 1399 1400 return 0; 1401} 1402 1403int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 1404 const struct sunxi_pinctrl_desc *desc, 1405 unsigned long variant) 1406{ 1407 struct device_node *node = pdev->dev.of_node; 1408 struct pinctrl_desc *pctrl_desc; 1409 struct pinctrl_pin_desc *pins; 1410 struct sunxi_pinctrl *pctl; 1411 struct pinmux_ops *pmxops; 1412 int i, ret, last_pin, pin_idx; 1413 struct clk *clk; 1414 1415 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1416 if (!pctl) 1417 return -ENOMEM; 1418 platform_set_drvdata(pdev, pctl); 1419 1420 raw_spin_lock_init(&pctl->lock); 1421 1422 pctl->membase = devm_platform_ioremap_resource(pdev, 0); 1423 if (IS_ERR(pctl->membase)) 1424 return PTR_ERR(pctl->membase); 1425 1426 pctl->dev = &pdev->dev; 1427 pctl->desc = desc; 1428 pctl->variant = variant; 1429 1430 pctl->irq_array = devm_kcalloc(&pdev->dev, 1431 IRQ_PER_BANK * pctl->desc->irq_banks, 1432 sizeof(*pctl->irq_array), 1433 GFP_KERNEL); 1434 if (!pctl->irq_array) 1435 return -ENOMEM; 1436 1437 ret = sunxi_pinctrl_build_state(pdev); 1438 if (ret) { 1439 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1440 return ret; 1441 } 1442 1443 pins = devm_kcalloc(&pdev->dev, 1444 pctl->desc->npins, sizeof(*pins), 1445 GFP_KERNEL); 1446 if (!pins) 1447 return -ENOMEM; 1448 1449 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1450 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1451 1452 if (pin->variant && !(pctl->variant & pin->variant)) 1453 continue; 1454 1455 pins[pin_idx++] = pin->pin; 1456 } 1457 1458 pctrl_desc = devm_kzalloc(&pdev->dev, 1459 sizeof(*pctrl_desc), 1460 GFP_KERNEL); 1461 if (!pctrl_desc) 1462 return -ENOMEM; 1463 1464 pctrl_desc->name = dev_name(&pdev->dev); 1465 pctrl_desc->owner = THIS_MODULE; 1466 pctrl_desc->pins = pins; 1467 pctrl_desc->npins = pctl->ngroups; 1468 pctrl_desc->confops = &sunxi_pconf_ops; 1469 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1470 1471 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1472 GFP_KERNEL); 1473 if (!pmxops) 1474 return -ENOMEM; 1475 1476 if (desc->disable_strict_mode) 1477 pmxops->strict = false; 1478 1479 pctrl_desc->pmxops = pmxops; 1480 1481 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1482 if (IS_ERR(pctl->pctl_dev)) { 1483 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1484 return PTR_ERR(pctl->pctl_dev); 1485 } 1486 1487 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1488 if (!pctl->chip) 1489 return -ENOMEM; 1490 1491 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1492 pctl->chip->owner = THIS_MODULE; 1493 pctl->chip->request = gpiochip_generic_request; 1494 pctl->chip->free = gpiochip_generic_free; 1495 pctl->chip->set_config = gpiochip_generic_config; 1496 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; 1497 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; 1498 pctl->chip->get = sunxi_pinctrl_gpio_get; 1499 pctl->chip->set = sunxi_pinctrl_gpio_set; 1500 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; 1501 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; 1502 pctl->chip->of_gpio_n_cells = 3; 1503 pctl->chip->can_sleep = false; 1504 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1505 pctl->desc->pin_base; 1506 pctl->chip->label = dev_name(&pdev->dev); 1507 pctl->chip->parent = &pdev->dev; 1508 pctl->chip->base = pctl->desc->pin_base; 1509 1510 ret = gpiochip_add_data(pctl->chip, pctl); 1511 if (ret) 1512 return ret; 1513 1514 for (i = 0; i < pctl->desc->npins; i++) { 1515 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1516 1517 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1518 pin->pin.number - pctl->desc->pin_base, 1519 pin->pin.number, 1); 1520 if (ret) 1521 goto gpiochip_error; 1522 } 1523 1524 ret = of_clk_get_parent_count(node); 1525 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1526 if (IS_ERR(clk)) { 1527 ret = PTR_ERR(clk); 1528 goto gpiochip_error; 1529 } 1530 1531 ret = clk_prepare_enable(clk); 1532 if (ret) 1533 goto gpiochip_error; 1534 1535 pctl->irq = devm_kcalloc(&pdev->dev, 1536 pctl->desc->irq_banks, 1537 sizeof(*pctl->irq), 1538 GFP_KERNEL); 1539 if (!pctl->irq) { 1540 ret = -ENOMEM; 1541 goto clk_error; 1542 } 1543 1544 for (i = 0; i < pctl->desc->irq_banks; i++) { 1545 pctl->irq[i] = platform_get_irq(pdev, i); 1546 if (pctl->irq[i] < 0) { 1547 ret = pctl->irq[i]; 1548 goto clk_error; 1549 } 1550 } 1551 1552 pctl->domain = irq_domain_add_linear(node, 1553 pctl->desc->irq_banks * IRQ_PER_BANK, 1554 &sunxi_pinctrl_irq_domain_ops, 1555 pctl); 1556 if (!pctl->domain) { 1557 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1558 ret = -ENOMEM; 1559 goto clk_error; 1560 } 1561 1562 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1563 int irqno = irq_create_mapping(pctl->domain, i); 1564 1565 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class, 1566 &sunxi_pinctrl_irq_request_class); 1567 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1568 handle_edge_irq); 1569 irq_set_chip_data(irqno, pctl); 1570 } 1571 1572 for (i = 0; i < pctl->desc->irq_banks; i++) { 1573 /* Mask and clear all IRQs before registering a handler */ 1574 writel(0, pctl->membase + 1575 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1576 writel(0xffffffff, 1577 pctl->membase + 1578 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1579 1580 irq_set_chained_handler_and_data(pctl->irq[i], 1581 sunxi_pinctrl_irq_handler, 1582 pctl); 1583 } 1584 1585 sunxi_pinctrl_setup_debounce(pctl, node); 1586 1587 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1588 1589 return 0; 1590 1591clk_error: 1592 clk_disable_unprepare(clk); 1593gpiochip_error: 1594 gpiochip_remove(pctl->chip); 1595 return ret; 1596} 1597