1/* 2 * Allwinner V3/V3s SoCs pinctrl driver. 3 * 4 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 5 * 6 * Based on pinctrl-sun8i-h3.c, which is: 7 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 8 * 9 * Based on pinctrl-sun8i-a23.c, which is: 10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> 11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> 12 * 13 * This file is licensed under the terms of the GNU General Public 14 * License version 2. This program is licensed "as is" without any 15 * warranty of any kind, whether express or implied. 16 */ 17 18#include <linux/module.h> 19#include <linux/platform_device.h> 20#include <linux/of.h> 21#include <linux/of_device.h> 22#include <linux/pinctrl/pinctrl.h> 23 24#include "pinctrl-sunxi.h" 25 26static const struct sunxi_desc_pin sun8i_v3s_pins[] = { 27 /* Hole */ 28 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 29 SUNXI_FUNCTION(0x0, "gpio_in"), 30 SUNXI_FUNCTION(0x1, "gpio_out"), 31 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 32 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ 33 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 34 SUNXI_FUNCTION(0x0, "gpio_in"), 35 SUNXI_FUNCTION(0x1, "gpio_out"), 36 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 37 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ 38 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 39 SUNXI_FUNCTION(0x0, "gpio_in"), 40 SUNXI_FUNCTION(0x1, "gpio_out"), 41 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 44 SUNXI_FUNCTION(0x0, "gpio_in"), 45 SUNXI_FUNCTION(0x1, "gpio_out"), 46 SUNXI_FUNCTION(0x2, "uart2"), /* D1 */ 47 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ 48 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 49 SUNXI_FUNCTION(0x0, "gpio_in"), 50 SUNXI_FUNCTION(0x1, "gpio_out"), 51 SUNXI_FUNCTION(0x2, "pwm0"), 52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ 53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 54 SUNXI_FUNCTION(0x0, "gpio_in"), 55 SUNXI_FUNCTION(0x1, "gpio_out"), 56 SUNXI_FUNCTION(0x2, "pwm1"), 57 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ 58 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 59 SUNXI_FUNCTION(0x0, "gpio_in"), 60 SUNXI_FUNCTION(0x1, "gpio_out"), 61 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ 62 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ 63 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 64 SUNXI_FUNCTION(0x0, "gpio_in"), 65 SUNXI_FUNCTION(0x1, "gpio_out"), 66 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ 67 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ 68 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), 69 SUNXI_FUNCTION(0x0, "gpio_in"), 70 SUNXI_FUNCTION(0x1, "gpio_out"), 71 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ 72 SUNXI_FUNCTION(0x3, "uart0"), /* TX */ 73 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ 74 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), 75 SUNXI_FUNCTION(0x0, "gpio_in"), 76 SUNXI_FUNCTION(0x1, "gpio_out"), 77 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ 78 SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 79 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ 80 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), 81 PINCTRL_SUN8I_V3, 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION(0x2, "jtag"), /* MS */ 85 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ 86 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), 87 PINCTRL_SUN8I_V3, 88 SUNXI_FUNCTION(0x0, "gpio_in"), 89 SUNXI_FUNCTION(0x1, "gpio_out"), 90 SUNXI_FUNCTION(0x2, "jtag"), /* CK */ 91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ 92 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), 93 PINCTRL_SUN8I_V3, 94 SUNXI_FUNCTION(0x0, "gpio_in"), 95 SUNXI_FUNCTION(0x1, "gpio_out"), 96 SUNXI_FUNCTION(0x2, "jtag"), /* DO */ 97 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ 98 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), 99 PINCTRL_SUN8I_V3, 100 SUNXI_FUNCTION(0x0, "gpio_in"), 101 SUNXI_FUNCTION(0x1, "gpio_out"), 102 SUNXI_FUNCTION(0x2, "jtag"), /* DI */ 103 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ 104 /* Hole */ 105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 106 SUNXI_FUNCTION(0x0, "gpio_in"), 107 SUNXI_FUNCTION(0x1, "gpio_out"), 108 SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */ 109 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 111 SUNXI_FUNCTION(0x0, "gpio_in"), 112 SUNXI_FUNCTION(0x1, "gpio_out"), 113 SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */ 114 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 115 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 116 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x1, "gpio_out"), 118 SUNXI_FUNCTION(0x2, "mmc2"), /* RST */ 119 SUNXI_FUNCTION(0x3, "spi0")), /* CS */ 120 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 121 SUNXI_FUNCTION(0x0, "gpio_in"), 122 SUNXI_FUNCTION(0x1, "gpio_out"), 123 SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ 124 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 125 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), 126 PINCTRL_SUN8I_V3, 127 SUNXI_FUNCTION(0x0, "gpio_in"), 128 SUNXI_FUNCTION(0x1, "gpio_out"), 129 SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ 130 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), 131 PINCTRL_SUN8I_V3, 132 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ 135 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), 136 PINCTRL_SUN8I_V3, 137 SUNXI_FUNCTION(0x0, "gpio_in"), 138 SUNXI_FUNCTION(0x1, "gpio_out"), 139 SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ 140 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), 141 PINCTRL_SUN8I_V3, 142 SUNXI_FUNCTION(0x0, "gpio_in"), 143 SUNXI_FUNCTION(0x1, "gpio_out"), 144 SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ 145 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), 146 PINCTRL_SUN8I_V3, 147 SUNXI_FUNCTION(0x0, "gpio_in"), 148 SUNXI_FUNCTION(0x1, "gpio_out"), 149 SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ 150 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), 151 PINCTRL_SUN8I_V3, 152 SUNXI_FUNCTION(0x0, "gpio_in"), 153 SUNXI_FUNCTION(0x1, "gpio_out"), 154 SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ 155 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), 156 PINCTRL_SUN8I_V3, 157 SUNXI_FUNCTION(0x0, "gpio_in"), 158 SUNXI_FUNCTION(0x1, "gpio_out"), 159 SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ 160 /* Hole */ 161 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), 162 PINCTRL_SUN8I_V3, 163 SUNXI_FUNCTION(0x0, "gpio_in"), 164 SUNXI_FUNCTION(0x1, "gpio_out"), 165 SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ 166 SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ 167 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), 168 PINCTRL_SUN8I_V3, 169 SUNXI_FUNCTION(0x0, "gpio_in"), 170 SUNXI_FUNCTION(0x1, "gpio_out"), 171 SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ 172 SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ 173 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), 174 PINCTRL_SUN8I_V3, 175 SUNXI_FUNCTION(0x0, "gpio_in"), 176 SUNXI_FUNCTION(0x1, "gpio_out"), 177 SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ 178 SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ 179 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), 180 PINCTRL_SUN8I_V3, 181 SUNXI_FUNCTION(0x0, "gpio_in"), 182 SUNXI_FUNCTION(0x1, "gpio_out"), 183 SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ 184 SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ 185 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), 186 PINCTRL_SUN8I_V3, 187 SUNXI_FUNCTION(0x0, "gpio_in"), 188 SUNXI_FUNCTION(0x1, "gpio_out"), 189 SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ 190 SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ 191 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), 192 PINCTRL_SUN8I_V3, 193 SUNXI_FUNCTION(0x0, "gpio_in"), 194 SUNXI_FUNCTION(0x1, "gpio_out"), 195 SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ 196 SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ 197 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), 198 PINCTRL_SUN8I_V3, 199 SUNXI_FUNCTION(0x0, "gpio_in"), 200 SUNXI_FUNCTION(0x1, "gpio_out"), 201 SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ 202 SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ 203 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), 204 PINCTRL_SUN8I_V3, 205 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ 208 SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ 209 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), 210 PINCTRL_SUN8I_V3, 211 SUNXI_FUNCTION(0x0, "gpio_in"), 212 SUNXI_FUNCTION(0x1, "gpio_out"), 213 SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ 214 SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ 215 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), 216 PINCTRL_SUN8I_V3, 217 SUNXI_FUNCTION(0x0, "gpio_in"), 218 SUNXI_FUNCTION(0x1, "gpio_out"), 219 SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ 220 SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ 221 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), 222 PINCTRL_SUN8I_V3, 223 SUNXI_FUNCTION(0x0, "gpio_in"), 224 SUNXI_FUNCTION(0x1, "gpio_out"), 225 SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ 226 SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ 227 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), 228 PINCTRL_SUN8I_V3, 229 SUNXI_FUNCTION(0x0, "gpio_in"), 230 SUNXI_FUNCTION(0x1, "gpio_out"), 231 SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ 232 SUNXI_FUNCTION(0x4, "emac")), /* CRS */ 233 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), 234 PINCTRL_SUN8I_V3, 235 SUNXI_FUNCTION(0x0, "gpio_in"), 236 SUNXI_FUNCTION(0x1, "gpio_out"), 237 SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ 238 SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */ 239 SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ 240 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), 241 PINCTRL_SUN8I_V3, 242 SUNXI_FUNCTION(0x0, "gpio_in"), 243 SUNXI_FUNCTION(0x1, "gpio_out"), 244 SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ 245 SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */ 246 SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ 247 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), 248 PINCTRL_SUN8I_V3, 249 SUNXI_FUNCTION(0x0, "gpio_in"), 250 SUNXI_FUNCTION(0x1, "gpio_out"), 251 SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ 252 SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */ 253 SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ 254 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), 255 PINCTRL_SUN8I_V3, 256 SUNXI_FUNCTION(0x0, "gpio_in"), 257 SUNXI_FUNCTION(0x1, "gpio_out"), 258 SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ 259 SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */ 260 SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ 261 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), 262 PINCTRL_SUN8I_V3, 263 SUNXI_FUNCTION(0x0, "gpio_in"), 264 SUNXI_FUNCTION(0x1, "gpio_out"), 265 SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ 266 SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */ 267 SUNXI_FUNCTION(0x4, "emac")), /* MDC */ 268 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), 269 PINCTRL_SUN8I_V3, 270 SUNXI_FUNCTION(0x0, "gpio_in"), 271 SUNXI_FUNCTION(0x1, "gpio_out"), 272 SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ 273 SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */ 274 SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ 275 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), 276 PINCTRL_SUN8I_V3, 277 SUNXI_FUNCTION(0x0, "gpio_in"), 278 SUNXI_FUNCTION(0x1, "gpio_out"), 279 SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ 280 SUNXI_FUNCTION(0x3, "lvds")), /* VPC */ 281 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), 282 PINCTRL_SUN8I_V3, 283 SUNXI_FUNCTION(0x0, "gpio_in"), 284 SUNXI_FUNCTION(0x1, "gpio_out"), 285 SUNXI_FUNCTION(0x2, "lcd"), /* DE */ 286 SUNXI_FUNCTION(0x3, "lvds")), /* VNC */ 287 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), 288 PINCTRL_SUN8I_V3, 289 SUNXI_FUNCTION(0x0, "gpio_in"), 290 SUNXI_FUNCTION(0x1, "gpio_out"), 291 SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ 292 SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */ 293 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), 294 PINCTRL_SUN8I_V3, 295 SUNXI_FUNCTION(0x0, "gpio_in"), 296 SUNXI_FUNCTION(0x1, "gpio_out"), 297 SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ 298 SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */ 299 /* Hole */ 300 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 301 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x1, "gpio_out"), 303 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 304 SUNXI_FUNCTION(0x3, "lcd")), /* CLK */ 305 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 306 SUNXI_FUNCTION(0x0, "gpio_in"), 307 SUNXI_FUNCTION(0x1, "gpio_out"), 308 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 309 SUNXI_FUNCTION(0x3, "lcd")), /* DE */ 310 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 311 SUNXI_FUNCTION(0x0, "gpio_in"), 312 SUNXI_FUNCTION(0x1, "gpio_out"), 313 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 314 SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */ 315 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 316 SUNXI_FUNCTION(0x0, "gpio_in"), 317 SUNXI_FUNCTION(0x1, "gpio_out"), 318 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 319 SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */ 320 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 321 SUNXI_FUNCTION(0x0, "gpio_in"), 322 SUNXI_FUNCTION(0x1, "gpio_out"), 323 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 324 SUNXI_FUNCTION(0x3, "lcd")), /* D2 */ 325 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 326 SUNXI_FUNCTION(0x0, "gpio_in"), 327 SUNXI_FUNCTION(0x1, "gpio_out"), 328 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 329 SUNXI_FUNCTION(0x3, "lcd")), /* D3 */ 330 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 331 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x1, "gpio_out"), 333 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 334 SUNXI_FUNCTION(0x3, "lcd")), /* D4 */ 335 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 336 SUNXI_FUNCTION(0x0, "gpio_in"), 337 SUNXI_FUNCTION(0x1, "gpio_out"), 338 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 339 SUNXI_FUNCTION(0x3, "lcd")), /* D5 */ 340 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 341 SUNXI_FUNCTION(0x0, "gpio_in"), 342 SUNXI_FUNCTION(0x1, "gpio_out"), 343 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 344 SUNXI_FUNCTION(0x3, "lcd")), /* D6 */ 345 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 346 SUNXI_FUNCTION(0x0, "gpio_in"), 347 SUNXI_FUNCTION(0x1, "gpio_out"), 348 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 349 SUNXI_FUNCTION(0x3, "lcd")), /* D7 */ 350 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 351 SUNXI_FUNCTION(0x0, "gpio_in"), 352 SUNXI_FUNCTION(0x1, "gpio_out"), 353 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 354 SUNXI_FUNCTION(0x3, "lcd")), /* D10 */ 355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 356 SUNXI_FUNCTION(0x0, "gpio_in"), 357 SUNXI_FUNCTION(0x1, "gpio_out"), 358 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 359 SUNXI_FUNCTION(0x3, "lcd")), /* D11 */ 360 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 361 SUNXI_FUNCTION(0x0, "gpio_in"), 362 SUNXI_FUNCTION(0x1, "gpio_out"), 363 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 364 SUNXI_FUNCTION(0x3, "lcd")), /* D12 */ 365 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 366 SUNXI_FUNCTION(0x0, "gpio_in"), 367 SUNXI_FUNCTION(0x1, "gpio_out"), 368 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 369 SUNXI_FUNCTION(0x3, "lcd")), /* D13 */ 370 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 371 SUNXI_FUNCTION(0x0, "gpio_in"), 372 SUNXI_FUNCTION(0x1, "gpio_out"), 373 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 374 SUNXI_FUNCTION(0x3, "lcd")), /* D14 */ 375 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 376 SUNXI_FUNCTION(0x0, "gpio_in"), 377 SUNXI_FUNCTION(0x1, "gpio_out"), 378 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 379 SUNXI_FUNCTION(0x3, "lcd")), /* D15 */ 380 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 381 SUNXI_FUNCTION(0x0, "gpio_in"), 382 SUNXI_FUNCTION(0x1, "gpio_out"), 383 SUNXI_FUNCTION(0x2, "csi"), /* D12 */ 384 SUNXI_FUNCTION(0x3, "lcd")), /* D18 */ 385 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), 386 SUNXI_FUNCTION(0x0, "gpio_in"), 387 SUNXI_FUNCTION(0x1, "gpio_out"), 388 SUNXI_FUNCTION(0x2, "csi"), /* D13 */ 389 SUNXI_FUNCTION(0x3, "lcd")), /* D19 */ 390 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), 391 SUNXI_FUNCTION(0x0, "gpio_in"), 392 SUNXI_FUNCTION(0x1, "gpio_out"), 393 SUNXI_FUNCTION(0x2, "csi"), /* D14 */ 394 SUNXI_FUNCTION(0x3, "lcd")), /* D20 */ 395 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), 396 SUNXI_FUNCTION(0x0, "gpio_in"), 397 SUNXI_FUNCTION(0x1, "gpio_out"), 398 SUNXI_FUNCTION(0x2, "csi"), /* D15 */ 399 SUNXI_FUNCTION(0x3, "lcd")), /* D21 */ 400 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), 401 SUNXI_FUNCTION(0x0, "gpio_in"), 402 SUNXI_FUNCTION(0x1, "gpio_out"), 403 SUNXI_FUNCTION(0x2, "csi"), /* FIELD */ 404 SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */ 405 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), 406 SUNXI_FUNCTION(0x0, "gpio_in"), 407 SUNXI_FUNCTION(0x1, "gpio_out"), 408 SUNXI_FUNCTION(0x2, "csi"), /* SCK */ 409 SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ 410 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 411 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), 412 SUNXI_FUNCTION(0x0, "gpio_in"), 413 SUNXI_FUNCTION(0x1, "gpio_out"), 414 SUNXI_FUNCTION(0x2, "csi"), /* SDA */ 415 SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ 416 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 417 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23), 418 SUNXI_FUNCTION(0x0, "gpio_in"), 419 SUNXI_FUNCTION(0x1, "gpio_out"), 420 SUNXI_FUNCTION(0x3, "lcd"), /* D22 */ 421 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 422 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24), 423 SUNXI_FUNCTION(0x0, "gpio_in"), 424 SUNXI_FUNCTION(0x1, "gpio_out"), 425 SUNXI_FUNCTION(0x3, "lcd"), /* D23 */ 426 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 427 /* Hole */ 428 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 429 SUNXI_FUNCTION(0x0, "gpio_in"), 430 SUNXI_FUNCTION(0x1, "gpio_out"), 431 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 432 SUNXI_FUNCTION(0x3, "jtag")), /* MS */ 433 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 434 SUNXI_FUNCTION(0x0, "gpio_in"), 435 SUNXI_FUNCTION(0x1, "gpio_out"), 436 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 437 SUNXI_FUNCTION(0x3, "jtag")), /* DI */ 438 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 439 SUNXI_FUNCTION(0x0, "gpio_in"), 440 SUNXI_FUNCTION(0x1, "gpio_out"), 441 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 442 SUNXI_FUNCTION(0x3, "uart0")), /* TX */ 443 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 444 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x1, "gpio_out"), 446 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 447 SUNXI_FUNCTION(0x3, "jtag")), /* DO */ 448 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 449 SUNXI_FUNCTION(0x0, "gpio_in"), 450 SUNXI_FUNCTION(0x1, "gpio_out"), 451 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 452 SUNXI_FUNCTION(0x3, "uart0")), /* RX */ 453 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 454 SUNXI_FUNCTION(0x0, "gpio_in"), 455 SUNXI_FUNCTION(0x1, "gpio_out"), 456 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 457 SUNXI_FUNCTION(0x3, "jtag")), /* CK */ 458 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 459 SUNXI_FUNCTION(0x0, "gpio_in"), 460 SUNXI_FUNCTION(0x1, "gpio_out")), 461 /* Hole */ 462 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 463 SUNXI_FUNCTION(0x0, "gpio_in"), 464 SUNXI_FUNCTION(0x1, "gpio_out"), 465 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 466 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ 467 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 468 SUNXI_FUNCTION(0x0, "gpio_in"), 469 SUNXI_FUNCTION(0x1, "gpio_out"), 470 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 471 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ 472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 473 SUNXI_FUNCTION(0x0, "gpio_in"), 474 SUNXI_FUNCTION(0x1, "gpio_out"), 475 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 476 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ 477 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 478 SUNXI_FUNCTION(0x0, "gpio_in"), 479 SUNXI_FUNCTION(0x1, "gpio_out"), 480 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 481 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ 482 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 483 SUNXI_FUNCTION(0x0, "gpio_in"), 484 SUNXI_FUNCTION(0x1, "gpio_out"), 485 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 486 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ 487 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 488 SUNXI_FUNCTION(0x0, "gpio_in"), 489 SUNXI_FUNCTION(0x1, "gpio_out"), 490 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 491 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ 492 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), 493 PINCTRL_SUN8I_V3, 494 SUNXI_FUNCTION(0x0, "gpio_in"), 495 SUNXI_FUNCTION(0x1, "gpio_out"), 496 SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 497 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ 498 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), 499 PINCTRL_SUN8I_V3, 500 SUNXI_FUNCTION(0x0, "gpio_in"), 501 SUNXI_FUNCTION(0x1, "gpio_out"), 502 SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 503 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ 504 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), 505 PINCTRL_SUN8I_V3, 506 SUNXI_FUNCTION(0x0, "gpio_in"), 507 SUNXI_FUNCTION(0x1, "gpio_out"), 508 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 509 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ 510 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), 511 PINCTRL_SUN8I_V3, 512 SUNXI_FUNCTION(0x0, "gpio_in"), 513 SUNXI_FUNCTION(0x1, "gpio_out"), 514 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 515 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ 516 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), 517 PINCTRL_SUN8I_V3, 518 SUNXI_FUNCTION(0x0, "gpio_in"), 519 SUNXI_FUNCTION(0x1, "gpio_out"), 520 SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ 521 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ 522 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), 523 PINCTRL_SUN8I_V3, 524 SUNXI_FUNCTION(0x0, "gpio_in"), 525 SUNXI_FUNCTION(0x1, "gpio_out"), 526 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 527 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ 528 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), 529 PINCTRL_SUN8I_V3, 530 SUNXI_FUNCTION(0x0, "gpio_in"), 531 SUNXI_FUNCTION(0x1, "gpio_out"), 532 SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ 533 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ 534 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), 535 PINCTRL_SUN8I_V3, 536 SUNXI_FUNCTION(0x0, "gpio_in"), 537 SUNXI_FUNCTION(0x1, "gpio_out"), 538 SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ 539 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ 540}; 541 542static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; 543 544static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { 545 .pins = sun8i_v3s_pins, 546 .npins = ARRAY_SIZE(sun8i_v3s_pins), 547 .irq_banks = 2, 548 .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, 549 .irq_read_needs_mux = true 550}; 551 552static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) 553{ 554 unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); 555 556 return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data, 557 variant); 558} 559 560static const struct of_device_id sun8i_v3s_pinctrl_match[] = { 561 { 562 .compatible = "allwinner,sun8i-v3-pinctrl", 563 .data = (void *)PINCTRL_SUN8I_V3 564 }, 565 { 566 .compatible = "allwinner,sun8i-v3s-pinctrl", 567 .data = (void *)PINCTRL_SUN8I_V3S 568 }, 569 { }, 570}; 571 572static struct platform_driver sun8i_v3s_pinctrl_driver = { 573 .probe = sun8i_v3s_pinctrl_probe, 574 .driver = { 575 .name = "sun8i-v3s-pinctrl", 576 .of_match_table = sun8i_v3s_pinctrl_match, 577 }, 578}; 579builtin_platform_driver(sun8i_v3s_pinctrl_driver); 580