1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9#include <linux/clk.h> 10#include <linux/gpio/driver.h> 11#include <linux/hwspinlock.h> 12#include <linux/io.h> 13#include <linux/irq.h> 14#include <linux/mfd/syscon.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/of_address.h> 18#include <linux/of_device.h> 19#include <linux/of_irq.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/pinconf-generic.h> 24#include <linux/pinctrl/pinctrl.h> 25#include <linux/pinctrl/pinmux.h> 26#include <linux/platform_device.h> 27#include <linux/regmap.h> 28#include <linux/reset.h> 29#include <linux/slab.h> 30 31#include "../core.h" 32#include "../pinconf.h" 33#include "../pinctrl-utils.h" 34#include "pinctrl-stm32.h" 35 36#define STM32_GPIO_MODER 0x00 37#define STM32_GPIO_TYPER 0x04 38#define STM32_GPIO_SPEEDR 0x08 39#define STM32_GPIO_PUPDR 0x0c 40#define STM32_GPIO_IDR 0x10 41#define STM32_GPIO_ODR 0x14 42#define STM32_GPIO_BSRR 0x18 43#define STM32_GPIO_LCKR 0x1c 44#define STM32_GPIO_AFRL 0x20 45#define STM32_GPIO_AFRH 0x24 46 47/* custom bitfield to backup pin status */ 48#define STM32_GPIO_BKP_MODE_SHIFT 0 49#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 50#define STM32_GPIO_BKP_ALT_SHIFT 2 51#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 52#define STM32_GPIO_BKP_SPEED_SHIFT 6 53#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 54#define STM32_GPIO_BKP_PUPD_SHIFT 8 55#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 56#define STM32_GPIO_BKP_TYPE 10 57#define STM32_GPIO_BKP_VAL 11 58 59#define STM32_GPIO_PINS_PER_BANK 16 60#define STM32_GPIO_IRQ_LINE 16 61 62#define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 63 64#define gpio_range_to_bank(chip) \ 65 container_of(chip, struct stm32_gpio_bank, range) 66 67#define HWSPNLCK_TIMEOUT 1000 /* usec */ 68 69static const char * const stm32_gpio_functions[] = { 70 "gpio", "af0", "af1", 71 "af2", "af3", "af4", 72 "af5", "af6", "af7", 73 "af8", "af9", "af10", 74 "af11", "af12", "af13", 75 "af14", "af15", "analog", 76}; 77 78struct stm32_pinctrl_group { 79 const char *name; 80 unsigned long config; 81 unsigned pin; 82}; 83 84struct stm32_gpio_bank { 85 void __iomem *base; 86 struct clk *clk; 87 struct reset_control *rstc; 88 spinlock_t lock; 89 struct gpio_chip gpio_chip; 90 struct pinctrl_gpio_range range; 91 struct fwnode_handle *fwnode; 92 struct irq_domain *domain; 93 u32 bank_nr; 94 u32 bank_ioport_nr; 95 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 96 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 97}; 98 99struct stm32_pinctrl { 100 struct device *dev; 101 struct pinctrl_dev *pctl_dev; 102 struct pinctrl_desc pctl_desc; 103 struct stm32_pinctrl_group *groups; 104 unsigned ngroups; 105 const char **grp_names; 106 struct stm32_gpio_bank *banks; 107 unsigned nbanks; 108 const struct stm32_pinctrl_match_data *match_data; 109 struct irq_domain *domain; 110 struct regmap *regmap; 111 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 112 struct hwspinlock *hwlock; 113 struct stm32_desc_pin *pins; 114 u32 npins; 115 u32 pkg; 116 u16 irqmux_map; 117 spinlock_t irqmux_lock; 118}; 119 120static inline int stm32_gpio_pin(int gpio) 121{ 122 return gpio % STM32_GPIO_PINS_PER_BANK; 123} 124 125static inline u32 stm32_gpio_get_mode(u32 function) 126{ 127 switch (function) { 128 case STM32_PIN_GPIO: 129 return 0; 130 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 131 return 2; 132 case STM32_PIN_ANALOG: 133 return 3; 134 } 135 136 return 0; 137} 138 139static inline u32 stm32_gpio_get_alt(u32 function) 140{ 141 switch (function) { 142 case STM32_PIN_GPIO: 143 return 0; 144 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 145 return function - 1; 146 case STM32_PIN_ANALOG: 147 return 0; 148 } 149 150 return 0; 151} 152 153static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 154 u32 offset, u32 value) 155{ 156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 158} 159 160static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 161 u32 mode, u32 alt) 162{ 163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 164 STM32_GPIO_BKP_ALT_MASK); 165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 167} 168 169static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 170 u32 drive) 171{ 172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 174} 175 176static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 177 u32 speed) 178{ 179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 181} 182 183static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 184 u32 bias) 185{ 186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 188} 189 190/* GPIO functions */ 191 192static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 193 unsigned offset, int value) 194{ 195 stm32_gpio_backup_value(bank, offset, value); 196 197 if (!value) 198 offset += STM32_GPIO_PINS_PER_BANK; 199 200 clk_enable(bank->clk); 201 202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 203 204 clk_disable(bank->clk); 205} 206 207static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 208{ 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 211 struct pinctrl_gpio_range *range; 212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 213 214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 215 if (!range) { 216 dev_err(pctl->dev, "pin %d not in range.\n", pin); 217 return -EINVAL; 218 } 219 220 return pinctrl_gpio_request(chip->base + offset); 221} 222 223static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 224{ 225 pinctrl_gpio_free(chip->base + offset); 226} 227 228static int stm32_gpio_get_noclk(struct gpio_chip *chip, unsigned int offset) 229{ 230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 231 232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 233} 234 235static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 236{ 237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 238 int ret; 239 240 clk_enable(bank->clk); 241 242 ret = stm32_gpio_get_noclk(chip, offset); 243 244 clk_disable(bank->clk); 245 246 return ret; 247} 248 249static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 250{ 251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 252 253 __stm32_gpio_set(bank, offset, value); 254} 255 256static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 257{ 258 return pinctrl_gpio_direction_input(chip->base + offset); 259} 260 261static int stm32_gpio_direction_output(struct gpio_chip *chip, 262 unsigned offset, int value) 263{ 264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 265 266 __stm32_gpio_set(bank, offset, value); 267 pinctrl_gpio_direction_output(chip->base + offset); 268 269 return 0; 270} 271 272 273static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 274{ 275 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 276 struct irq_fwspec fwspec; 277 278 fwspec.fwnode = bank->fwnode; 279 fwspec.param_count = 2; 280 fwspec.param[0] = offset; 281 fwspec.param[1] = IRQ_TYPE_NONE; 282 283 return irq_create_fwspec_mapping(&fwspec); 284} 285 286static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 287{ 288 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 289 int pin = stm32_gpio_pin(offset); 290 int ret; 291 u32 mode, alt; 292 293 stm32_pmx_get_mode(bank, pin, &mode, &alt); 294 if ((alt == 0) && (mode == 0)) 295 ret = GPIO_LINE_DIRECTION_IN; 296 else if ((alt == 0) && (mode == 1)) 297 ret = GPIO_LINE_DIRECTION_OUT; 298 else 299 ret = -EINVAL; 300 301 return ret; 302} 303 304static const struct gpio_chip stm32_gpio_template = { 305 .request = stm32_gpio_request, 306 .free = stm32_gpio_free, 307 .get = stm32_gpio_get, 308 .set = stm32_gpio_set, 309 .direction_input = stm32_gpio_direction_input, 310 .direction_output = stm32_gpio_direction_output, 311 .to_irq = stm32_gpio_to_irq, 312 .get_direction = stm32_gpio_get_direction, 313 .set_config = gpiochip_generic_config, 314}; 315 316static void stm32_gpio_irq_trigger(struct irq_data *d) 317{ 318 struct stm32_gpio_bank *bank = d->domain->host_data; 319 int level; 320 321 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ 322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) 323 return; 324 325 /* If level interrupt type then retrig */ 326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq); 327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 329 irq_chip_retrigger_hierarchy(d); 330} 331 332static void stm32_gpio_irq_eoi(struct irq_data *d) 333{ 334 irq_chip_eoi_parent(d); 335 stm32_gpio_irq_trigger(d); 336}; 337 338static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 339{ 340 struct stm32_gpio_bank *bank = d->domain->host_data; 341 u32 parent_type; 342 343 switch (type) { 344 case IRQ_TYPE_EDGE_RISING: 345 case IRQ_TYPE_EDGE_FALLING: 346 case IRQ_TYPE_EDGE_BOTH: 347 parent_type = type; 348 break; 349 case IRQ_TYPE_LEVEL_HIGH: 350 parent_type = IRQ_TYPE_EDGE_RISING; 351 break; 352 case IRQ_TYPE_LEVEL_LOW: 353 parent_type = IRQ_TYPE_EDGE_FALLING; 354 break; 355 default: 356 return -EINVAL; 357 } 358 359 bank->irq_type[d->hwirq] = type; 360 361 return irq_chip_set_type_parent(d, parent_type); 362}; 363 364static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 365{ 366 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 368 unsigned long flags; 369 int ret; 370 371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 372 if (ret) 373 return ret; 374 375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 376 if (ret) { 377 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 378 irq_data->hwirq); 379 return ret; 380 } 381 382 flags = irqd_get_trigger_type(irq_data); 383 if (flags & IRQ_TYPE_LEVEL_MASK) 384 clk_enable(bank->clk); 385 386 return 0; 387} 388 389static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 390{ 391 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 392 393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK) 394 clk_disable(bank->clk); 395 396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 397} 398 399static void stm32_gpio_irq_unmask(struct irq_data *d) 400{ 401 irq_chip_unmask_parent(d); 402 stm32_gpio_irq_trigger(d); 403} 404 405static struct irq_chip stm32_gpio_irq_chip = { 406 .name = "stm32gpio", 407 .irq_eoi = stm32_gpio_irq_eoi, 408 .irq_ack = irq_chip_ack_parent, 409 .irq_mask = irq_chip_mask_parent, 410 .irq_unmask = stm32_gpio_irq_unmask, 411 .irq_set_type = stm32_gpio_set_type, 412 .irq_set_wake = irq_chip_set_wake_parent, 413 .irq_request_resources = stm32_gpio_irq_request_resources, 414 .irq_release_resources = stm32_gpio_irq_release_resources, 415}; 416 417static int stm32_gpio_domain_translate(struct irq_domain *d, 418 struct irq_fwspec *fwspec, 419 unsigned long *hwirq, 420 unsigned int *type) 421{ 422 if ((fwspec->param_count != 2) || 423 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 424 return -EINVAL; 425 426 *hwirq = fwspec->param[0]; 427 *type = fwspec->param[1]; 428 return 0; 429} 430 431static int stm32_gpio_domain_activate(struct irq_domain *d, 432 struct irq_data *irq_data, bool reserve) 433{ 434 struct stm32_gpio_bank *bank = d->host_data; 435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 436 unsigned long flags; 437 int ret = 0; 438 439 /* 440 * gpio irq mux is shared between several banks, a lock has to be done 441 * to avoid overriding. 442 */ 443 spin_lock_irqsave(&pctl->irqmux_lock, flags); 444 445 if (pctl->hwlock) { 446 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 447 HWSPNLCK_TIMEOUT); 448 if (ret) { 449 dev_err(pctl->dev, "Can't get hwspinlock\n"); 450 goto unlock; 451 } 452 } 453 454 if (pctl->irqmux_map & BIT(irq_data->hwirq)) { 455 dev_err(pctl->dev, "irq line %ld already requested.\n", 456 irq_data->hwirq); 457 ret = -EBUSY; 458 if (pctl->hwlock) 459 hwspin_unlock_in_atomic(pctl->hwlock); 460 goto unlock; 461 } else { 462 pctl->irqmux_map |= BIT(irq_data->hwirq); 463 } 464 465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 466 467 if (pctl->hwlock) 468 hwspin_unlock_in_atomic(pctl->hwlock); 469 470unlock: 471 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 472 return ret; 473} 474 475static void stm32_gpio_domain_deactivate(struct irq_domain *d, 476 struct irq_data *irq_data) 477{ 478 struct stm32_gpio_bank *bank = d->host_data; 479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 480 unsigned long flags; 481 482 spin_lock_irqsave(&pctl->irqmux_lock, flags); 483 pctl->irqmux_map &= ~BIT(irq_data->hwirq); 484 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 485} 486 487static int stm32_gpio_domain_alloc(struct irq_domain *d, 488 unsigned int virq, 489 unsigned int nr_irqs, void *data) 490{ 491 struct stm32_gpio_bank *bank = d->host_data; 492 struct irq_fwspec *fwspec = data; 493 struct irq_fwspec parent_fwspec; 494 irq_hw_number_t hwirq; 495 496 hwirq = fwspec->param[0]; 497 parent_fwspec.fwnode = d->parent->fwnode; 498 parent_fwspec.param_count = 2; 499 parent_fwspec.param[0] = fwspec->param[0]; 500 parent_fwspec.param[1] = fwspec->param[1]; 501 502 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 503 bank); 504 505 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 506} 507 508static const struct irq_domain_ops stm32_gpio_domain_ops = { 509 .translate = stm32_gpio_domain_translate, 510 .alloc = stm32_gpio_domain_alloc, 511 .free = irq_domain_free_irqs_common, 512 .activate = stm32_gpio_domain_activate, 513 .deactivate = stm32_gpio_domain_deactivate, 514}; 515 516/* Pinctrl functions */ 517static struct stm32_pinctrl_group * 518stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 519{ 520 int i; 521 522 for (i = 0; i < pctl->ngroups; i++) { 523 struct stm32_pinctrl_group *grp = pctl->groups + i; 524 525 if (grp->pin == pin) 526 return grp; 527 } 528 529 return NULL; 530} 531 532static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 533 u32 pin_num, u32 fnum) 534{ 535 int i; 536 537 for (i = 0; i < pctl->npins; i++) { 538 const struct stm32_desc_pin *pin = pctl->pins + i; 539 const struct stm32_desc_function *func = pin->functions; 540 541 if (pin->pin.number != pin_num) 542 continue; 543 544 while (func && func->name) { 545 if (func->num == fnum) 546 return true; 547 func++; 548 } 549 550 break; 551 } 552 553 return false; 554} 555 556static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 557 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 558 struct pinctrl_map **map, unsigned *reserved_maps, 559 unsigned *num_maps) 560{ 561 if (*num_maps == *reserved_maps) 562 return -ENOSPC; 563 564 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 565 (*map)[*num_maps].data.mux.group = grp->name; 566 567 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 568 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 569 fnum, pin); 570 return -EINVAL; 571 } 572 573 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 574 (*num_maps)++; 575 576 return 0; 577} 578 579static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 580 struct device_node *node, 581 struct pinctrl_map **map, 582 unsigned *reserved_maps, 583 unsigned *num_maps) 584{ 585 struct stm32_pinctrl *pctl; 586 struct stm32_pinctrl_group *grp; 587 struct property *pins; 588 u32 pinfunc, pin, func; 589 unsigned long *configs; 590 unsigned int num_configs; 591 bool has_config = 0; 592 unsigned reserve = 0; 593 int num_pins, num_funcs, maps_per_pin, i, err = 0; 594 595 pctl = pinctrl_dev_get_drvdata(pctldev); 596 597 pins = of_find_property(node, "pinmux", NULL); 598 if (!pins) { 599 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 600 node); 601 return -EINVAL; 602 } 603 604 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 605 &num_configs); 606 if (err) 607 return err; 608 609 if (num_configs) 610 has_config = 1; 611 612 num_pins = pins->length / sizeof(u32); 613 num_funcs = num_pins; 614 maps_per_pin = 0; 615 if (num_funcs) 616 maps_per_pin++; 617 if (has_config && num_pins >= 1) 618 maps_per_pin++; 619 620 if (!num_pins || !maps_per_pin) { 621 err = -EINVAL; 622 goto exit; 623 } 624 625 reserve = num_pins * maps_per_pin; 626 627 err = pinctrl_utils_reserve_map(pctldev, map, 628 reserved_maps, num_maps, reserve); 629 if (err) 630 goto exit; 631 632 for (i = 0; i < num_pins; i++) { 633 err = of_property_read_u32_index(node, "pinmux", 634 i, &pinfunc); 635 if (err) 636 goto exit; 637 638 pin = STM32_GET_PIN_NO(pinfunc); 639 func = STM32_GET_PIN_FUNC(pinfunc); 640 641 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 642 dev_err(pctl->dev, "invalid function.\n"); 643 err = -EINVAL; 644 goto exit; 645 } 646 647 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 648 if (!grp) { 649 dev_err(pctl->dev, "unable to match pin %d to group\n", 650 pin); 651 err = -EINVAL; 652 goto exit; 653 } 654 655 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 656 reserved_maps, num_maps); 657 if (err) 658 goto exit; 659 660 if (has_config) { 661 err = pinctrl_utils_add_map_configs(pctldev, map, 662 reserved_maps, num_maps, grp->name, 663 configs, num_configs, 664 PIN_MAP_TYPE_CONFIGS_GROUP); 665 if (err) 666 goto exit; 667 } 668 } 669 670exit: 671 kfree(configs); 672 return err; 673} 674 675static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 676 struct device_node *np_config, 677 struct pinctrl_map **map, unsigned *num_maps) 678{ 679 struct device_node *np; 680 unsigned reserved_maps; 681 int ret; 682 683 *map = NULL; 684 *num_maps = 0; 685 reserved_maps = 0; 686 687 for_each_child_of_node(np_config, np) { 688 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 689 &reserved_maps, num_maps); 690 if (ret < 0) { 691 pinctrl_utils_free_map(pctldev, *map, *num_maps); 692 of_node_put(np); 693 return ret; 694 } 695 } 696 697 return 0; 698} 699 700static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 701{ 702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 703 704 return pctl->ngroups; 705} 706 707static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 708 unsigned group) 709{ 710 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 711 712 return pctl->groups[group].name; 713} 714 715static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 716 unsigned group, 717 const unsigned **pins, 718 unsigned *num_pins) 719{ 720 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 721 722 *pins = (unsigned *)&pctl->groups[group].pin; 723 *num_pins = 1; 724 725 return 0; 726} 727 728static const struct pinctrl_ops stm32_pctrl_ops = { 729 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 730 .dt_free_map = pinctrl_utils_free_map, 731 .get_groups_count = stm32_pctrl_get_groups_count, 732 .get_group_name = stm32_pctrl_get_group_name, 733 .get_group_pins = stm32_pctrl_get_group_pins, 734}; 735 736 737/* Pinmux functions */ 738 739static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 740{ 741 return ARRAY_SIZE(stm32_gpio_functions); 742} 743 744static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 745 unsigned selector) 746{ 747 return stm32_gpio_functions[selector]; 748} 749 750static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 751 unsigned function, 752 const char * const **groups, 753 unsigned * const num_groups) 754{ 755 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 756 757 *groups = pctl->grp_names; 758 *num_groups = pctl->ngroups; 759 760 return 0; 761} 762 763static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 764 int pin, u32 mode, u32 alt) 765{ 766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 767 u32 val; 768 int alt_shift = (pin % 8) * 4; 769 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 770 unsigned long flags; 771 int err = 0; 772 773 clk_enable(bank->clk); 774 spin_lock_irqsave(&bank->lock, flags); 775 776 if (pctl->hwlock) { 777 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 778 HWSPNLCK_TIMEOUT); 779 if (err) { 780 dev_err(pctl->dev, "Can't get hwspinlock\n"); 781 goto unlock; 782 } 783 } 784 785 val = readl_relaxed(bank->base + alt_offset); 786 val &= ~GENMASK(alt_shift + 3, alt_shift); 787 val |= (alt << alt_shift); 788 writel_relaxed(val, bank->base + alt_offset); 789 790 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 791 val &= ~GENMASK(pin * 2 + 1, pin * 2); 792 val |= mode << (pin * 2); 793 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 794 795 if (pctl->hwlock) 796 hwspin_unlock_in_atomic(pctl->hwlock); 797 798 stm32_gpio_backup_mode(bank, pin, mode, alt); 799 800unlock: 801 spin_unlock_irqrestore(&bank->lock, flags); 802 clk_disable(bank->clk); 803 804 return err; 805} 806 807void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 808 u32 *alt) 809{ 810 u32 val; 811 int alt_shift = (pin % 8) * 4; 812 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 813 unsigned long flags; 814 815 clk_enable(bank->clk); 816 spin_lock_irqsave(&bank->lock, flags); 817 818 val = readl_relaxed(bank->base + alt_offset); 819 val &= GENMASK(alt_shift + 3, alt_shift); 820 *alt = val >> alt_shift; 821 822 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 823 val &= GENMASK(pin * 2 + 1, pin * 2); 824 *mode = val >> (pin * 2); 825 826 spin_unlock_irqrestore(&bank->lock, flags); 827 clk_disable(bank->clk); 828} 829 830static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 831 unsigned function, 832 unsigned group) 833{ 834 bool ret; 835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 836 struct stm32_pinctrl_group *g = pctl->groups + group; 837 struct pinctrl_gpio_range *range; 838 struct stm32_gpio_bank *bank; 839 u32 mode, alt; 840 int pin; 841 842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 843 if (!ret) { 844 dev_err(pctl->dev, "invalid function %d on group %d .\n", 845 function, group); 846 return -EINVAL; 847 } 848 849 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 850 if (!range) { 851 dev_err(pctl->dev, "No gpio range defined.\n"); 852 return -EINVAL; 853 } 854 855 bank = gpiochip_get_data(range->gc); 856 pin = stm32_gpio_pin(g->pin); 857 858 mode = stm32_gpio_get_mode(function); 859 alt = stm32_gpio_get_alt(function); 860 861 return stm32_pmx_set_mode(bank, pin, mode, alt); 862} 863 864static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 865 struct pinctrl_gpio_range *range, unsigned gpio, 866 bool input) 867{ 868 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 869 int pin = stm32_gpio_pin(gpio); 870 871 return stm32_pmx_set_mode(bank, pin, !input, 0); 872} 873 874static const struct pinmux_ops stm32_pmx_ops = { 875 .get_functions_count = stm32_pmx_get_funcs_cnt, 876 .get_function_name = stm32_pmx_get_func_name, 877 .get_function_groups = stm32_pmx_get_func_groups, 878 .set_mux = stm32_pmx_set_mux, 879 .gpio_set_direction = stm32_pmx_gpio_set_direction, 880 .strict = true, 881}; 882 883/* Pinconf functions */ 884 885static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 886 unsigned offset, u32 drive) 887{ 888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 889 unsigned long flags; 890 u32 val; 891 int err = 0; 892 893 clk_enable(bank->clk); 894 spin_lock_irqsave(&bank->lock, flags); 895 896 if (pctl->hwlock) { 897 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 898 HWSPNLCK_TIMEOUT); 899 if (err) { 900 dev_err(pctl->dev, "Can't get hwspinlock\n"); 901 goto unlock; 902 } 903 } 904 905 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 906 val &= ~BIT(offset); 907 val |= drive << offset; 908 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 909 910 if (pctl->hwlock) 911 hwspin_unlock_in_atomic(pctl->hwlock); 912 913 stm32_gpio_backup_driving(bank, offset, drive); 914 915unlock: 916 spin_unlock_irqrestore(&bank->lock, flags); 917 clk_disable(bank->clk); 918 919 return err; 920} 921 922static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 923 unsigned int offset) 924{ 925 unsigned long flags; 926 u32 val; 927 928 clk_enable(bank->clk); 929 spin_lock_irqsave(&bank->lock, flags); 930 931 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 932 val &= BIT(offset); 933 934 spin_unlock_irqrestore(&bank->lock, flags); 935 clk_disable(bank->clk); 936 937 return (val >> offset); 938} 939 940static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 941 unsigned offset, u32 speed) 942{ 943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 944 unsigned long flags; 945 u32 val; 946 int err = 0; 947 948 clk_enable(bank->clk); 949 spin_lock_irqsave(&bank->lock, flags); 950 951 if (pctl->hwlock) { 952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 953 HWSPNLCK_TIMEOUT); 954 if (err) { 955 dev_err(pctl->dev, "Can't get hwspinlock\n"); 956 goto unlock; 957 } 958 } 959 960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 961 val &= ~GENMASK(offset * 2 + 1, offset * 2); 962 val |= speed << (offset * 2); 963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 964 965 if (pctl->hwlock) 966 hwspin_unlock_in_atomic(pctl->hwlock); 967 968 stm32_gpio_backup_speed(bank, offset, speed); 969 970unlock: 971 spin_unlock_irqrestore(&bank->lock, flags); 972 clk_disable(bank->clk); 973 974 return err; 975} 976 977static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 978 unsigned int offset) 979{ 980 unsigned long flags; 981 u32 val; 982 983 clk_enable(bank->clk); 984 spin_lock_irqsave(&bank->lock, flags); 985 986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 987 val &= GENMASK(offset * 2 + 1, offset * 2); 988 989 spin_unlock_irqrestore(&bank->lock, flags); 990 clk_disable(bank->clk); 991 992 return (val >> (offset * 2)); 993} 994 995static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 996 unsigned offset, u32 bias) 997{ 998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 999 unsigned long flags; 1000 u32 val; 1001 int err = 0; 1002 1003 clk_enable(bank->clk); 1004 spin_lock_irqsave(&bank->lock, flags); 1005 1006 if (pctl->hwlock) { 1007 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 1008 HWSPNLCK_TIMEOUT); 1009 if (err) { 1010 dev_err(pctl->dev, "Can't get hwspinlock\n"); 1011 goto unlock; 1012 } 1013 } 1014 1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1016 val &= ~GENMASK(offset * 2 + 1, offset * 2); 1017 val |= bias << (offset * 2); 1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 1019 1020 if (pctl->hwlock) 1021 hwspin_unlock_in_atomic(pctl->hwlock); 1022 1023 stm32_gpio_backup_bias(bank, offset, bias); 1024 1025unlock: 1026 spin_unlock_irqrestore(&bank->lock, flags); 1027 clk_disable(bank->clk); 1028 1029 return err; 1030} 1031 1032static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1033 unsigned int offset) 1034{ 1035 unsigned long flags; 1036 u32 val; 1037 1038 clk_enable(bank->clk); 1039 spin_lock_irqsave(&bank->lock, flags); 1040 1041 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1042 val &= GENMASK(offset * 2 + 1, offset * 2); 1043 1044 spin_unlock_irqrestore(&bank->lock, flags); 1045 clk_disable(bank->clk); 1046 1047 return (val >> (offset * 2)); 1048} 1049 1050static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1051 unsigned int offset, bool dir) 1052{ 1053 unsigned long flags; 1054 u32 val; 1055 1056 clk_enable(bank->clk); 1057 spin_lock_irqsave(&bank->lock, flags); 1058 1059 if (dir) 1060 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1061 BIT(offset)); 1062 else 1063 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1064 BIT(offset)); 1065 1066 spin_unlock_irqrestore(&bank->lock, flags); 1067 clk_disable(bank->clk); 1068 1069 return val; 1070} 1071 1072static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1073 unsigned int pin, enum pin_config_param param, 1074 enum pin_config_param arg) 1075{ 1076 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1077 struct pinctrl_gpio_range *range; 1078 struct stm32_gpio_bank *bank; 1079 int offset, ret = 0; 1080 1081 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1082 if (!range) { 1083 dev_err(pctl->dev, "No gpio range defined.\n"); 1084 return -EINVAL; 1085 } 1086 1087 bank = gpiochip_get_data(range->gc); 1088 offset = stm32_gpio_pin(pin); 1089 1090 switch (param) { 1091 case PIN_CONFIG_DRIVE_PUSH_PULL: 1092 ret = stm32_pconf_set_driving(bank, offset, 0); 1093 break; 1094 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1095 ret = stm32_pconf_set_driving(bank, offset, 1); 1096 break; 1097 case PIN_CONFIG_SLEW_RATE: 1098 ret = stm32_pconf_set_speed(bank, offset, arg); 1099 break; 1100 case PIN_CONFIG_BIAS_DISABLE: 1101 ret = stm32_pconf_set_bias(bank, offset, 0); 1102 break; 1103 case PIN_CONFIG_BIAS_PULL_UP: 1104 ret = stm32_pconf_set_bias(bank, offset, 1); 1105 break; 1106 case PIN_CONFIG_BIAS_PULL_DOWN: 1107 ret = stm32_pconf_set_bias(bank, offset, 2); 1108 break; 1109 case PIN_CONFIG_OUTPUT: 1110 __stm32_gpio_set(bank, offset, arg); 1111 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1112 break; 1113 default: 1114 ret = -ENOTSUPP; 1115 } 1116 1117 return ret; 1118} 1119 1120static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1121 unsigned group, 1122 unsigned long *config) 1123{ 1124 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1125 1126 *config = pctl->groups[group].config; 1127 1128 return 0; 1129} 1130 1131static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1132 unsigned long *configs, unsigned num_configs) 1133{ 1134 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1135 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1136 int i, ret; 1137 1138 for (i = 0; i < num_configs; i++) { 1139 mutex_lock(&pctldev->mutex); 1140 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1141 pinconf_to_config_param(configs[i]), 1142 pinconf_to_config_argument(configs[i])); 1143 mutex_unlock(&pctldev->mutex); 1144 if (ret < 0) 1145 return ret; 1146 1147 g->config = configs[i]; 1148 } 1149 1150 return 0; 1151} 1152 1153static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1154 unsigned long *configs, unsigned int num_configs) 1155{ 1156 int i, ret; 1157 1158 for (i = 0; i < num_configs; i++) { 1159 ret = stm32_pconf_parse_conf(pctldev, pin, 1160 pinconf_to_config_param(configs[i]), 1161 pinconf_to_config_argument(configs[i])); 1162 if (ret < 0) 1163 return ret; 1164 } 1165 1166 return 0; 1167} 1168 1169static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1170 struct seq_file *s, 1171 unsigned int pin) 1172{ 1173 struct pinctrl_gpio_range *range; 1174 struct stm32_gpio_bank *bank; 1175 int offset; 1176 u32 mode, alt, drive, speed, bias; 1177 static const char * const modes[] = { 1178 "input", "output", "alternate", "analog" }; 1179 static const char * const speeds[] = { 1180 "low", "medium", "high", "very high" }; 1181 static const char * const biasing[] = { 1182 "floating", "pull up", "pull down", "" }; 1183 bool val; 1184 1185 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1186 if (!range) 1187 return; 1188 1189 bank = gpiochip_get_data(range->gc); 1190 offset = stm32_gpio_pin(pin); 1191 1192 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1193 bias = stm32_pconf_get_bias(bank, offset); 1194 1195 seq_printf(s, "%s ", modes[mode]); 1196 1197 switch (mode) { 1198 /* input */ 1199 case 0: 1200 val = stm32_pconf_get(bank, offset, true); 1201 seq_printf(s, "- %s - %s", 1202 val ? "high" : "low", 1203 biasing[bias]); 1204 break; 1205 1206 /* output */ 1207 case 1: 1208 drive = stm32_pconf_get_driving(bank, offset); 1209 speed = stm32_pconf_get_speed(bank, offset); 1210 val = stm32_pconf_get(bank, offset, false); 1211 seq_printf(s, "- %s - %s - %s - %s %s", 1212 val ? "high" : "low", 1213 drive ? "open drain" : "push pull", 1214 biasing[bias], 1215 speeds[speed], "speed"); 1216 break; 1217 1218 /* alternate */ 1219 case 2: 1220 drive = stm32_pconf_get_driving(bank, offset); 1221 speed = stm32_pconf_get_speed(bank, offset); 1222 seq_printf(s, "%d - %s - %s - %s %s", alt, 1223 drive ? "open drain" : "push pull", 1224 biasing[bias], 1225 speeds[speed], "speed"); 1226 break; 1227 1228 /* analog */ 1229 case 3: 1230 break; 1231 } 1232} 1233 1234static const struct pinconf_ops stm32_pconf_ops = { 1235 .pin_config_group_get = stm32_pconf_group_get, 1236 .pin_config_group_set = stm32_pconf_group_set, 1237 .pin_config_set = stm32_pconf_set, 1238 .pin_config_dbg_show = stm32_pconf_dbg_show, 1239}; 1240 1241static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1242 struct device_node *np) 1243{ 1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1245 int bank_ioport_nr; 1246 struct pinctrl_gpio_range *range = &bank->range; 1247 struct of_phandle_args args; 1248 struct device *dev = pctl->dev; 1249 struct resource res; 1250 int npins = STM32_GPIO_PINS_PER_BANK; 1251 int bank_nr, err, i = 0; 1252 1253 if (!IS_ERR(bank->rstc)) 1254 reset_control_deassert(bank->rstc); 1255 1256 if (of_address_to_resource(np, 0, &res)) 1257 return -ENODEV; 1258 1259 bank->base = devm_ioremap_resource(dev, &res); 1260 if (IS_ERR(bank->base)) 1261 return PTR_ERR(bank->base); 1262 1263 err = clk_prepare(bank->clk); 1264 if (err) { 1265 dev_err(dev, "failed to prepare clk (%d)\n", err); 1266 return err; 1267 } 1268 1269 bank->gpio_chip = stm32_gpio_template; 1270 1271 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1272 1273 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) { 1274 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1275 bank->gpio_chip.base = args.args[1]; 1276 1277 /* get the last defined gpio line (offset + nb of pins) */ 1278 npins = args.args[0] + args.args[2]; 1279 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args)) 1280 npins = max(npins, (int)(args.args[0] + args.args[2])); 1281 } else { 1282 bank_nr = pctl->nbanks; 1283 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1284 range->name = bank->gpio_chip.label; 1285 range->id = bank_nr; 1286 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1287 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1288 range->npins = npins; 1289 range->gc = &bank->gpio_chip; 1290 pinctrl_add_gpio_range(pctl->pctl_dev, 1291 &pctl->banks[bank_nr].range); 1292 } 1293 1294 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1295 bank_ioport_nr = bank_nr; 1296 1297 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1298 1299 bank->gpio_chip.ngpio = npins; 1300 bank->gpio_chip.of_node = np; 1301 bank->gpio_chip.parent = dev; 1302 bank->bank_nr = bank_nr; 1303 bank->bank_ioport_nr = bank_ioport_nr; 1304 spin_lock_init(&bank->lock); 1305 1306 if (pctl->domain) { 1307 /* create irq hierarchical domain */ 1308 bank->fwnode = of_node_to_fwnode(np); 1309 1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, 1311 bank->fwnode, &stm32_gpio_domain_ops, 1312 bank); 1313 1314 if (!bank->domain) 1315 return -ENODEV; 1316 } 1317 1318 err = gpiochip_add_data(&bank->gpio_chip, bank); 1319 if (err) { 1320 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1321 return err; 1322 } 1323 1324 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1325 return 0; 1326} 1327 1328static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np) 1329{ 1330 struct device_node *parent; 1331 struct irq_domain *domain; 1332 1333 if (!of_find_property(np, "interrupt-parent", NULL)) 1334 return NULL; 1335 1336 parent = of_irq_find_parent(np); 1337 if (!parent) 1338 return ERR_PTR(-ENXIO); 1339 1340 domain = irq_find_host(parent); 1341 of_node_put(parent); 1342 if (!domain) 1343 /* domain not registered yet */ 1344 return ERR_PTR(-EPROBE_DEFER); 1345 1346 return domain; 1347} 1348 1349static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1350 struct stm32_pinctrl *pctl) 1351{ 1352 struct device_node *np = pdev->dev.of_node; 1353 struct device *dev = &pdev->dev; 1354 struct regmap *rm; 1355 int offset, ret, i; 1356 int mask, mask_width; 1357 1358 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1359 if (IS_ERR(pctl->regmap)) 1360 return PTR_ERR(pctl->regmap); 1361 1362 rm = pctl->regmap; 1363 1364 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1365 if (ret) 1366 return ret; 1367 1368 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1369 if (ret) 1370 mask = SYSCFG_IRQMUX_MASK; 1371 1372 mask_width = fls(mask); 1373 1374 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1375 struct reg_field mux; 1376 1377 mux.reg = offset + (i / 4) * 4; 1378 mux.lsb = (i % 4) * mask_width; 1379 mux.msb = mux.lsb + mask_width - 1; 1380 1381 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1382 i, mux.reg, mux.lsb, mux.msb); 1383 1384 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1385 if (IS_ERR(pctl->irqmux[i])) 1386 return PTR_ERR(pctl->irqmux[i]); 1387 } 1388 1389 return 0; 1390} 1391 1392static int stm32_pctrl_build_state(struct platform_device *pdev) 1393{ 1394 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1395 int i; 1396 1397 pctl->ngroups = pctl->npins; 1398 1399 /* Allocate groups */ 1400 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1401 sizeof(*pctl->groups), GFP_KERNEL); 1402 if (!pctl->groups) 1403 return -ENOMEM; 1404 1405 /* We assume that one pin is one group, use pin name as group name. */ 1406 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1407 sizeof(*pctl->grp_names), GFP_KERNEL); 1408 if (!pctl->grp_names) 1409 return -ENOMEM; 1410 1411 for (i = 0; i < pctl->npins; i++) { 1412 const struct stm32_desc_pin *pin = pctl->pins + i; 1413 struct stm32_pinctrl_group *group = pctl->groups + i; 1414 1415 group->name = pin->pin.name; 1416 group->pin = pin->pin.number; 1417 pctl->grp_names[i] = pin->pin.name; 1418 } 1419 1420 return 0; 1421} 1422 1423static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1424 struct stm32_desc_pin *pins) 1425{ 1426 const struct stm32_desc_pin *p; 1427 int i, nb_pins_available = 0; 1428 1429 for (i = 0; i < pctl->match_data->npins; i++) { 1430 p = pctl->match_data->pins + i; 1431 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1432 continue; 1433 pins->pin = p->pin; 1434 pins->functions = p->functions; 1435 pins++; 1436 nb_pins_available++; 1437 } 1438 1439 pctl->npins = nb_pins_available; 1440 1441 return 0; 1442} 1443 1444static void stm32_pctl_get_package(struct device_node *np, 1445 struct stm32_pinctrl *pctl) 1446{ 1447 if (of_property_read_u32(np, "st,package", &pctl->pkg)) { 1448 pctl->pkg = 0; 1449 dev_warn(pctl->dev, "No package detected, use default one\n"); 1450 } else { 1451 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1452 } 1453} 1454 1455int stm32_pctl_probe(struct platform_device *pdev) 1456{ 1457 struct device_node *np = pdev->dev.of_node; 1458 struct device_node *child; 1459 const struct of_device_id *match; 1460 struct device *dev = &pdev->dev; 1461 struct stm32_pinctrl *pctl; 1462 struct pinctrl_pin_desc *pins; 1463 int i, ret, hwlock_id, banks = 0; 1464 1465 if (!np) 1466 return -EINVAL; 1467 1468 match = of_match_device(dev->driver->of_match_table, dev); 1469 if (!match || !match->data) 1470 return -EINVAL; 1471 1472 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1473 dev_err(dev, "only support pins-are-numbered format\n"); 1474 return -EINVAL; 1475 } 1476 1477 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1478 if (!pctl) 1479 return -ENOMEM; 1480 1481 platform_set_drvdata(pdev, pctl); 1482 1483 /* check for IRQ controller (may require deferred probe) */ 1484 pctl->domain = stm32_pctrl_get_irq_domain(np); 1485 if (IS_ERR(pctl->domain)) 1486 return PTR_ERR(pctl->domain); 1487 if (!pctl->domain) 1488 dev_warn(dev, "pinctrl without interrupt support\n"); 1489 1490 /* hwspinlock is optional */ 1491 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1492 if (hwlock_id < 0) { 1493 if (hwlock_id == -EPROBE_DEFER) 1494 return hwlock_id; 1495 } else { 1496 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1497 } 1498 1499 spin_lock_init(&pctl->irqmux_lock); 1500 1501 pctl->dev = dev; 1502 pctl->match_data = match->data; 1503 1504 /* get package information */ 1505 stm32_pctl_get_package(np, pctl); 1506 1507 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1508 sizeof(*pctl->pins), GFP_KERNEL); 1509 if (!pctl->pins) 1510 return -ENOMEM; 1511 1512 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1513 if (ret) 1514 return ret; 1515 1516 ret = stm32_pctrl_build_state(pdev); 1517 if (ret) { 1518 dev_err(dev, "build state failed: %d\n", ret); 1519 return -EINVAL; 1520 } 1521 1522 if (pctl->domain) { 1523 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1524 if (ret) 1525 return ret; 1526 } 1527 1528 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1529 GFP_KERNEL); 1530 if (!pins) 1531 return -ENOMEM; 1532 1533 for (i = 0; i < pctl->npins; i++) 1534 pins[i] = pctl->pins[i].pin; 1535 1536 pctl->pctl_desc.name = dev_name(&pdev->dev); 1537 pctl->pctl_desc.owner = THIS_MODULE; 1538 pctl->pctl_desc.pins = pins; 1539 pctl->pctl_desc.npins = pctl->npins; 1540 pctl->pctl_desc.link_consumers = true; 1541 pctl->pctl_desc.confops = &stm32_pconf_ops; 1542 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1543 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1544 pctl->dev = &pdev->dev; 1545 1546 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1547 pctl); 1548 1549 if (IS_ERR(pctl->pctl_dev)) { 1550 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1551 return PTR_ERR(pctl->pctl_dev); 1552 } 1553 1554 for_each_available_child_of_node(np, child) 1555 if (of_property_read_bool(child, "gpio-controller")) 1556 banks++; 1557 1558 if (!banks) { 1559 dev_err(dev, "at least one GPIO bank is required\n"); 1560 return -EINVAL; 1561 } 1562 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1563 GFP_KERNEL); 1564 if (!pctl->banks) 1565 return -ENOMEM; 1566 1567 i = 0; 1568 for_each_available_child_of_node(np, child) { 1569 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1570 1571 if (of_property_read_bool(child, "gpio-controller")) { 1572 bank->rstc = of_reset_control_get_exclusive(child, 1573 NULL); 1574 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) 1575 return -EPROBE_DEFER; 1576 1577 bank->clk = of_clk_get_by_name(child, NULL); 1578 if (IS_ERR(bank->clk)) { 1579 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) 1580 dev_err(dev, 1581 "failed to get clk (%ld)\n", 1582 PTR_ERR(bank->clk)); 1583 return PTR_ERR(bank->clk); 1584 } 1585 i++; 1586 } 1587 } 1588 1589 for_each_available_child_of_node(np, child) { 1590 if (of_property_read_bool(child, "gpio-controller")) { 1591 ret = stm32_gpiolib_register_bank(pctl, child); 1592 if (ret) { 1593 of_node_put(child); 1594 return ret; 1595 } 1596 1597 pctl->nbanks++; 1598 } 1599 } 1600 1601 dev_info(dev, "Pinctrl STM32 initialized\n"); 1602 1603 return 0; 1604} 1605 1606static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1607 struct stm32_pinctrl *pctl, u32 pin) 1608{ 1609 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1610 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1611 struct pinctrl_gpio_range *range; 1612 struct stm32_gpio_bank *bank; 1613 bool pin_is_irq; 1614 int ret; 1615 1616 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1617 if (!range) 1618 return 0; 1619 1620 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1621 1622 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1623 return 0; 1624 1625 bank = gpiochip_get_data(range->gc); 1626 1627 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1628 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1629 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1630 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1631 1632 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1633 if (ret) 1634 return ret; 1635 1636 if (mode == 1) { 1637 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1638 val = val >> STM32_GPIO_BKP_VAL; 1639 __stm32_gpio_set(bank, offset, val); 1640 } 1641 1642 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1643 val >>= STM32_GPIO_BKP_TYPE; 1644 ret = stm32_pconf_set_driving(bank, offset, val); 1645 if (ret) 1646 return ret; 1647 1648 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1649 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1650 ret = stm32_pconf_set_speed(bank, offset, val); 1651 if (ret) 1652 return ret; 1653 1654 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1655 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1656 ret = stm32_pconf_set_bias(bank, offset, val); 1657 if (ret) 1658 return ret; 1659 1660 if (pin_is_irq) 1661 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1662 1663 return 0; 1664} 1665 1666int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1667{ 1668 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1669 struct stm32_pinctrl_group *g = pctl->groups; 1670 int i; 1671 1672 for (i = 0; i < pctl->ngroups; i++, g++) 1673 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1674 1675 return 0; 1676} 1677